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From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
To: qemu-devel@nongnu.org, laurent@vivier.eu
Subject: [PATCH v2 2/9] escc: reset register values to zero in escc_reset()
Date: Thu,  2 Sep 2021 11:21:58 +0100	[thread overview]
Message-ID: <20210902102205.7554-3-mark.cave-ayland@ilande.co.uk> (raw)
In-Reply-To: <20210902102205.7554-1-mark.cave-ayland@ilande.co.uk>

This is to ensure that a device reset always returns the ESCC to a known state.

Note that this is currently redundant with the same code in escc_reset_chn()
but that will change shortly.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
 hw/char/escc.c | 19 +++++++++++++++++--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/hw/char/escc.c b/hw/char/escc.c
index c87ecd59d8..b0d3b92dc1 100644
--- a/hw/char/escc.c
+++ b/hw/char/escc.c
@@ -300,9 +300,24 @@ static void escc_reset_chn(ESCCChannelState *s)
 static void escc_reset(DeviceState *d)
 {
     ESCCState *s = ESCC(d);
+    int i, j;
 
-    escc_reset_chn(&s->chn[0]);
-    escc_reset_chn(&s->chn[1]);
+    for (i = 0; i < 2; i++) {
+        ESCCChannelState *cs = &s->chn[i];
+
+        /*
+         * According to the ESCC datasheet "Miscellaneous Questions" section
+         * on page 384, the values of the ESCC registers are not guaranteed on
+         * power-on until an explicit hardware or software reset has been
+         * issued. For now we zero the registers so that a device reset always
+         * returns the emulated device to a fixed state.
+         */
+        for (j = 0; j < ESCC_SERIAL_REGS; j++) {
+            cs->rregs[j] = 0;
+            cs->wregs[j] = 0;
+        }
+        escc_reset_chn(cs);
+    }
 }
 
 static inline void set_rxint(ESCCChannelState *s)
-- 
2.20.1



  parent reply	other threads:[~2021-09-02 10:24 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-02 10:21 [PATCH v2 0/9] escc: fix reset and R_STATUS when SDLC mode is enabled Mark Cave-Ayland
2021-09-02 10:21 ` [PATCH v2 1/9] escc: checkpatch fixes Mark Cave-Ayland
2021-09-02 10:21 ` Mark Cave-Ayland [this message]
2021-09-02 10:21 ` [PATCH v2 3/9] escc: introduce escc_soft_reset_chn() for software reset Mark Cave-Ayland
2021-09-02 10:22 ` [PATCH v2 4/9] escc: introduce escc_hard_reset_chn() for hardware reset Mark Cave-Ayland
2021-09-02 15:42   ` Peter Maydell
2021-09-02 17:46     ` Mark Cave-Ayland
2021-09-02 19:31       ` Peter Maydell
2021-09-02 19:36         ` Mark Cave-Ayland
2021-09-02 10:22 ` [PATCH v2 5/9] escc: implement soft reset as described in the datasheet Mark Cave-Ayland
2021-09-02 10:22 ` [PATCH v2 6/9] escc: implement hard " Mark Cave-Ayland
2021-09-02 10:22 ` [PATCH v2 7/9] escc: remove register changes from escc_reset_chn() Mark Cave-Ayland
2021-09-02 10:22 ` [PATCH v2 8/9] escc: re-use escc_reset_chn() for hard and soft reset Mark Cave-Ayland
2021-09-02 10:26   ` Philippe Mathieu-Daudé
2021-09-02 10:22 ` [PATCH v2 9/9] escc: fix STATUS_SYNC bit in R_STATUS register Mark Cave-Ayland

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