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From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
To: qemu-devel@nongnu.org, laurent@vivier.eu
Subject: [PATCH v2 3/9] escc: introduce escc_soft_reset_chn() for software reset
Date: Thu,  2 Sep 2021 11:21:59 +0100	[thread overview]
Message-ID: <20210902102205.7554-4-mark.cave-ayland@ilande.co.uk> (raw)
In-Reply-To: <20210902102205.7554-1-mark.cave-ayland@ilande.co.uk>

This new software reset function is to be called when the appropriate channel
software reset bit is written to register WR9. Its initial implementation is
the same as the existing escc_reset_chn() function used for device reset.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
 hw/char/escc.c | 38 ++++++++++++++++++++++++++++++++++++--
 1 file changed, 36 insertions(+), 2 deletions(-)

diff --git a/hw/char/escc.c b/hw/char/escc.c
index b0d3b92dc1..935ec1aef6 100644
--- a/hw/char/escc.c
+++ b/hw/char/escc.c
@@ -297,6 +297,40 @@ static void escc_reset_chn(ESCCChannelState *s)
     clear_queue(s);
 }
 
+static void escc_soft_reset_chn(ESCCChannelState *s)
+{
+    int i;
+
+    s->reg = 0;
+    for (i = 0; i < ESCC_SERIAL_REGS; i++) {
+        s->rregs[i] = 0;
+        s->wregs[i] = 0;
+    }
+    /* 1X divisor, 1 stop bit, no parity */
+    s->wregs[W_TXCTRL1] = TXCTRL1_1STOP;
+    s->wregs[W_MINTR] = MINTR_RST_ALL;
+    /* Synch mode tx clock = TRxC */
+    s->wregs[W_CLOCK] = CLOCK_TRXC;
+    /* PLL disabled */
+    s->wregs[W_MISC2] = MISC2_PLLDIS;
+    /* Enable most interrupts */
+    s->wregs[W_EXTINT] = EXTINT_DCD | EXTINT_SYNCINT | EXTINT_CTSINT |
+                         EXTINT_TXUNDRN | EXTINT_BRKINT;
+    if (s->disabled) {
+        s->rregs[R_STATUS] = STATUS_TXEMPTY | STATUS_DCD | STATUS_SYNC |
+                             STATUS_CTS | STATUS_TXUNDRN;
+    } else {
+        s->rregs[R_STATUS] = STATUS_TXEMPTY | STATUS_TXUNDRN;
+    }
+    s->rregs[R_SPEC] = SPEC_BITS8 | SPEC_ALLSENT;
+
+    s->rx = s->tx = 0;
+    s->rxint = s->txint = 0;
+    s->rxint_under_svc = s->txint_under_svc = 0;
+    s->e0_mode = s->led_mode = s->caps_lock_mode = s->num_lock_mode = 0;
+    clear_queue(s);
+}
+
 static void escc_reset(DeviceState *d)
 {
     ESCCState *s = ESCC(d);
@@ -547,10 +581,10 @@ static void escc_mem_write(void *opaque, hwaddr addr,
             default:
                 break;
             case MINTR_RST_B:
-                escc_reset_chn(&serial->chn[0]);
+                escc_soft_reset_chn(&serial->chn[0]);
                 return;
             case MINTR_RST_A:
-                escc_reset_chn(&serial->chn[1]);
+                escc_soft_reset_chn(&serial->chn[1]);
                 return;
             case MINTR_RST_ALL:
                 escc_reset(DEVICE(serial));
-- 
2.20.1



  parent reply	other threads:[~2021-09-02 10:27 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-02 10:21 [PATCH v2 0/9] escc: fix reset and R_STATUS when SDLC mode is enabled Mark Cave-Ayland
2021-09-02 10:21 ` [PATCH v2 1/9] escc: checkpatch fixes Mark Cave-Ayland
2021-09-02 10:21 ` [PATCH v2 2/9] escc: reset register values to zero in escc_reset() Mark Cave-Ayland
2021-09-02 10:21 ` Mark Cave-Ayland [this message]
2021-09-02 10:22 ` [PATCH v2 4/9] escc: introduce escc_hard_reset_chn() for hardware reset Mark Cave-Ayland
2021-09-02 15:42   ` Peter Maydell
2021-09-02 17:46     ` Mark Cave-Ayland
2021-09-02 19:31       ` Peter Maydell
2021-09-02 19:36         ` Mark Cave-Ayland
2021-09-02 10:22 ` [PATCH v2 5/9] escc: implement soft reset as described in the datasheet Mark Cave-Ayland
2021-09-02 10:22 ` [PATCH v2 6/9] escc: implement hard " Mark Cave-Ayland
2021-09-02 10:22 ` [PATCH v2 7/9] escc: remove register changes from escc_reset_chn() Mark Cave-Ayland
2021-09-02 10:22 ` [PATCH v2 8/9] escc: re-use escc_reset_chn() for hard and soft reset Mark Cave-Ayland
2021-09-02 10:26   ` Philippe Mathieu-Daudé
2021-09-02 10:22 ` [PATCH v2 9/9] escc: fix STATUS_SYNC bit in R_STATUS register Mark Cave-Ayland

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