From: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>,
CQ Tang <cq.tang@intel.com>,
Matt Roper <matthew.d.roper@intel.com>
Subject: [Intel-gfx] [PATCH V4 1/6] drm/i915/gt: Add support of mocs propagation
Date: Fri, 3 Sep 2021 00:26:30 +0530 [thread overview]
Message-ID: <20210902185635.290538-2-ayaz.siddiqui@intel.com> (raw)
In-Reply-To: <20210902185635.290538-1-ayaz.siddiqui@intel.com>
Now there are lots of Command and registers that require mocs index
programming.
So propagating mocs_index from mocs to gt so that it can be
used directly without having platform-specific checks.
Cc: CQ Tang<cq.tang@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt.c | 2 ++
drivers/gpu/drm/i915/gt/intel_gt_types.h | 4 ++++
drivers/gpu/drm/i915/gt/intel_mocs.c | 13 +++++++++++++
drivers/gpu/drm/i915/gt/intel_mocs.h | 1 +
4 files changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 62d40c9866427..2aeaae036a6f8 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -682,6 +682,8 @@ int intel_gt_init(struct intel_gt *gt)
goto err_pm;
}
+ set_mocs_index(gt);
+
err = intel_engines_init(gt);
if (err)
goto err_engines;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index a81e21bf1bd1a..88601a2d2c229 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -192,6 +192,10 @@ struct intel_gt {
unsigned long mslice_mask;
} info;
+
+ struct i915_mocs_index_gt {
+ u8 uc_index;
+ } mocs;
};
enum intel_gt_scratch_field {
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.c b/drivers/gpu/drm/i915/gt/intel_mocs.c
index 582c4423b95d6..7ccac15d9a331 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.c
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.c
@@ -22,6 +22,7 @@ struct drm_i915_mocs_table {
unsigned int size;
unsigned int n_entries;
const struct drm_i915_mocs_entry *table;
+ u8 uc_index;
};
/* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
@@ -340,14 +341,18 @@ static unsigned int get_mocs_settings(const struct drm_i915_private *i915,
{
unsigned int flags;
+ memset(table, 0, sizeof(struct drm_i915_mocs_table));
+
if (IS_DG1(i915)) {
table->size = ARRAY_SIZE(dg1_mocs_table);
table->table = dg1_mocs_table;
+ table->uc_index = 1;
table->n_entries = GEN9_NUM_MOCS_ENTRIES;
} else if (GRAPHICS_VER(i915) >= 12) {
table->size = ARRAY_SIZE(tgl_mocs_table);
table->table = tgl_mocs_table;
table->n_entries = GEN9_NUM_MOCS_ENTRIES;
+ table->uc_index = 3;
} else if (GRAPHICS_VER(i915) == 11) {
table->size = ARRAY_SIZE(icl_mocs_table);
table->table = icl_mocs_table;
@@ -504,6 +509,14 @@ static u32 global_mocs_offset(void)
return i915_mmio_reg_offset(GEN12_GLOBAL_MOCS(0));
}
+void set_mocs_index(struct intel_gt *gt)
+{
+ struct drm_i915_mocs_table table;
+
+ get_mocs_settings(gt->i915, &table);
+ gt->mocs.uc_index = table.uc_index;
+}
+
void intel_mocs_init(struct intel_gt *gt)
{
struct drm_i915_mocs_table table;
diff --git a/drivers/gpu/drm/i915/gt/intel_mocs.h b/drivers/gpu/drm/i915/gt/intel_mocs.h
index d83274f5163bd..8a09d64b115f7 100644
--- a/drivers/gpu/drm/i915/gt/intel_mocs.h
+++ b/drivers/gpu/drm/i915/gt/intel_mocs.h
@@ -36,5 +36,6 @@ struct intel_gt;
void intel_mocs_init(struct intel_gt *gt);
void intel_mocs_init_engine(struct intel_engine_cs *engine);
+void set_mocs_index(struct intel_gt *gt);
#endif
--
2.26.2
next prev parent reply other threads:[~2021-09-02 19:00 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-02 18:56 [Intel-gfx] [PATCH V4 0/6] drm/i915/gt: Initialize unused MOCS entries to L3_WB Ayaz A Siddiqui
2021-09-02 18:56 ` Ayaz A Siddiqui [this message]
2021-09-02 20:19 ` [Intel-gfx] [PATCH V4 1/6] drm/i915/gt: Add support of mocs propagation Matt Roper
2021-09-02 18:56 ` [Intel-gfx] [PATCH V4 2/6] drm/i915/gt: Set CMD_CCTL to UC for Gen12 Onward Ayaz A Siddiqui
2021-09-02 20:35 ` Matt Roper
2021-09-02 22:59 ` Lucas De Marchi
2021-09-02 23:26 ` Matt Roper
2021-09-02 18:56 ` [Intel-gfx] [PATCH V4 3/6] drm/i915/gt: Set BLIT_CCTL reg to un-cached Ayaz A Siddiqui
2021-09-02 20:45 ` Matt Roper
2021-09-02 18:56 ` [Intel-gfx] [PATCH V4 4/6] drm/i915/gt: Initialize unused MOCS entries with device specific values Ayaz A Siddiqui
2021-09-02 20:51 ` Matt Roper
2021-09-02 18:56 ` [Intel-gfx] [PATCH V4 5/6] drm/i915/gt: Initialize L3CC table in mocs init Ayaz A Siddiqui
2021-09-02 21:01 ` Matt Roper
2021-09-02 18:56 ` [Intel-gfx] [PATCH V4 6/6] drm/i915/selftest: Remove Renderer class check for l3cc table read Ayaz A Siddiqui
2021-09-02 21:07 ` Matt Roper
2021-09-02 19:28 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/gt: Initialize unused MOCS entries to L3_WB Patchwork
2021-09-02 20:10 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-09-03 5:21 ` Siddiqui, Ayaz A
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210902185635.290538-2-ayaz.siddiqui@intel.com \
--to=ayaz.siddiqui@intel.com \
--cc=cq.tang@intel.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=matthew.d.roper@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.