Re: [Intel-gfx] [PATCH V4 2/6] drm/i915/gt: Set CMD_CCTL to UC for Gen12 Onward

[Lucas De Marchi <lucas.demarchi@intel.com>]

On Fri, Sep 03, 2021 at 12:26:31AM +0530, Ayaz A Siddiqui wrote:
>Cache-control registers for Command Stream(CMD_CCTL) are used
>to set catchability for memory writes and reads outputted by
>Command Streamers on Gen12 onward platforms.
>
>These registers need to point un-cached(UC) MOCS index.
>
>Cc: Matt Roper <matthew.d.roper@intel.com>
>Signed-off-by: Ayaz A Siddiqui <ayaz.siddiqui@intel.com>
>---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 26 +++++++++++++++++++++
> drivers/gpu/drm/i915/i915_reg.h             | 17 ++++++++++++++
> 2 files changed, 43 insertions(+)
>
>diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>index 94e1937f8d296..38c66765ff94c 100644
>--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>@@ -1640,6 +1640,30 @@ void intel_engine_apply_whitelist(struct intel_engine_cs *engine)
> 				   i915_mmio_reg_offset(RING_NOPID(base)));
> }
>
>+/*
>+ * engine_fake_wa_init(), a place holder to program the registers
>+ * which are not part of a workaround.
>+ * Adding programming of those register inside workaround will
>+ * allow utilizing wa framework to proper application and verification.
>+ */
>+static void
>+engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>+{
>+	u8 mocs;
>+
>+	if (GRAPHICS_VER(engine->i915) >= 12) {

this is including TGL. Shouldn't TGL be the exception here?

Lucas De Marchi