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From: Swapnil Jakhade <sjakhade@cadence.com>
To: <vkoul@kernel.org>, <kishon@ti.com>, <robh+dt@kernel.org>,
	<p.zabel@pengutronix.de>, <linux-phy@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>
Cc: <mparab@cadence.com>, <sjakhade@cadence.com>, <lokeshvutla@ti.com>
Subject: [PATCH 03/14] dt-bindings: phy: cadence-sierra: Add binding to specify SSC mode
Date: Fri, 3 Sep 2021 07:00:43 +0200	[thread overview]
Message-ID: <20210903050054.25627-4-sjakhade@cadence.com> (raw)
In-Reply-To: <20210903050054.25627-1-sjakhade@cadence.com>

Add binding to specify Spread Spectrum Clocking mode used.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
---
 .../devicetree/bindings/phy/phy-cadence-sierra.yaml      | 9 +++++++++
 include/dt-bindings/phy/phy-cadence.h                    | 4 ++++
 2 files changed, 13 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
index e71b32c9c0d1..a9e227d8b076 100644
--- a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
@@ -113,6 +113,15 @@ patternProperties:
         minimum: 1
         maximum: 16
 
+      cdns,ssc-mode:
+        description:
+          Specifies the Spread Spectrum Clocking mode used. It can be NO_SSC,
+          EXTERNAL_SSC or INTERNAL_SSC.
+          Refer include/dt-bindings/phy/phy-cadence.h for the constants to be used.
+        $ref: /schemas/types.yaml#/definitions/uint32
+        enum: [0, 1, 2]
+        default: 1
+
     required:
       - reg
       - resets
diff --git a/include/dt-bindings/phy/phy-cadence.h b/include/dt-bindings/phy/phy-cadence.h
index 4652bcb86265..0122c6067b17 100644
--- a/include/dt-bindings/phy/phy-cadence.h
+++ b/include/dt-bindings/phy/phy-cadence.h
@@ -17,4 +17,8 @@
 #define CDNS_SIERRA_PLL_CMNLC		0
 #define CDNS_SIERRA_PLL_CMNLC1		1
 
+#define SIERRA_SERDES_NO_SSC		0
+#define SIERRA_SERDES_EXTERNAL_SSC	1
+#define SIERRA_SERDES_INTERNAL_SSC	2
+
 #endif /* _DT_BINDINGS_CADENCE_SERDES_H */
-- 
2.26.1


WARNING: multiple messages have this Message-ID (diff)
From: Swapnil Jakhade <sjakhade@cadence.com>
To: <vkoul@kernel.org>, <kishon@ti.com>, <robh+dt@kernel.org>,
	<p.zabel@pengutronix.de>, <linux-phy@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>
Cc: <mparab@cadence.com>, <sjakhade@cadence.com>, <lokeshvutla@ti.com>
Subject: [PATCH 03/14] dt-bindings: phy: cadence-sierra: Add binding to specify SSC mode
Date: Fri, 3 Sep 2021 07:00:43 +0200	[thread overview]
Message-ID: <20210903050054.25627-4-sjakhade@cadence.com> (raw)
In-Reply-To: <20210903050054.25627-1-sjakhade@cadence.com>

Add binding to specify Spread Spectrum Clocking mode used.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
---
 .../devicetree/bindings/phy/phy-cadence-sierra.yaml      | 9 +++++++++
 include/dt-bindings/phy/phy-cadence.h                    | 4 ++++
 2 files changed, 13 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
index e71b32c9c0d1..a9e227d8b076 100644
--- a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
@@ -113,6 +113,15 @@ patternProperties:
         minimum: 1
         maximum: 16
 
+      cdns,ssc-mode:
+        description:
+          Specifies the Spread Spectrum Clocking mode used. It can be NO_SSC,
+          EXTERNAL_SSC or INTERNAL_SSC.
+          Refer include/dt-bindings/phy/phy-cadence.h for the constants to be used.
+        $ref: /schemas/types.yaml#/definitions/uint32
+        enum: [0, 1, 2]
+        default: 1
+
     required:
       - reg
       - resets
diff --git a/include/dt-bindings/phy/phy-cadence.h b/include/dt-bindings/phy/phy-cadence.h
index 4652bcb86265..0122c6067b17 100644
--- a/include/dt-bindings/phy/phy-cadence.h
+++ b/include/dt-bindings/phy/phy-cadence.h
@@ -17,4 +17,8 @@
 #define CDNS_SIERRA_PLL_CMNLC		0
 #define CDNS_SIERRA_PLL_CMNLC1		1
 
+#define SIERRA_SERDES_NO_SSC		0
+#define SIERRA_SERDES_EXTERNAL_SSC	1
+#define SIERRA_SERDES_INTERNAL_SSC	2
+
 #endif /* _DT_BINDINGS_CADENCE_SERDES_H */
-- 
2.26.1


-- 
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  parent reply	other threads:[~2021-09-03  5:02 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-03  5:00 [PATCH 00/14] PHY: Add support for multilink configurations in Cadence Sierra PHY driver Swapnil Jakhade
2021-09-03  5:00 ` Swapnil Jakhade
2021-09-03  5:00 ` [PATCH 01/14] phy: cadence: Sierra: Use of_device_get_match_data() to get driver data Swapnil Jakhade
2021-09-03  5:00   ` Swapnil Jakhade
2021-09-03  5:00 ` [PATCH 02/14] phy: cadence: Sierra: Prepare driver to add support for multilink configurations Swapnil Jakhade
2021-09-03  5:00   ` Swapnil Jakhade
2021-09-03  5:00 ` Swapnil Jakhade [this message]
2021-09-03  5:00   ` [PATCH 03/14] dt-bindings: phy: cadence-sierra: Add binding to specify SSC mode Swapnil Jakhade
2021-09-03 16:12   ` Rob Herring
2021-09-03 16:12     ` Rob Herring
2021-09-03  5:00 ` [PATCH 04/14] phy: cadence: Sierra: Add support to get SSC type from device tree Swapnil Jakhade
2021-09-03  5:00   ` Swapnil Jakhade
2021-09-03  5:00 ` [PATCH 05/14] phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra documentation Swapnil Jakhade
2021-09-03  5:00   ` Swapnil Jakhade
2021-09-03  5:00 ` [PATCH 06/14] phy: cadence: Sierra: Add PHY PCS common register configurations Swapnil Jakhade
2021-09-03  5:00   ` Swapnil Jakhade
2021-09-03  5:00 ` [PATCH 07/14] phy: cadence: Sierra: Check cmn_ready assertion during PHY power on Swapnil Jakhade
2021-09-03  5:00   ` Swapnil Jakhade
2021-09-03  5:00 ` [PATCH 08/14] phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operation Swapnil Jakhade
2021-09-03  5:00   ` Swapnil Jakhade
2021-09-03  5:00 ` [PATCH 09/14] phy: cadence: Sierra: Update single link PCIe register configuration Swapnil Jakhade
2021-09-03  5:00   ` Swapnil Jakhade
2021-09-03  5:00 ` [PATCH 10/14] phy: cadence: Sierra: Fix to get correct parent for mux clocks Swapnil Jakhade
2021-09-03  5:00   ` Swapnil Jakhade
2021-09-03  5:00 ` [PATCH 11/14] phy: cadence: Sierra: Add support for PHY multilink configurations Swapnil Jakhade
2021-09-03  5:00   ` Swapnil Jakhade
2021-09-03  5:00 ` [PATCH 12/14] phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration Swapnil Jakhade
2021-09-03  5:00   ` Swapnil Jakhade
2021-09-03  5:00 ` [PATCH 13/14] dt-bindings: phy: cadence-sierra: Add clock ID for derived reference clock Swapnil Jakhade
2021-09-03  5:00   ` Swapnil Jakhade
2021-09-03  5:00 ` [PATCH 14/14] phy: cadence: Sierra: Add support for derived reference clock output Swapnil Jakhade
2021-09-03  5:00   ` Swapnil Jakhade

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