* [PULL v2 00/36] (Mostly) x86 changes for 2021-09-06
@ 2021-09-06 15:26 Paolo Bonzini
2021-09-06 15:26 ` [PULL v2 01/36] target/i386: add missing bits to CR4_RESERVED_MASK Paolo Bonzini
2021-09-06 15:45 ` [PULL v2 00/36] (Mostly) x86 changes for 2021-09-06 Peter Maydell
0 siblings, 2 replies; 4+ messages in thread
From: Paolo Bonzini @ 2021-09-06 15:26 UTC (permalink / raw)
To: qemu-devel
The following changes since commit 935efca6c246c108253b0e4e51cc87648fc7ca10:
Merge remote-tracking branch 'remotes/thuth-gitlab/tags/pull-request-2021-09-06' into staging (2021-09-06 12:38:07 +0100)
are available in the Git repository at:
https://gitlab.com/bonzini/qemu.git tags/for-upstream
for you to fetch changes up to e423a6e6467abe2994e70670eb197069cc652782:
doc: Add the SGX doc (2021-09-06 17:24:38 +0200)
----------------------------------------------------------------
* SGX support (Sean, Yang)
* vGIF and vVMLOAD/VMSAVE support (Lara)
* Fix LA57 support in TCG (Daniel)
----------------------------------------------------------------
v1->v2: now entirely x86 - removed gbm patch and added the first one to fix TCG LA57
Daniel P. Berrangé (1):
target/i386: add missing bits to CR4_RESERVED_MASK
Lara Lazier (7):
target/i386: VMRUN and VMLOAD canonicalizations
target/i386: Added VGIF feature
target/i386: Moved int_ctl into CPUX86State structure
target/i386: Added VGIF V_IRQ masking capability
target/i386: Added ignore TPR check in ctl_has_irq
target/i386: Added changed priority check for VIRQ
target/i386: Added vVMLOAD and vVMSAVE feature
Sean Christopherson (21):
memory: Add RAM_PROTECTED flag to skip IOMMU mappings
hostmem: Add hostmem-epc as a backend for SGX EPC
i386: Add 'sgx-epc' device to expose EPC sections to guest
vl: Add sgx compound properties to expose SGX EPC sections to guest
i386: Add primary SGX CPUID and MSR defines
i386: Add SGX CPUID leaf FEAT_SGX_12_0_EAX
i386: Add SGX CPUID leaf FEAT_SGX_12_0_EBX
i386: Add SGX CPUID leaf FEAT_SGX_12_1_EAX
i386: Add get/set/migrate support for SGX_LEPUBKEYHASH MSRs
i386: Add feature control MSR dependency when SGX is enabled
i386: Update SGX CPUID info according to hardware/KVM/user input
i386: kvm: Add support for exposing PROVISIONKEY to guest
i386: Propagate SGX CPUID sub-leafs to KVM
Adjust min CPUID level to 0x12 when SGX is enabled
hw/i386/fw_cfg: Set SGX bits in feature control fw_cfg accordingly
hw/i386/pc: Account for SGX EPC sections when calculating device memory
i386/pc: Add e820 entry for SGX EPC section(s)
i386: acpi: Add SGX EPC entry to ACPI tables
q35: Add support for SGX EPC
i440fx: Add support for SGX EPC
doc: Add the SGX doc
Yang Zhong (7):
qom: Add memory-backend-epc ObjectOptions support
hostmem-epc: Add the reset interface for EPC backend reset
sgx-epc: Add the reset interface for sgx-epc virt device
sgx-epc: Avoid bios reset during sgx epc initialization
hostmem-epc: Make prealloc consistent with qemu cmdline during reset
Kconfig: Add CONFIG_SGX support
sgx-epc: Add the fill_device_info() callback support
backends/hostmem-epc.c | 118 ++++++++++++++
backends/meson.build | 1 +
configs/devices/i386-softmmu/default.mak | 1 +
docs/intel-sgx.txt | 167 +++++++++++++++++++
hw/i386/Kconfig | 5 +
hw/i386/acpi-build.c | 22 +++
hw/i386/fw_cfg.c | 10 +-
hw/i386/meson.build | 2 +
hw/i386/pc.c | 15 +-
hw/i386/pc_piix.c | 4 +
hw/i386/pc_q35.c | 3 +
hw/i386/sgx-epc.c | 265 +++++++++++++++++++++++++++++++
hw/i386/sgx-stub.c | 13 ++
hw/i386/sgx.c | 84 ++++++++++
hw/i386/x86.c | 29 ++++
hw/vfio/common.c | 1 +
include/exec/memory.h | 15 +-
include/hw/i386/pc.h | 8 +
include/hw/i386/sgx-epc.h | 67 ++++++++
include/hw/i386/x86.h | 1 +
monitor/hmp-cmds.c | 10 ++
qapi/machine.json | 52 +++++-
qapi/qom.json | 19 +++
qemu-options.hx | 10 +-
slirp | 2 +-
softmmu/memory.c | 5 +
softmmu/physmem.c | 3 +-
target/i386/cpu.c | 199 +++++++++++++++++++++--
target/i386/cpu.h | 39 +++++
target/i386/kvm/kvm.c | 75 +++++++++
target/i386/kvm/kvm_i386.h | 2 +
target/i386/machine.c | 42 ++++-
target/i386/svm.h | 8 +
target/i386/tcg/seg_helper.c | 2 +-
target/i386/tcg/sysemu/excp_helper.c | 2 +-
target/i386/tcg/sysemu/misc_helper.c | 11 +-
target/i386/tcg/sysemu/svm_helper.c | 121 +++++++++-----
37 files changed, 1368 insertions(+), 65 deletions(-)
create mode 100644 backends/hostmem-epc.c
create mode 100644 docs/intel-sgx.txt
create mode 100644 hw/i386/sgx-epc.c
create mode 100644 hw/i386/sgx-stub.c
create mode 100644 hw/i386/sgx.c
create mode 100644 include/hw/i386/sgx-epc.h
--
2.31.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PULL v2 01/36] target/i386: add missing bits to CR4_RESERVED_MASK
2021-09-06 15:26 [PULL v2 00/36] (Mostly) x86 changes for 2021-09-06 Paolo Bonzini
@ 2021-09-06 15:26 ` Paolo Bonzini
2021-09-06 15:55 ` Richard W.M. Jones
2021-09-06 15:45 ` [PULL v2 00/36] (Mostly) x86 changes for 2021-09-06 Peter Maydell
1 sibling, 1 reply; 4+ messages in thread
From: Paolo Bonzini @ 2021-09-06 15:26 UTC (permalink / raw)
To: qemu-devel; +Cc: Daniel P. Berrangé, Richard W . M . Jones
From: Daniel P. Berrangé <berrange@redhat.com>
Booting Fedora kernels with -cpu max hangs very early in boot. Disabling
the la57 CPUID bit fixes the problem. git bisect traced the regression to
commit 213ff024a2f92020290296cb9dc29c2af3d4a221 (HEAD, refs/bisect/bad)
Author: Lara Lazier <laramglazier@gmail.com>
Date: Wed Jul 21 17:26:50 2021 +0200
target/i386: Added consistency checks for CR4
All MBZ bits in CR4 must be zero. (APM2 15.5)
Added reserved bitmask and added checks in both
helper_vmrun and helper_write_crN.
Signed-off-by: Lara Lazier <laramglazier@gmail.com>
Message-Id: <20210721152651.14683-2-laramglazier@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
In this commit CR4_RESERVED_MASK is missing CR4_LA57_MASK and
two others. Adding this lets Fedora kernels boot once again.
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Tested-by: Richard W.M. Jones <rjones@redhat.com>
Message-Id: <20210831175033.175584-1-berrange@redhat.com>
[Removed VMXE/SMXE, matching the commit message. - Paolo]
Fixes: 213ff024a2 ("target/i386: Added consistency checks for CR4", 2021-07-22)
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/cpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 6c50d3ab4f..21b33fbe2e 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -257,6 +257,7 @@ typedef enum X86Seg {
| CR4_DE_MASK | CR4_PSE_MASK | CR4_PAE_MASK \
| CR4_MCE_MASK | CR4_PGE_MASK | CR4_PCE_MASK \
| CR4_OSFXSR_MASK | CR4_OSXMMEXCPT_MASK |CR4_UMIP_MASK \
+ | CR4_LA57_MASK \
| CR4_FSGSBASE_MASK | CR4_PCIDE_MASK | CR4_OSXSAVE_MASK \
| CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_PKE_MASK | CR4_PKS_MASK))
--
2.31.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PULL v2 00/36] (Mostly) x86 changes for 2021-09-06
2021-09-06 15:26 [PULL v2 00/36] (Mostly) x86 changes for 2021-09-06 Paolo Bonzini
2021-09-06 15:26 ` [PULL v2 01/36] target/i386: add missing bits to CR4_RESERVED_MASK Paolo Bonzini
@ 2021-09-06 15:45 ` Peter Maydell
1 sibling, 0 replies; 4+ messages in thread
From: Peter Maydell @ 2021-09-06 15:45 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: QEMU Developers
On Mon, 6 Sept 2021 at 16:28, Paolo Bonzini <pbonzini@redhat.com> wrote:
>
> The following changes since commit 935efca6c246c108253b0e4e51cc87648fc7ca10:
>
> Merge remote-tracking branch 'remotes/thuth-gitlab/tags/pull-request-2021-09-06' into staging (2021-09-06 12:38:07 +0100)
>
> are available in the Git repository at:
>
> https://gitlab.com/bonzini/qemu.git tags/for-upstream
>
> for you to fetch changes up to e423a6e6467abe2994e70670eb197069cc652782:
>
> doc: Add the SGX doc (2021-09-06 17:24:38 +0200)
>
> ----------------------------------------------------------------
> * SGX support (Sean, Yang)
> * vGIF and vVMLOAD/VMSAVE support (Lara)
> * Fix LA57 support in TCG (Daniel)
> ----------------------------------------------------------------
>
> v1->v2: now entirely x86 - removed gbm patch and added the first one to fix TCG LA57
> slirp | 2 +-
Nothing slirp-related in the changelog, but the module has
been changed by commit f99ca7795fa6d17
("target/i386: Moved int_ctl into CPUX86State structure")
in your branch. Looks like an accident, could you clean it up,
and resubmit, please ?
thanks
-- PMM
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PULL v2 01/36] target/i386: add missing bits to CR4_RESERVED_MASK
2021-09-06 15:26 ` [PULL v2 01/36] target/i386: add missing bits to CR4_RESERVED_MASK Paolo Bonzini
@ 2021-09-06 15:55 ` Richard W.M. Jones
0 siblings, 0 replies; 4+ messages in thread
From: Richard W.M. Jones @ 2021-09-06 15:55 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: Daniel P. Berrangé, qemu-devel
On Mon, Sep 06, 2021 at 05:26:57PM +0200, Paolo Bonzini wrote:
> From: Daniel P. Berrangé <berrange@redhat.com>
>
> Booting Fedora kernels with -cpu max hangs very early in boot. Disabling
> the la57 CPUID bit fixes the problem. git bisect traced the regression to
>
> commit 213ff024a2f92020290296cb9dc29c2af3d4a221 (HEAD, refs/bisect/bad)
> Author: Lara Lazier <laramglazier@gmail.com>
> Date: Wed Jul 21 17:26:50 2021 +0200
>
> target/i386: Added consistency checks for CR4
>
> All MBZ bits in CR4 must be zero. (APM2 15.5)
> Added reserved bitmask and added checks in both
> helper_vmrun and helper_write_crN.
>
> Signed-off-by: Lara Lazier <laramglazier@gmail.com>
> Message-Id: <20210721152651.14683-2-laramglazier@gmail.com>
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
>
> In this commit CR4_RESERVED_MASK is missing CR4_LA57_MASK and
> two others. Adding this lets Fedora kernels boot once again.
>
> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
> Tested-by: Richard W.M. Jones <rjones@redhat.com>
I tested it again and it still works:
$ LIBGUESTFS_BACKEND_SETTINGS=force_tcg LIBGUESTFS_HV=$PWD/qemu-system-x86_64 libguestfs-test-tool
...
===== TEST FINISHED OK =====
(versus without the patch where it appears to hang in very early kernel)
Rich.
> Message-Id: <20210831175033.175584-1-berrange@redhat.com>
> [Removed VMXE/SMXE, matching the commit message. - Paolo]
> Fixes: 213ff024a2 ("target/i386: Added consistency checks for CR4", 2021-07-22)
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
> target/i386/cpu.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index 6c50d3ab4f..21b33fbe2e 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -257,6 +257,7 @@ typedef enum X86Seg {
> | CR4_DE_MASK | CR4_PSE_MASK | CR4_PAE_MASK \
> | CR4_MCE_MASK | CR4_PGE_MASK | CR4_PCE_MASK \
> | CR4_OSFXSR_MASK | CR4_OSXMMEXCPT_MASK |CR4_UMIP_MASK \
> + | CR4_LA57_MASK \
> | CR4_FSGSBASE_MASK | CR4_PCIDE_MASK | CR4_OSXSAVE_MASK \
> | CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_PKE_MASK | CR4_PKS_MASK))
>
> --
> 2.31.1
--
Richard Jones, Virtualization Group, Red Hat http://people.redhat.com/~rjones
Read my programming and virtualization blog: http://rwmj.wordpress.com
virt-df lists disk usage of guests without needing to install any
software inside the virtual machine. Supports Linux and Windows.
http://people.redhat.com/~rjones/virt-df/
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2021-09-06 15:59 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-09-06 15:26 [PULL v2 00/36] (Mostly) x86 changes for 2021-09-06 Paolo Bonzini
2021-09-06 15:26 ` [PULL v2 01/36] target/i386: add missing bits to CR4_RESERVED_MASK Paolo Bonzini
2021-09-06 15:55 ` Richard W.M. Jones
2021-09-06 15:45 ` [PULL v2 00/36] (Mostly) x86 changes for 2021-09-06 Peter Maydell
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.