* [PULL v3 00/36] (Mostly) x86 changes for 2021-09-06 @ 2021-09-07 7:13 Paolo Bonzini 2021-09-07 7:13 ` [PULL v3 04/36] target/i386: Moved int_ctl into CPUX86State structure Paolo Bonzini ` (2 more replies) 0 siblings, 3 replies; 6+ messages in thread From: Paolo Bonzini @ 2021-09-07 7:13 UTC (permalink / raw) To: qemu-devel The following changes since commit 935efca6c246c108253b0e4e51cc87648fc7ca10: Merge remote-tracking branch 'remotes/thuth-gitlab/tags/pull-request-2021-09-06' into staging (2021-09-06 12:38:07 +0100) are available in the Git repository at: https://gitlab.com/bonzini/qemu.git tags/for-upstream for you to fetch changes up to 127c76bd1aa893122a22677b991c0f31ebef7f09: doc: Add the SGX doc (2021-09-07 08:54:57 +0200) ---------------------------------------------------------------- * SGX support (Sean, Yang) * vGIF and vVMLOAD/VMSAVE support (Lara) * Fix LA57 support in TCG (Daniel) ---------------------------------------------------------------- v1->v2: now entirely x86 - removed gbm patch and added the first one to fix TCG LA57 v2->v3: fix "target/i386: Moved int_ctl into CPUX86State structure" commit Daniel P. Berrangé (1): target/i386: add missing bits to CR4_RESERVED_MASK Lara Lazier (7): target/i386: VMRUN and VMLOAD canonicalizations target/i386: Added VGIF feature target/i386: Moved int_ctl into CPUX86State structure target/i386: Added VGIF V_IRQ masking capability target/i386: Added ignore TPR check in ctl_has_irq target/i386: Added changed priority check for VIRQ target/i386: Added vVMLOAD and vVMSAVE feature Sean Christopherson (21): memory: Add RAM_PROTECTED flag to skip IOMMU mappings hostmem: Add hostmem-epc as a backend for SGX EPC i386: Add 'sgx-epc' device to expose EPC sections to guest vl: Add sgx compound properties to expose SGX EPC sections to guest i386: Add primary SGX CPUID and MSR defines i386: Add SGX CPUID leaf FEAT_SGX_12_0_EAX i386: Add SGX CPUID leaf FEAT_SGX_12_0_EBX i386: Add SGX CPUID leaf FEAT_SGX_12_1_EAX i386: Add get/set/migrate support for SGX_LEPUBKEYHASH MSRs i386: Add feature control MSR dependency when SGX is enabled i386: Update SGX CPUID info according to hardware/KVM/user input i386: kvm: Add support for exposing PROVISIONKEY to guest i386: Propagate SGX CPUID sub-leafs to KVM Adjust min CPUID level to 0x12 when SGX is enabled hw/i386/fw_cfg: Set SGX bits in feature control fw_cfg accordingly hw/i386/pc: Account for SGX EPC sections when calculating device memory i386/pc: Add e820 entry for SGX EPC section(s) i386: acpi: Add SGX EPC entry to ACPI tables q35: Add support for SGX EPC i440fx: Add support for SGX EPC doc: Add the SGX doc Yang Zhong (7): qom: Add memory-backend-epc ObjectOptions support hostmem-epc: Add the reset interface for EPC backend reset sgx-epc: Add the reset interface for sgx-epc virt device sgx-epc: Avoid bios reset during sgx epc initialization hostmem-epc: Make prealloc consistent with qemu cmdline during reset Kconfig: Add CONFIG_SGX support sgx-epc: Add the fill_device_info() callback support backends/hostmem-epc.c | 118 ++++++++++++++ backends/meson.build | 1 + configs/devices/i386-softmmu/default.mak | 1 + docs/intel-sgx.txt | 167 +++++++++++++++++++ hw/i386/Kconfig | 5 + hw/i386/acpi-build.c | 22 +++ hw/i386/fw_cfg.c | 10 +- hw/i386/meson.build | 2 + hw/i386/pc.c | 15 +- hw/i386/pc_piix.c | 4 + hw/i386/pc_q35.c | 3 + hw/i386/sgx-epc.c | 265 +++++++++++++++++++++++++++++++ hw/i386/sgx-stub.c | 13 ++ hw/i386/sgx.c | 84 ++++++++++ hw/i386/x86.c | 29 ++++ hw/vfio/common.c | 1 + include/exec/memory.h | 15 +- include/hw/i386/pc.h | 8 + include/hw/i386/sgx-epc.h | 67 ++++++++ include/hw/i386/x86.h | 1 + monitor/hmp-cmds.c | 10 ++ qapi/machine.json | 52 +++++- qapi/qom.json | 19 +++ qemu-options.hx | 10 +- softmmu/memory.c | 5 + softmmu/physmem.c | 3 +- target/i386/cpu.c | 199 +++++++++++++++++++++-- target/i386/cpu.h | 39 +++++ target/i386/kvm/kvm.c | 75 +++++++++ target/i386/kvm/kvm_i386.h | 2 + target/i386/machine.c | 42 ++++- target/i386/svm.h | 8 + target/i386/tcg/seg_helper.c | 2 +- target/i386/tcg/sysemu/excp_helper.c | 2 +- target/i386/tcg/sysemu/misc_helper.c | 11 +- target/i386/tcg/sysemu/svm_helper.c | 121 +++++++++----- 36 files changed, 1367 insertions(+), 64 deletions(-) create mode 100644 backends/hostmem-epc.c create mode 100644 docs/intel-sgx.txt create mode 100644 hw/i386/sgx-epc.c create mode 100644 hw/i386/sgx-stub.c create mode 100644 hw/i386/sgx.c create mode 100644 include/hw/i386/sgx-epc.h -- 2.31.1 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PULL v3 04/36] target/i386: Moved int_ctl into CPUX86State structure 2021-09-07 7:13 [PULL v3 00/36] (Mostly) x86 changes for 2021-09-06 Paolo Bonzini @ 2021-09-07 7:13 ` Paolo Bonzini 2021-09-07 12:23 ` [PULL v3 00/36] (Mostly) x86 changes for 2021-09-06 Peter Maydell 2021-09-07 16:00 ` Peter Maydell 2 siblings, 0 replies; 6+ messages in thread From: Paolo Bonzini @ 2021-09-07 7:13 UTC (permalink / raw) To: qemu-devel; +Cc: Lara Lazier From: Lara Lazier <laramglazier@gmail.com> Moved int_ctl into the CPUX86State structure. It removes some unnecessary stores and loads, and prepares for tracking the vIRQ state even when it is masked due to vGIF. Signed-off-by: Lara Lazier <laramglazier@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 1 + target/i386/machine.c | 22 ++++++++++++- target/i386/tcg/seg_helper.c | 2 +- target/i386/tcg/sysemu/misc_helper.c | 4 +-- target/i386/tcg/sysemu/svm_helper.c | 48 +++++++++------------------- 6 files changed, 41 insertions(+), 38 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 86064ea1f9..ddc3b63cb8 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5655,7 +5655,7 @@ static void x86_cpu_reset(DeviceState *dev) env->old_exception = -1; /* init to reset state */ - + env->int_ctl = 0; env->hflags2 |= HF2_GIF_MASK; env->hflags &= ~HF_GUEST_MASK; diff --git a/target/i386/cpu.h b/target/i386/cpu.h index aafc2eb696..3dfe630d7e 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1578,6 +1578,7 @@ typedef struct CPUX86State { uint64_t nested_cr3; uint32_t nested_pg_mode; uint8_t v_tpr; + uint32_t int_ctl; /* KVM states, automatically cleared on reset */ uint8_t nmi_injected; diff --git a/target/i386/machine.c b/target/i386/machine.c index f6f094f1c9..b0943118d1 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -203,7 +203,7 @@ static int cpu_pre_save(void *opaque) X86CPU *cpu = opaque; CPUX86State *env = &cpu->env; int i; - + env->v_tpr = env->int_ctl & V_TPR_MASK; /* FPU */ env->fpus_vmstate = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11; env->fptag_vmstate = 0; @@ -1356,6 +1356,25 @@ static const VMStateDescription vmstate_svm_npt = { } }; +static bool svm_guest_needed(void *opaque) +{ + X86CPU *cpu = opaque; + CPUX86State *env = &cpu->env; + + return tcg_enabled() && env->int_ctl; +} + +static const VMStateDescription vmstate_svm_guest = { + .name = "cpu/svm_guest", + .version_id = 1, + .minimum_version_id = 1, + .needed = svm_guest_needed, + .fields = (VMStateField[]){ + VMSTATE_UINT32(env.int_ctl, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + #ifndef TARGET_X86_64 static bool intel_efer32_needed(void *opaque) { @@ -1524,6 +1543,7 @@ const VMStateDescription vmstate_x86_cpu = { &vmstate_msr_intel_pt, &vmstate_msr_virt_ssbd, &vmstate_svm_npt, + &vmstate_svm_guest, #ifndef TARGET_X86_64 &vmstate_efer32, #endif diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c index 3ed20ca31d..cef68b610a 100644 --- a/target/i386/tcg/seg_helper.c +++ b/target/i386/tcg/seg_helper.c @@ -1166,7 +1166,6 @@ bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request) break; #if !defined(CONFIG_USER_ONLY) case CPU_INTERRUPT_VIRQ: - /* FIXME: this should respect TPR */ cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR, 0, 0); intno = x86_ldl_phys(cs, env->vm_vmcb + offsetof(struct vmcb, control.int_vector)); @@ -1174,6 +1173,7 @@ bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request) "Servicing virtual hardware INT=0x%02x\n", intno); do_interrupt_x86_hardirq(env, intno, 1); cs->interrupt_request &= ~CPU_INTERRUPT_VIRQ; + env->int_ctl &= ~V_IRQ_MASK; break; #endif } diff --git a/target/i386/tcg/sysemu/misc_helper.c b/target/i386/tcg/sysemu/misc_helper.c index e7a2ebde81..91b0fc916b 100644 --- a/target/i386/tcg/sysemu/misc_helper.c +++ b/target/i386/tcg/sysemu/misc_helper.c @@ -73,7 +73,7 @@ target_ulong helper_read_crN(CPUX86State *env, int reg) if (!(env->hflags2 & HF2_VINTR_MASK)) { val = cpu_get_apic_tpr(env_archcpu(env)->apic_state); } else { - val = env->v_tpr; + val = env->int_ctl & V_TPR_MASK; } break; } @@ -121,7 +121,7 @@ void helper_write_crN(CPUX86State *env, int reg, target_ulong t0) cpu_set_apic_tpr(env_archcpu(env)->apic_state, t0); qemu_mutex_unlock_iothread(); } - env->v_tpr = t0 & 0x0f; + env->int_ctl = (env->int_ctl & ~V_TPR_MASK) | (t0 & V_TPR_MASK); break; default: env->cr[reg] = t0; diff --git a/target/i386/tcg/sysemu/svm_helper.c b/target/i386/tcg/sysemu/svm_helper.c index 66c2c1e61f..24c58b6a38 100644 --- a/target/i386/tcg/sysemu/svm_helper.c +++ b/target/i386/tcg/sysemu/svm_helper.c @@ -76,14 +76,14 @@ static inline void svm_load_seg_cache(CPUX86State *env, hwaddr addr, sc->base, sc->limit, sc->flags); } -static inline bool ctl_has_irq(uint32_t int_ctl) +static inline bool ctl_has_irq(CPUX86State *env) { uint32_t int_prio; uint32_t tpr; - int_prio = (int_ctl & V_INTR_PRIO_MASK) >> V_INTR_PRIO_SHIFT; - tpr = int_ctl & V_TPR_MASK; - return (int_ctl & V_IRQ_MASK) && (int_prio >= tpr); + int_prio = (env->int_ctl & V_INTR_PRIO_MASK) >> V_INTR_PRIO_SHIFT; + tpr = env->int_ctl & V_TPR_MASK; + return (env->int_ctl & V_IRQ_MASK) && (int_prio >= tpr); } static inline bool is_efer_invalid_state (CPUX86State *env) @@ -121,13 +121,11 @@ static inline bool is_efer_invalid_state (CPUX86State *env) return false; } -static inline bool virtual_gif_enabled(CPUX86State *env, uint32_t *int_ctl) +static inline bool virtual_gif_enabled(CPUX86State *env) { if (likely(env->hflags & HF_GUEST_MASK)) { - *int_ctl = x86_ldl_phys(env_cpu(env), - env->vm_vmcb + offsetof(struct vmcb, control.int_ctl)); return (env->features[FEAT_SVM] & CPUID_SVM_VGIF) - && (*int_ctl & V_GIF_ENABLED_MASK); + && (env->int_ctl & V_GIF_ENABLED_MASK); } return false; } @@ -139,7 +137,6 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) target_ulong addr; uint64_t nested_ctl; uint32_t event_inj; - uint32_t int_ctl; uint32_t asid; uint64_t new_cr0; uint64_t new_cr3; @@ -292,11 +289,10 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) cpu_x86_update_cr3(env, new_cr3); env->cr[2] = x86_ldq_phys(cs, env->vm_vmcb + offsetof(struct vmcb, save.cr2)); - int_ctl = x86_ldl_phys(cs, + env->int_ctl = x86_ldl_phys(cs, env->vm_vmcb + offsetof(struct vmcb, control.int_ctl)); env->hflags2 &= ~(HF2_HIF_MASK | HF2_VINTR_MASK); - if (int_ctl & V_INTR_MASKING_MASK) { - env->v_tpr = int_ctl & V_TPR_MASK; + if (env->int_ctl & V_INTR_MASKING_MASK) { env->hflags2 |= HF2_VINTR_MASK; if (env->eflags & IF_MASK) { env->hflags2 |= HF2_HIF_MASK; @@ -362,7 +358,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend) env->hflags2 |= HF2_GIF_MASK; - if (ctl_has_irq(int_ctl)) { + if (ctl_has_irq(env)) { CPUState *cs = env_cpu(env); cs->interrupt_request |= CPU_INTERRUPT_VIRQ; @@ -522,11 +518,8 @@ void helper_stgi(CPUX86State *env) { cpu_svm_check_intercept_param(env, SVM_EXIT_STGI, 0, GETPC()); - CPUState *cs = env_cpu(env); - uint32_t int_ctl; - if (virtual_gif_enabled(env, &int_ctl)) { - x86_stl_phys(cs, env->vm_vmcb + offsetof(struct vmcb, control.int_ctl), - int_ctl | V_GIF_MASK); + if (virtual_gif_enabled(env)) { + env->int_ctl |= V_GIF_MASK; } else { env->hflags2 |= HF2_GIF_MASK; } @@ -536,11 +529,8 @@ void helper_clgi(CPUX86State *env) { cpu_svm_check_intercept_param(env, SVM_EXIT_CLGI, 0, GETPC()); - CPUState *cs = env_cpu(env); - uint32_t int_ctl; - if (virtual_gif_enabled(env, &int_ctl)) { - x86_stl_phys(cs, env->vm_vmcb + offsetof(struct vmcb, control.int_ctl), - int_ctl & ~V_GIF_MASK); + if (virtual_gif_enabled(env)) { + env->int_ctl &= ~V_GIF_MASK; } else { env->hflags2 &= ~HF2_GIF_MASK; } @@ -688,7 +678,6 @@ void cpu_vmexit(CPUX86State *env, uint32_t exit_code, uint64_t exit_info_1, void do_vmexit(CPUX86State *env) { CPUState *cs = env_cpu(env); - uint32_t int_ctl; if (env->hflags & HF_INHIBIT_IRQ_MASK) { x86_stl_phys(cs, @@ -731,16 +720,8 @@ void do_vmexit(CPUX86State *env) env->vm_vmcb + offsetof(struct vmcb, save.cr3), env->cr[3]); x86_stq_phys(cs, env->vm_vmcb + offsetof(struct vmcb, save.cr4), env->cr[4]); - - int_ctl = x86_ldl_phys(cs, - env->vm_vmcb + offsetof(struct vmcb, control.int_ctl)); - int_ctl &= ~(V_TPR_MASK | V_IRQ_MASK); - int_ctl |= env->v_tpr & V_TPR_MASK; - if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { - int_ctl |= V_IRQ_MASK; - } x86_stl_phys(cs, - env->vm_vmcb + offsetof(struct vmcb, control.int_ctl), int_ctl); + env->vm_vmcb + offsetof(struct vmcb, control.int_ctl), env->int_ctl); x86_stq_phys(cs, env->vm_vmcb + offsetof(struct vmcb, save.rflags), cpu_compute_eflags(env)); @@ -763,6 +744,7 @@ void do_vmexit(CPUX86State *env) env->intercept = 0; env->intercept_exceptions = 0; cs->interrupt_request &= ~CPU_INTERRUPT_VIRQ; + env->int_ctl = 0; env->tsc_offset = 0; env->gdt.base = x86_ldq_phys(cs, env->vm_hsave + offsetof(struct vmcb, -- 2.31.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PULL v3 00/36] (Mostly) x86 changes for 2021-09-06 2021-09-07 7:13 [PULL v3 00/36] (Mostly) x86 changes for 2021-09-06 Paolo Bonzini 2021-09-07 7:13 ` [PULL v3 04/36] target/i386: Moved int_ctl into CPUX86State structure Paolo Bonzini @ 2021-09-07 12:23 ` Peter Maydell 2021-09-07 16:04 ` Paolo Bonzini 2021-09-07 16:00 ` Peter Maydell 2 siblings, 1 reply; 6+ messages in thread From: Peter Maydell @ 2021-09-07 12:23 UTC (permalink / raw) To: Paolo Bonzini; +Cc: QEMU Developers On Tue, 7 Sept 2021 at 08:16, Paolo Bonzini <pbonzini@redhat.com> wrote: > > The following changes since commit 935efca6c246c108253b0e4e51cc87648fc7ca10: > > Merge remote-tracking branch 'remotes/thuth-gitlab/tags/pull-request-2021-09-06' into staging (2021-09-06 12:38:07 +0100) > > are available in the Git repository at: > > https://gitlab.com/bonzini/qemu.git tags/for-upstream > > for you to fetch changes up to 127c76bd1aa893122a22677b991c0f31ebef7f09: > > doc: Add the SGX doc (2021-09-07 08:54:57 +0200) > > ---------------------------------------------------------------- Sorry to bounce this for a third time, but I only just noticed this in the diffstat: > docs/intel-sgx.txt | 167 +++++++++++++++++++ No new .txt files in docs, please. All documentation from now on needs to be in rst format and correctly integrated into the right place in the manual structure. thanks -- PMM ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PULL v3 00/36] (Mostly) x86 changes for 2021-09-06 2021-09-07 12:23 ` [PULL v3 00/36] (Mostly) x86 changes for 2021-09-06 Peter Maydell @ 2021-09-07 16:04 ` Paolo Bonzini 0 siblings, 0 replies; 6+ messages in thread From: Paolo Bonzini @ 2021-09-07 16:04 UTC (permalink / raw) To: Peter Maydell; +Cc: QEMU Developers On 07/09/21 14:23, Peter Maydell wrote: > On Tue, 7 Sept 2021 at 08:16, Paolo Bonzini <pbonzini@redhat.com> wrote: >> >> The following changes since commit 935efca6c246c108253b0e4e51cc87648fc7ca10: >> >> Merge remote-tracking branch 'remotes/thuth-gitlab/tags/pull-request-2021-09-06' into staging (2021-09-06 12:38:07 +0100) >> >> are available in the Git repository at: >> >> https://gitlab.com/bonzini/qemu.git tags/for-upstream >> >> for you to fetch changes up to 127c76bd1aa893122a22677b991c0f31ebef7f09: >> >> doc: Add the SGX doc (2021-09-07 08:54:57 +0200) >> >> ---------------------------------------------------------------- > > Sorry to bounce this for a third time, but I only just noticed > this in the diffstat: > >> docs/intel-sgx.txt | 167 +++++++++++++++++++ > > No new .txt files in docs, please. All documentation from now > on needs to be in rst format and correctly integrated into > the right place in the manual structure. As discussed on IRC, I didn't want this series to be held by discussion on how to improve target-i386.rst and make room for more files, but I have now finished and posted a proposal for that. Since I see that this pull request is already in the staging branch, I assume that I'll include the SGX conversion to reStructuredText as soon as that proposal is reviewed. Paolo ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PULL v3 00/36] (Mostly) x86 changes for 2021-09-06 2021-09-07 7:13 [PULL v3 00/36] (Mostly) x86 changes for 2021-09-06 Paolo Bonzini 2021-09-07 7:13 ` [PULL v3 04/36] target/i386: Moved int_ctl into CPUX86State structure Paolo Bonzini 2021-09-07 12:23 ` [PULL v3 00/36] (Mostly) x86 changes for 2021-09-06 Peter Maydell @ 2021-09-07 16:00 ` Peter Maydell 2021-09-07 17:07 ` Paolo Bonzini 2 siblings, 1 reply; 6+ messages in thread From: Peter Maydell @ 2021-09-07 16:00 UTC (permalink / raw) To: Paolo Bonzini; +Cc: QEMU Developers On Tue, 7 Sept 2021 at 08:16, Paolo Bonzini <pbonzini@redhat.com> wrote: > > The following changes since commit 935efca6c246c108253b0e4e51cc87648fc7ca10: > > Merge remote-tracking branch 'remotes/thuth-gitlab/tags/pull-request-2021-09-06' into staging (2021-09-06 12:38:07 +0100) > > are available in the Git repository at: > > https://gitlab.com/bonzini/qemu.git tags/for-upstream > > for you to fetch changes up to 127c76bd1aa893122a22677b991c0f31ebef7f09: > > doc: Add the SGX doc (2021-09-07 08:54:57 +0200) > > ---------------------------------------------------------------- > * SGX support (Sean, Yang) > * vGIF and vVMLOAD/VMSAVE support (Lara) > * Fix LA57 support in TCG (Daniel) > > ---------------------------------------------------------------- New warnings during 'make check': qemu-system-i386: warning: Unknown firmware file in legacy mode: etc/msr_feature_control qemu-system-x86_64: warning: Unknown firmware file in legacy mode: etc/msr_feature_control (not sure which qtest produced these). ppc produced a new meson warning: Program cp found: YES (/bin/cp) Program cp found: YES (/bin/cp) Program cp found: YES (/bin/cp) Program cp found: YES (/bin/cp) Program sphinx-build-3 sphinx-build skipped: feature docs disabled Program python3 found: YES (/usr/bin/python3) WARNING: Project targeting '>=0.55.0' but tried to use feature introduced in '0.57.0': test() timeout <= 0. Program diff found: YES (/usr/bin/diff) Program dbus-daemon found: YES (/usr/bin/dbus-daemon) Program /usr/bin/gdbus-codegen found: YES (/usr/bin/gdbus-codegen) Program initrd-stress.sh found: YES (/home/pm215/qemu/tests/migration/initrd-stress.sh) Program xgettext found: YES (/usr/bin/xgettext) Build targets in project: 650 WARNING: Project specifies a minimum meson_version '>=0.55.0' but uses features which were added in newer versions: * 0.57.0: {'test() timeout <= 0'} (PS: why does meson report "Program /usr/bin/python3 found: YES (/usr/bin/python3)" and "Program cp found: YES (/bin/cp)" so many times ??) -- PMM ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PULL v3 00/36] (Mostly) x86 changes for 2021-09-06 2021-09-07 16:00 ` Peter Maydell @ 2021-09-07 17:07 ` Paolo Bonzini 0 siblings, 0 replies; 6+ messages in thread From: Paolo Bonzini @ 2021-09-07 17:07 UTC (permalink / raw) To: Peter Maydell; +Cc: QEMU Developers On 07/09/21 18:00, Peter Maydell wrote: > New warnings during 'make check': > > qemu-system-i386: warning: Unknown firmware file in legacy mode: > etc/msr_feature_control > qemu-system-x86_64: warning: Unknown firmware file in legacy mode: > etc/msr_feature_control > > (not sure which qtest produced these). Hmm, the bug is preexisting but now it's exposed on machines that have SGX. > ppc produced a new meson warning: This isn't me, but rather the same system update that caused that .so issue. I was planning to update QEMU to a newer version of meson, so that will go away soon. > (PS: why does meson report "Program /usr/bin/python3 found: YES > (/usr/bin/python3)" and > "Program cp found: YES (/bin/cp)" so many times ??) It seems to report it once per custom_target. I'll take a look tomorrow. Paolo ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-09-07 17:08 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-09-07 7:13 [PULL v3 00/36] (Mostly) x86 changes for 2021-09-06 Paolo Bonzini 2021-09-07 7:13 ` [PULL v3 04/36] target/i386: Moved int_ctl into CPUX86State structure Paolo Bonzini 2021-09-07 12:23 ` [PULL v3 00/36] (Mostly) x86 changes for 2021-09-06 Peter Maydell 2021-09-07 16:04 ` Paolo Bonzini 2021-09-07 16:00 ` Peter Maydell 2021-09-07 17:07 ` Paolo Bonzini
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.