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From: Chester Lin <clin@suse.com>
To: "Rob Herring" <robh+dt@kernel.org>,
	"Larisa Grigore" <larisa.grigore@nxp.com>,
	"Radu Nicolae Pirea" <radu-nicolae.pirea@oss.nxp.com>,
	"Andreas Färber" <afaerber@suse.de>,
	"Matthias Brugger" <mbrugger@suse.com>
Cc: s32@nxp.com, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-serial@vger.kernel.org,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Shawn Guo <shawnguo@kernel.org>, Li Yang <leoyang.li@nxp.com>,
	Krzysztof Kozlowski <krzk@kernel.org>,
	catalin-dan.udma@nxp.com, bogdan.hamciuc@nxp.com,
	bogdan.folea@nxp.com, ciprianmarian.costea@nxp.com,
	ghennadi.procopciuc@nxp.com, "Ivan T . Ivanov" <iivanov@suse.de>,
	"Lee, Chun-Yi" <jlee@suse.com>, Chester Lin <clin@suse.com>
Subject: [PATCH v2 5/8] arm64: dts: s32g2: add serial/uart support
Date: Wed,  8 Sep 2021 14:45:25 +0800	[thread overview]
Message-ID: <20210908064528.922-6-clin@suse.com> (raw)
In-Reply-To: <20210908064528.922-1-clin@suse.com>

Add serial/uart support for NXP S32G2 based on the information provided by
NXP's CodeAurora BSP.

Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
Signed-off-by: Chester Lin <clin@suse.com>
---
Changes in v2:
- Add new Signed-off-by.
- Fix the copyright string.
- Remove aliases.
- Revise reg properties based on new cell size.

 arch/arm64/boot/dts/freescale/s32g2.dtsi | 25 ++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index 53b18671deec..59ea8a25aa4c 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -3,6 +3,7 @@
  * NXP S32G2 SoC family
  *
  * Copyright (c) 2021 SUSE LLC
+ * Copyright (c) 2017-2021 NXP
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -84,6 +85,30 @@ soc {
 		#size-cells = <1>;
 		ranges = <0 0 0 0x80000000>;
 
+		uart0: serial@401c8000 {
+			compatible = "nxp,s32g2-linflexuart",
+				     "fsl,s32v234-linflexuart";
+			reg = <0x401c8000 0x3000>;
+			interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
+			status = "disabled";
+		};
+
+		uart1: serial@401cc000 {
+			compatible = "nxp,s32g2-linflexuart",
+				     "fsl,s32v234-linflexuart";
+			reg = <0x401cc000 0x3000>;
+			interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>;
+			status = "disabled";
+		};
+
+		uart2: serial@402bc000 {
+			compatible = "nxp,s32g2-linflexuart",
+				     "fsl,s32v234-linflexuart";
+			reg = <0x402bc000 0x3000>;
+			interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
+			status = "disabled";
+		};
+
 		gic: interrupt-controller@50800000 {
 			compatible = "arm,gic-v3";
 			reg = <0x50800000 0x10000>,
-- 
2.30.0


WARNING: multiple messages have this Message-ID (diff)
From: Chester Lin <clin@suse.com>
To: "Rob Herring" <robh+dt@kernel.org>,
	"Larisa Grigore" <larisa.grigore@nxp.com>,
	"Radu Nicolae Pirea" <radu-nicolae.pirea@oss.nxp.com>,
	"Andreas Färber" <afaerber@suse.de>,
	"Matthias Brugger" <mbrugger@suse.com>
Cc: s32@nxp.com, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-serial@vger.kernel.org,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Shawn Guo <shawnguo@kernel.org>, Li Yang <leoyang.li@nxp.com>,
	Krzysztof Kozlowski <krzk@kernel.org>,
	catalin-dan.udma@nxp.com, bogdan.hamciuc@nxp.com,
	bogdan.folea@nxp.com, ciprianmarian.costea@nxp.com,
	ghennadi.procopciuc@nxp.com, "Ivan T . Ivanov" <iivanov@suse.de>,
	"Lee, Chun-Yi" <jlee@suse.com>, Chester Lin <clin@suse.com>
Subject: [PATCH v2 5/8] arm64: dts: s32g2: add serial/uart support
Date: Wed,  8 Sep 2021 14:45:25 +0800	[thread overview]
Message-ID: <20210908064528.922-6-clin@suse.com> (raw)
In-Reply-To: <20210908064528.922-1-clin@suse.com>

Add serial/uart support for NXP S32G2 based on the information provided by
NXP's CodeAurora BSP.

Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
Signed-off-by: Chester Lin <clin@suse.com>
---
Changes in v2:
- Add new Signed-off-by.
- Fix the copyright string.
- Remove aliases.
- Revise reg properties based on new cell size.

 arch/arm64/boot/dts/freescale/s32g2.dtsi | 25 ++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index 53b18671deec..59ea8a25aa4c 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -3,6 +3,7 @@
  * NXP S32G2 SoC family
  *
  * Copyright (c) 2021 SUSE LLC
+ * Copyright (c) 2017-2021 NXP
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -84,6 +85,30 @@ soc {
 		#size-cells = <1>;
 		ranges = <0 0 0 0x80000000>;
 
+		uart0: serial@401c8000 {
+			compatible = "nxp,s32g2-linflexuart",
+				     "fsl,s32v234-linflexuart";
+			reg = <0x401c8000 0x3000>;
+			interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
+			status = "disabled";
+		};
+
+		uart1: serial@401cc000 {
+			compatible = "nxp,s32g2-linflexuart",
+				     "fsl,s32v234-linflexuart";
+			reg = <0x401cc000 0x3000>;
+			interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>;
+			status = "disabled";
+		};
+
+		uart2: serial@402bc000 {
+			compatible = "nxp,s32g2-linflexuart",
+				     "fsl,s32v234-linflexuart";
+			reg = <0x402bc000 0x3000>;
+			interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
+			status = "disabled";
+		};
+
 		gic: interrupt-controller@50800000 {
 			compatible = "arm,gic-v3";
 			reg = <0x50800000 0x10000>,
-- 
2.30.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2021-09-08  6:46 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-08  6:45 [PATCH v2 0/8] arm64: dts: initial NXP S32G2 support Chester Lin
2021-09-08  6:45 ` Chester Lin
2021-09-08  6:45 ` [PATCH v2 1/8] dt-bindings: arm: fsl: add NXP S32G2 boards Chester Lin
2021-09-08  6:45   ` Chester Lin
2021-09-08  6:45 ` [PATCH v2 2/8] dt-bindings: serial: fsl-linflexuart: convert to json-schema format Chester Lin
2021-09-08  6:45   ` Chester Lin
2021-09-20 22:32   ` Rob Herring
2021-09-20 22:32     ` Rob Herring
2021-09-08  6:45 ` [PATCH v2 3/8] dt-bindings: serial: fsl-linflexuart: add compatible for S32G2 Chester Lin
2021-09-08  6:45   ` Chester Lin
2021-09-20 22:32   ` Rob Herring
2021-09-20 22:32     ` Rob Herring
2021-09-08  6:45 ` [PATCH v2 4/8] arm64: dts: add NXP S32G2 support Chester Lin
2021-09-08  6:45   ` Chester Lin
2021-09-08  6:45 ` Chester Lin [this message]
2021-09-08  6:45   ` [PATCH v2 5/8] arm64: dts: s32g2: add serial/uart support Chester Lin
2021-09-08  6:45 ` [PATCH v2 6/8] arm64: dts: s32g2: add VNP-EVB and VNP-RDB2 support Chester Lin
2021-09-08  6:45   ` Chester Lin
2021-09-08  6:45 ` [PATCH v2 7/8] arm64: dts: s32g2: add memory nodes for evb and rdb2 Chester Lin
2021-09-08  6:45   ` Chester Lin
2021-09-08  6:45 ` [PATCH v2 8/8] MAINTAINERS: add an entry for NXP S32G boards Chester Lin
2021-09-08  6:45   ` Chester Lin
2021-10-04  8:11 ` [PATCH v2 0/8] arm64: dts: initial NXP S32G2 support Shawn Guo
2021-10-04  8:11   ` Shawn Guo

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