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From: Mikita Lipski <mikita.lipski@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: <Harry.Wentland@amd.com>, <Sunpeng.Li@amd.com>,
	<Bhawanpreet.Lakha@amd.com>, <Rodrigo.Siqueira@amd.com>,
	<Aurabindo.Pillai@amd.com>, <qingqing.zhuo@amd.com>,
	<mikita.lipski@amd.com>, <roman.li@amd.com>,
	<Anson.Jacob@amd.com>, <wayne.lin@amd.com>, <stylon.wang@amd.com>,
	<solomon.chiu@amd.com>, Hersen Wu <hersenwu@amd.com>,
	<stable@vger.kernel.org>, Scott Foster <Scott.Foster@amd.com>
Subject: [PATCH 22/33] drm/amd/display: dsc mst 2 4K displays go dark with 2 lane HBR3
Date: Wed, 8 Sep 2021 10:54:13 -0400	[thread overview]
Message-ID: <20210908145424.3311-23-mikita.lipski@amd.com> (raw)
In-Reply-To: <20210908145424.3311-1-mikita.lipski@amd.com>

From: Hersen Wu <hersenwu@amd.com>

[Why]
call stack of amdgpu dsc mst pbn, slot num calculation is as below:
-compute_bpp_x16_from_target_bandwidth
-decide_dsc_target_bpp_x16
-setup_dsc_config
-dc_dsc_compute_bandwidth_range
-compute_mst_dsc_configs_for_link
-compute_mst_dsc_configs_for_state

from pbn -> dsc target bpp_x16

bpp_x16 is calulated by compute_bpp_x16_from_target_bandwidth.
Beside pixel clock and bpp, num_slices_h and bpp_increment_div
will also affect bpp_x16.

from dsc target bpp_x16 -> pbn

within dm_update_mst_vcpi_slots_for_dsc,
pbn = drm_dp_calc_pbn_mode(clock, bpp_x16, true);

drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc)
{
  return DIV_ROUND_UP_ULL(mul_u32_u32(clock * (bpp / 16), 64 * 1006),
            8 * 54 * 1000 * 1000);
}

bpp / 16 trunc digits after decimal point. This will cause calculation
delta. drm_dp_calc_pbn_mode does not have other informations,
like num_slices_h, bpp_increment_div. therefore, it does not do revese
calcuation properly from bpp_x16 to pbn.

pbn from drm_dp_calc_pbn_mode is less than pbn from
compute_mst_dsc_configs_for_state. This cause not enough mst slot
allocated to display. display could not visually light up.

[How]
pass pbn from compute_mst_dsc_configs_for_state to
dm_update_mst_vcpi_slots_for_dsc

Cc: stable@vger.kernel.org

Reviewed-by: Scott Foster <Scott.Foster@amd.com>
Acked-by: Mikita Lipski <mikita.lipski@amd.com>
Signed-off-by: Hersen Wu <hersenwu@amd.com>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 22 ++++++++++++++-----
 .../display/amdgpu_dm/amdgpu_dm_mst_types.c   | 18 +++++++--------
 .../display/amdgpu_dm/amdgpu_dm_mst_types.h   | 11 +++++++++-
 3 files changed, 34 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index a6c8c30f8c2d..87499ef5282c 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -7090,14 +7090,15 @@ const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
 
 #if defined(CONFIG_DRM_AMD_DC_DCN)
 static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
-					    struct dc_state *dc_state)
+					    struct dc_state *dc_state,
+					    struct dsc_mst_fairness_vars *vars)
 {
 	struct dc_stream_state *stream = NULL;
 	struct drm_connector *connector;
 	struct drm_connector_state *new_con_state;
 	struct amdgpu_dm_connector *aconnector;
 	struct dm_connector_state *dm_conn_state;
-	int i, j, clock, bpp;
+	int i, j, clock;
 	int vcpi, pbn_div, pbn = 0;
 
 	for_each_new_connector_in_state(state, connector, new_con_state, i) {
@@ -7136,9 +7137,15 @@ static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state,
 		}
 
 		pbn_div = dm_mst_get_pbn_divider(stream->link);
-		bpp = stream->timing.dsc_cfg.bits_per_pixel;
 		clock = stream->timing.pix_clk_100hz / 10;
-		pbn = drm_dp_calc_pbn_mode(clock, bpp, true);
+		/* pbn is calculated by compute_mst_dsc_configs_for_state*/
+		for (j = 0; j < dc_state->stream_count; j++) {
+			if (vars[j].aconnector == aconnector) {
+				pbn = vars[j].pbn;
+				break;
+			}
+		}
+
 		vcpi = drm_dp_mst_atomic_enable_dsc(state,
 						    aconnector->port,
 						    pbn, pbn_div,
@@ -10542,6 +10549,9 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
 	int ret, i;
 	bool lock_and_validation_needed = false;
 	struct dm_crtc_state *dm_old_crtc_state;
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+	struct dsc_mst_fairness_vars vars[MAX_PIPES];
+#endif
 
 	trace_amdgpu_dm_atomic_check_begin(state);
 
@@ -10772,10 +10782,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
 			goto fail;
 
 #if defined(CONFIG_DRM_AMD_DC_DCN)
-		if (!compute_mst_dsc_configs_for_state(state, dm_state->context))
+		if (!compute_mst_dsc_configs_for_state(state, dm_state->context, vars))
 			goto fail;
 
-		ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context);
+		ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars);
 		if (ret)
 			goto fail;
 #endif
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 705f2e67edb5..1a99fcc27078 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -518,12 +518,7 @@ struct dsc_mst_fairness_params {
 	uint32_t num_slices_h;
 	uint32_t num_slices_v;
 	uint32_t bpp_overwrite;
-};
-
-struct dsc_mst_fairness_vars {
-	int pbn;
-	bool dsc_enabled;
-	int bpp_x16;
+	struct amdgpu_dm_connector *aconnector;
 };
 
 static int kbps_to_peak_pbn(int kbps)
@@ -750,12 +745,12 @@ static void try_disable_dsc(struct drm_atomic_state *state,
 
 static bool compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
 					     struct dc_state *dc_state,
-					     struct dc_link *dc_link)
+					     struct dc_link *dc_link,
+					     struct dsc_mst_fairness_vars *vars)
 {
 	int i;
 	struct dc_stream_state *stream;
 	struct dsc_mst_fairness_params params[MAX_PIPES];
-	struct dsc_mst_fairness_vars vars[MAX_PIPES];
 	struct amdgpu_dm_connector *aconnector;
 	int count = 0;
 	bool debugfs_overwrite = false;
@@ -776,6 +771,7 @@ static bool compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
 		params[count].timing = &stream->timing;
 		params[count].sink = stream->sink;
 		aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
+		params[count].aconnector = aconnector;
 		params[count].port = aconnector->port;
 		params[count].clock_force_enable = aconnector->dsc_settings.dsc_force_enable;
 		if (params[count].clock_force_enable == DSC_CLK_FORCE_ENABLE)
@@ -798,6 +794,7 @@ static bool compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
 	}
 	/* Try no compression */
 	for (i = 0; i < count; i++) {
+		vars[i].aconnector = params[i].aconnector;
 		vars[i].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps);
 		vars[i].dsc_enabled = false;
 		vars[i].bpp_x16 = 0;
@@ -851,7 +848,8 @@ static bool compute_mst_dsc_configs_for_link(struct drm_atomic_state *state,
 }
 
 bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
-				       struct dc_state *dc_state)
+				       struct dc_state *dc_state,
+				       struct dsc_mst_fairness_vars *vars)
 {
 	int i, j;
 	struct dc_stream_state *stream;
@@ -882,7 +880,7 @@ bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
 			return false;
 
 		mutex_lock(&aconnector->mst_mgr.lock);
-		if (!compute_mst_dsc_configs_for_link(state, dc_state, stream->link)) {
+		if (!compute_mst_dsc_configs_for_link(state, dc_state, stream->link, vars)) {
 			mutex_unlock(&aconnector->mst_mgr.lock);
 			return false;
 		}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
index b38bd68121ce..900d3f7a8498 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h
@@ -39,8 +39,17 @@ void
 dm_dp_create_fake_mst_encoders(struct amdgpu_device *adev);
 
 #if defined(CONFIG_DRM_AMD_DC_DCN)
+
+struct dsc_mst_fairness_vars {
+	int pbn;
+	bool dsc_enabled;
+	int bpp_x16;
+	struct amdgpu_dm_connector *aconnector;
+};
+
 bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
-				       struct dc_state *dc_state);
+				       struct dc_state *dc_state,
+				       struct dsc_mst_fairness_vars *vars);
 #endif
 
 #endif
-- 
2.25.1


  parent reply	other threads:[~2021-09-08 14:55 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-08 14:53 [PATCH 00/33] DC Patches September 08, 2021 Mikita Lipski
2021-09-08 14:53 ` [PATCH 01/33] drm/amd/display: Add DPCD writes at key points Mikita Lipski
2021-09-08 14:53 ` [PATCH 02/33] drm/amd/display: Fix system hang at boot Mikita Lipski
2021-09-08 14:53 ` [PATCH 03/33] drm/amd/display: move bpp range decision in decide dsc bw range function Mikita Lipski
2021-09-08 14:53 ` [PATCH 04/33] drm/amd/display: update conditions to do dfp cap ext validation Mikita Lipski
2021-09-08 14:53 ` [PATCH 05/33] drm/amd/display: Add option to defer works of hpd_rx_irq Mikita Lipski
2021-09-08 14:53 ` [PATCH 06/33] drm/amd/display: Fork thread to offload work " Mikita Lipski
2021-09-08 14:53 ` [PATCH 07/33] drm/amd/display: unblock abm when odm is enabled only on configs that support it Mikita Lipski
2021-09-08 14:53 ` [PATCH 08/33] drm/amd/display: Add flag to detect dpms force off during HPD Mikita Lipski
2021-09-08 14:54 ` [PATCH 09/33] drm/amd/display: Fix dynamic link encoder access Mikita Lipski
2021-09-08 14:54 ` [PATCH 10/33] drm/amd/display: Fix false BAD_FREE warning from Coverity Mikita Lipski
2021-09-08 14:54 ` [PATCH 11/33] drm/amd/display: Fix for null pointer access for ddc pin and aux engine Mikita Lipski
2021-09-08 14:54 ` [PATCH 12/33] drm/amd/display: [FW Promotion] Release 0.0.81 Mikita Lipski
2021-09-08 14:54 ` [PATCH 13/33] drm/amd/display: Revert "dc: w/a for hard hang on HPD on native DP" Mikita Lipski
2021-09-08 14:54 ` [PATCH 14/33] drm/amd/display: 3.2.151 Mikita Lipski
2021-09-08 14:54 ` [PATCH 15/33] drm/amd/display: Fix multiple memory leaks reported by coverity Mikita Lipski
2021-09-08 14:54 ` [PATCH 16/33] drm/amd/display: Get backlight from PWM if DMCU is not initialized Mikita Lipski
2021-09-08 14:54   ` Mikita Lipski
2021-09-08 14:54 ` [PATCH 17/33] drm/amd/display: Revert "Directly retrain link from debugfs" Mikita Lipski
2021-09-08 14:54 ` [PATCH 18/33] drm/amd/display: Add regamma/degamma coefficients and set sRGB when TF is BT709 Mikita Lipski
2021-09-08 14:54 ` [PATCH 19/33] drm/amd/display: Apply w/a for hard hang on HPD Mikita Lipski
2021-09-08 14:54 ` [PATCH 20/33] drm/amd/display: Optimize bandwidth on following fast update Mikita Lipski
2021-09-08 14:54 ` [PATCH 21/33] drm/amd/display: Refine condition of cursor visibility for pipe-split Mikita Lipski
2021-09-08 14:54 ` Mikita Lipski [this message]
2021-09-08 14:54   ` [PATCH 22/33] drm/amd/display: dsc mst 2 4K displays go dark with 2 lane HBR3 Mikita Lipski
2021-09-08 14:54 ` [PATCH 23/33] drm/amd/display: Add periodic detection when zstate is enabled Mikita Lipski
2021-09-08 14:54 ` [PATCH 24/33] drm/amd/display: Add helper for blanking all dp displays Mikita Lipski
2021-09-08 14:54 ` [PATCH 25/33] drm/amd/display: [FW Promotion] Release 0.0.82 Mikita Lipski
2021-09-08 14:54 ` [PATCH 26/33] drm/amd/display: Correct degamma coefficients Mikita Lipski
2021-09-08 14:54 ` [PATCH 27/33] drm/amd/display: 3.2.152 Mikita Lipski
2021-09-08 14:54 ` [PATCH 28/33] drm/amd/display: Fix unstable HPCP compliance on Chrome Barcelo Mikita Lipski
2021-09-08 14:54 ` [PATCH 29/33] drm/amd/display: Link training retry fix for abort case Mikita Lipski
2021-09-08 14:54 ` [PATCH 30/33] drm/amd/display: Revert adding degamma coefficients Mikita Lipski
2021-09-08 14:54 ` [PATCH 31/33] drm/amd/display: Add VPG and AFMT low power support for DCN3.1 Mikita Lipski
2021-09-08 14:54 ` [PATCH 32/33] drm/amd/display: remove force_enable_edp_fec param Mikita Lipski
2021-09-08 14:54 ` [PATCH 33/33] drm/amd/display: Enable mem low power control for DCN3.1 sub-IP blocks Mikita Lipski
2021-09-10 15:11 ` [PATCH 00/33] DC Patches September 08, 2021 Wheeler, Daniel

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