From: Richard Cochran <richardcochran@gmail.com>
To: "Machnikowski, Maciej" <maciej.machnikowski@intel.com>
Cc: Andrew Lunn <andrew@lunn.ch>, Jakub Kicinski <kuba@kernel.org>,
Florian Fainelli <f.fainelli@gmail.com>,
Ido Schimmel <idosch@idosch.org>,
"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
"intel-wired-lan@lists.osuosl.org"
<intel-wired-lan@lists.osuosl.org>,
"abyagowi@fb.com" <abyagowi@fb.com>,
"Nguyen, Anthony L" <anthony.l.nguyen@intel.com>,
"davem@davemloft.net" <davem@davemloft.net>,
"linux-kselftest@vger.kernel.org"
<linux-kselftest@vger.kernel.org>,
Michal Kubecek <mkubecek@suse.cz>,
Saeed Mahameed <saeed@kernel.org>,
Michael Chan <michael.chan@broadcom.com>
Subject: Re: [PATCH net-next 1/2] rtnetlink: Add new RTM_GETEECSTATE message to get SyncE status
Date: Fri, 10 Sep 2021 07:14:23 -0700 [thread overview]
Message-ID: <20210910141423.GA21865@hoboy.vegasvil.org> (raw)
In-Reply-To: <PH0PR11MB49515C4ACE9BAD7BD9172825EAD59@PH0PR11MB4951.namprd11.prod.outlook.com>
On Thu, Sep 09, 2021 at 08:18:10AM +0000, Machnikowski, Maciej wrote:
> Controlling the clock that actually drives any components (PHY/MAC) in
> runtime can be a good way to brick the part.
I didn't say that.
> I feel that, while the reuse
> of structures may be a good idea, the userspace API for clocks is not.
> They are usually set up once at the board init level and stay like that "forever".
>
> The outputs we need to control are only a subset of all of them and they
> rather fall in the PTP pins level of details, rather than clock ones.
clk-gate.c
clk-mux.c
Making that available for user space to twiddle is a better way that
tacking on to the PTP stuff.
You can model your device as having a multiplexer in front of it.
Thanks,
Richard
WARNING: multiple messages have this Message-ID (diff)
From: Richard Cochran <richardcochran@gmail.com>
To: intel-wired-lan@osuosl.org
Subject: [Intel-wired-lan] [PATCH net-next 1/2] rtnetlink: Add new RTM_GETEECSTATE message to get SyncE status
Date: Fri, 10 Sep 2021 07:14:23 -0700 [thread overview]
Message-ID: <20210910141423.GA21865@hoboy.vegasvil.org> (raw)
In-Reply-To: <PH0PR11MB49515C4ACE9BAD7BD9172825EAD59@PH0PR11MB4951.namprd11.prod.outlook.com>
On Thu, Sep 09, 2021 at 08:18:10AM +0000, Machnikowski, Maciej wrote:
> Controlling the clock that actually drives any components (PHY/MAC) in
> runtime can be a good way to brick the part.
I didn't say that.
> I feel that, while the reuse
> of structures may be a good idea, the userspace API for clocks is not.
> They are usually set up once at the board init level and stay like that "forever".
>
> The outputs we need to control are only a subset of all of them and they
> rather fall in the PTP pins level of details, rather than clock ones.
clk-gate.c
clk-mux.c
Making that available for user space to twiddle is a better way that
tacking on to the PTP stuff.
You can model your device as having a multiplexer in front of it.
Thanks,
Richard
next prev parent reply other threads:[~2021-09-10 14:14 UTC|newest]
Thread overview: 82+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-03 15:14 [RFC v4 net-next 0/2] Add RTNL interface for SyncE Maciej Machnikowski
2021-09-03 15:14 ` [Intel-wired-lan] " Maciej Machnikowski
2021-09-03 15:14 ` [PATCH net-next 1/2] rtnetlink: Add new RTM_GETEECSTATE message to get SyncE status Maciej Machnikowski
2021-09-03 15:14 ` [Intel-wired-lan] " Maciej Machnikowski
2021-09-03 16:18 ` Stephen Hemminger
2021-09-03 16:18 ` [Intel-wired-lan] " Stephen Hemminger
2021-09-03 22:20 ` Machnikowski, Maciej
2021-09-03 22:20 ` [Intel-wired-lan] " Machnikowski, Maciej
2021-09-03 22:14 ` Jakub Kicinski
2021-09-03 22:14 ` [Intel-wired-lan] " Jakub Kicinski
2021-09-06 18:30 ` Machnikowski, Maciej
2021-09-06 18:30 ` [Intel-wired-lan] " Machnikowski, Maciej
2021-09-06 18:39 ` Jakub Kicinski
2021-09-06 18:39 ` [Intel-wired-lan] " Jakub Kicinski
2021-09-06 19:01 ` Machnikowski, Maciej
2021-09-06 19:01 ` [Intel-wired-lan] " Machnikowski, Maciej
2021-09-07 1:01 ` Jakub Kicinski
2021-09-07 1:01 ` [Intel-wired-lan] " Jakub Kicinski
2021-09-07 8:50 ` Machnikowski, Maciej
2021-09-07 8:50 ` [Intel-wired-lan] " Machnikowski, Maciej
2021-09-07 14:55 ` Jakub Kicinski
2021-09-07 14:55 ` [Intel-wired-lan] " Jakub Kicinski
2021-09-07 15:47 ` Machnikowski, Maciej
2021-09-07 15:47 ` [Intel-wired-lan] " Machnikowski, Maciej
2021-09-07 19:47 ` Jakub Kicinski
2021-09-07 19:47 ` [Intel-wired-lan] " Jakub Kicinski
2021-09-08 8:03 ` Machnikowski, Maciej
2021-09-08 8:03 ` [Intel-wired-lan] " Machnikowski, Maciej
2021-09-08 16:21 ` Jakub Kicinski
2021-09-08 16:21 ` [Intel-wired-lan] " Jakub Kicinski
2021-09-08 17:30 ` Machnikowski, Maciej
2021-09-08 17:30 ` [Intel-wired-lan] " Machnikowski, Maciej
2021-09-08 19:34 ` Andrew Lunn
2021-09-08 19:34 ` [Intel-wired-lan] " Andrew Lunn
2021-09-08 20:27 ` Machnikowski, Maciej
2021-09-08 20:27 ` [Intel-wired-lan] " Machnikowski, Maciej
2021-09-08 22:20 ` Jakub Kicinski
2021-09-08 22:20 ` [Intel-wired-lan] " Jakub Kicinski
2021-09-08 22:59 ` Andrew Lunn
2021-09-08 22:59 ` [Intel-wired-lan] " Andrew Lunn
2021-09-09 2:09 ` Richard Cochran
2021-09-09 2:09 ` [Intel-wired-lan] " Richard Cochran
2021-09-09 8:18 ` Machnikowski, Maciej
2021-09-09 8:18 ` [Intel-wired-lan] " Machnikowski, Maciej
2021-09-10 14:14 ` Richard Cochran [this message]
2021-09-10 14:14 ` Richard Cochran
2021-09-08 22:18 ` Jakub Kicinski
2021-09-08 22:18 ` [Intel-wired-lan] " Jakub Kicinski
2021-09-08 23:14 ` Andrew Lunn
2021-09-08 23:14 ` [Intel-wired-lan] " Andrew Lunn
2021-09-08 23:58 ` Jakub Kicinski
2021-09-08 23:58 ` [Intel-wired-lan] " Jakub Kicinski
2021-09-09 8:26 ` Machnikowski, Maciej
2021-09-09 8:26 ` [Intel-wired-lan] " Machnikowski, Maciej
2021-09-09 9:24 ` Machnikowski, Maciej
2021-09-09 9:24 ` [Intel-wired-lan] " Machnikowski, Maciej
2021-09-09 10:15 ` David Miller
2021-09-09 10:15 ` [Intel-wired-lan] " David Miller
2021-09-09 8:11 ` Machnikowski, Maciej
2021-09-09 8:11 ` [Intel-wired-lan] " Machnikowski, Maciej
2021-09-13 8:50 ` Ido Schimmel
2021-09-13 8:50 ` [Intel-wired-lan] " Ido Schimmel
2021-09-21 13:36 ` Ido Schimmel
2021-09-21 13:36 ` [Intel-wired-lan] " Ido Schimmel
2021-09-21 13:15 ` Ido Schimmel
2021-09-21 13:15 ` [Intel-wired-lan] " Ido Schimmel
2021-09-21 13:37 ` Machnikowski, Maciej
2021-09-21 13:37 ` [Intel-wired-lan] " Machnikowski, Maciej
2021-09-21 14:58 ` Ido Schimmel
2021-09-21 14:58 ` [Intel-wired-lan] " Ido Schimmel
2021-09-21 21:14 ` Jakub Kicinski
2021-09-21 21:14 ` [Intel-wired-lan] " Jakub Kicinski
2021-09-22 6:22 ` Ido Schimmel
2021-09-22 6:22 ` [Intel-wired-lan] " Ido Schimmel
2021-09-03 15:14 ` [PATCH net-next 2/2] ice: add support for reading SyncE DPLL state Maciej Machnikowski
2021-09-03 15:14 ` [Intel-wired-lan] " Maciej Machnikowski
2021-09-03 22:06 ` Jakub Kicinski
2021-09-03 22:06 ` [Intel-wired-lan] " Jakub Kicinski
2021-09-21 13:25 ` Ido Schimmel
2021-09-21 13:25 ` [Intel-wired-lan] " Ido Schimmel
-- strict thread matches above, loose matches on Subject: below --
2021-08-31 11:52 [PATCH net-next 0/2] Add RTNL interface for SyncE EEC state Maciej Machnikowski
2021-08-31 11:52 ` [PATCH net-next 1/2] rtnetlink: Add new RTM_GETEECSTATE message to get SyncE status Maciej Machnikowski
2021-08-31 13:44 ` Jakub Kicinski
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