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From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org,
	Matt Roper <matthew.d.roper@intel.com>,
	Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Subject: [PATCH v2 1/6] drm/i915/uncore: Convert gen6/gen7 read operations to fwtable
Date: Fri, 10 Sep 2021 13:10:25 -0700	[thread overview]
Message-ID: <20210910201030.3436066-2-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20210910201030.3436066-1-matthew.d.roper@intel.com>

On gen6-gen8 (except vlv/chv) we don't use a forcewake lookup table; we
simply check whether the register offset is < 0x40000, and return
FORCEWAKE_RENDER if it is.  To prepare for upcoming refactoring, let's
define a single-entry forcewake table from [0x0, 0x3ffff] and switch
these platforms over to use the fwtable reader functions.

v2:
 - Drop __gen6_reg_read_fw_domains which is no longer used.  (Tvrtko)

Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/intel_uncore.c | 21 ++++++++-------------
 1 file changed, 8 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index f9767054dbdf..8c09af1e9f7a 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -853,16 +853,6 @@ void assert_forcewakes_active(struct intel_uncore *uncore,
 /* We give fast paths for the really cool registers */
 #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000)
 
-#define __gen6_reg_read_fw_domains(uncore, offset) \
-({ \
-	enum forcewake_domains __fwd; \
-	if (NEEDS_FORCE_WAKE(offset)) \
-		__fwd = FORCEWAKE_RENDER; \
-	else \
-		__fwd = 0; \
-	__fwd; \
-})
-
 static int fw_range_cmp(u32 offset, const struct intel_forcewake_range *entry)
 {
 	if (offset < entry->start)
@@ -1064,6 +1054,10 @@ gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg)
 	__fwd; \
 })
 
+static const struct intel_forcewake_range __gen6_fw_ranges[] = {
+	GEN_FW_RANGE(0x0, 0x3ffff, FORCEWAKE_RENDER),
+};
+
 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
 static const struct intel_forcewake_range __chv_fw_ranges[] = {
 	GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
@@ -1623,7 +1617,6 @@ __gen_read(func, 64)
 
 __gen_reg_read_funcs(gen11_fwtable);
 __gen_reg_read_funcs(fwtable);
-__gen_reg_read_funcs(gen6);
 
 #undef __gen_reg_read_funcs
 #undef GEN6_READ_FOOTER
@@ -2111,15 +2104,17 @@ static int uncore_forcewake_init(struct intel_uncore *uncore)
 		ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
 		ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
 	} else if (GRAPHICS_VER(i915) == 8) {
+		ASSIGN_FW_DOMAINS_TABLE(uncore, __gen6_fw_ranges);
 		ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen8);
-		ASSIGN_READ_MMIO_VFUNCS(uncore, gen6);
+		ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
 	} else if (IS_VALLEYVIEW(i915)) {
 		ASSIGN_FW_DOMAINS_TABLE(uncore, __vlv_fw_ranges);
 		ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6);
 		ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
 	} else if (IS_GRAPHICS_VER(i915, 6, 7)) {
+		ASSIGN_FW_DOMAINS_TABLE(uncore, __gen6_fw_ranges);
 		ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6);
-		ASSIGN_READ_MMIO_VFUNCS(uncore, gen6);
+		ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
 	}
 
 	uncore->pmic_bus_access_nb.notifier_call = i915_pmic_bus_access_notifier;
-- 
2.25.4


WARNING: multiple messages have this Message-ID (diff)
From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org,
	Matt Roper <matthew.d.roper@intel.com>,
	Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Subject: [Intel-gfx] [PATCH v2 1/6] drm/i915/uncore: Convert gen6/gen7 read operations to fwtable
Date: Fri, 10 Sep 2021 13:10:25 -0700	[thread overview]
Message-ID: <20210910201030.3436066-2-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20210910201030.3436066-1-matthew.d.roper@intel.com>

On gen6-gen8 (except vlv/chv) we don't use a forcewake lookup table; we
simply check whether the register offset is < 0x40000, and return
FORCEWAKE_RENDER if it is.  To prepare for upcoming refactoring, let's
define a single-entry forcewake table from [0x0, 0x3ffff] and switch
these platforms over to use the fwtable reader functions.

v2:
 - Drop __gen6_reg_read_fw_domains which is no longer used.  (Tvrtko)

Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/intel_uncore.c | 21 ++++++++-------------
 1 file changed, 8 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index f9767054dbdf..8c09af1e9f7a 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -853,16 +853,6 @@ void assert_forcewakes_active(struct intel_uncore *uncore,
 /* We give fast paths for the really cool registers */
 #define NEEDS_FORCE_WAKE(reg) ((reg) < 0x40000)
 
-#define __gen6_reg_read_fw_domains(uncore, offset) \
-({ \
-	enum forcewake_domains __fwd; \
-	if (NEEDS_FORCE_WAKE(offset)) \
-		__fwd = FORCEWAKE_RENDER; \
-	else \
-		__fwd = 0; \
-	__fwd; \
-})
-
 static int fw_range_cmp(u32 offset, const struct intel_forcewake_range *entry)
 {
 	if (offset < entry->start)
@@ -1064,6 +1054,10 @@ gen6_reg_write_fw_domains(struct intel_uncore *uncore, i915_reg_t reg)
 	__fwd; \
 })
 
+static const struct intel_forcewake_range __gen6_fw_ranges[] = {
+	GEN_FW_RANGE(0x0, 0x3ffff, FORCEWAKE_RENDER),
+};
+
 /* *Must* be sorted by offset ranges! See intel_fw_table_check(). */
 static const struct intel_forcewake_range __chv_fw_ranges[] = {
 	GEN_FW_RANGE(0x2000, 0x3fff, FORCEWAKE_RENDER),
@@ -1623,7 +1617,6 @@ __gen_read(func, 64)
 
 __gen_reg_read_funcs(gen11_fwtable);
 __gen_reg_read_funcs(fwtable);
-__gen_reg_read_funcs(gen6);
 
 #undef __gen_reg_read_funcs
 #undef GEN6_READ_FOOTER
@@ -2111,15 +2104,17 @@ static int uncore_forcewake_init(struct intel_uncore *uncore)
 		ASSIGN_WRITE_MMIO_VFUNCS(uncore, fwtable);
 		ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
 	} else if (GRAPHICS_VER(i915) == 8) {
+		ASSIGN_FW_DOMAINS_TABLE(uncore, __gen6_fw_ranges);
 		ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen8);
-		ASSIGN_READ_MMIO_VFUNCS(uncore, gen6);
+		ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
 	} else if (IS_VALLEYVIEW(i915)) {
 		ASSIGN_FW_DOMAINS_TABLE(uncore, __vlv_fw_ranges);
 		ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6);
 		ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
 	} else if (IS_GRAPHICS_VER(i915, 6, 7)) {
+		ASSIGN_FW_DOMAINS_TABLE(uncore, __gen6_fw_ranges);
 		ASSIGN_WRITE_MMIO_VFUNCS(uncore, gen6);
-		ASSIGN_READ_MMIO_VFUNCS(uncore, gen6);
+		ASSIGN_READ_MMIO_VFUNCS(uncore, fwtable);
 	}
 
 	uncore->pmic_bus_access_nb.notifier_call = i915_pmic_bus_access_notifier;
-- 
2.25.4


  reply	other threads:[~2021-09-10 20:10 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-10 20:10 [PATCH v2 0/6] i915: Simplify mmio handling & add new DG2 shadow table Matt Roper
2021-09-10 20:10 ` [Intel-gfx] " Matt Roper
2021-09-10 20:10 ` Matt Roper [this message]
2021-09-10 20:10   ` [Intel-gfx] [PATCH v2 1/6] drm/i915/uncore: Convert gen6/gen7 read operations to fwtable Matt Roper
2021-09-21 13:50   ` Tvrtko Ursulin
2021-09-21 13:50     ` [Intel-gfx] " Tvrtko Ursulin
2021-09-10 20:10 ` [PATCH v2 2/6] drm/i915/uncore: Associate shadow table with uncore Matt Roper
2021-09-10 20:10   ` [Intel-gfx] " Matt Roper
2021-09-21 13:54   ` Tvrtko Ursulin
2021-09-10 20:10 ` [PATCH v2 3/6] drm/i915/uncore: Replace gen8 write functions with general fwtable Matt Roper
2021-09-10 20:10   ` [Intel-gfx] " Matt Roper
2021-09-21 13:54   ` Tvrtko Ursulin
2021-09-10 20:10 ` [PATCH v2 4/6] drm/i915/uncore: Drop gen11/gen12 mmio write handlers Matt Roper
2021-09-10 20:10   ` [Intel-gfx] " Matt Roper
2021-09-21 14:35   ` Tvrtko Ursulin
2021-09-21 14:35     ` [Intel-gfx] " Tvrtko Ursulin
2021-09-10 20:10 ` [PATCH v2 5/6] drm/i915/uncore: Drop gen11 mmio read handlers Matt Roper
2021-09-10 20:10   ` [Intel-gfx] " Matt Roper
2021-09-21 14:40   ` Tvrtko Ursulin
2021-09-21 14:40     ` [Intel-gfx] " Tvrtko Ursulin
2021-09-21 17:36   ` Lucas De Marchi
2021-09-21 17:36     ` [Intel-gfx] " Lucas De Marchi
2021-09-10 20:10 ` [PATCH v2 6/6] drm/i915/dg2: Add DG2-specific shadow register table Matt Roper
2021-09-10 20:10   ` [Intel-gfx] " Matt Roper
2021-09-21 22:35   ` Lucas De Marchi
2021-09-21 22:35     ` [Intel-gfx] " Lucas De Marchi
2021-09-10 20:25 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Simplify mmio handling & add new DG2 shadow table (rev2) Patchwork
2021-09-10 20:27 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-09-10 20:56 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-09-10 21:09   ` Matt Roper
2021-09-21 22:18     ` Vudum, Lakshminarayana
2021-09-21 16:57 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for i915: Simplify mmio handling & add new DG2 shadow table (rev3) Patchwork
2021-09-21 16:59 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-09-21 17:28 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-21 21:32 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-09-21 22:05   ` Matt Roper
2021-09-21 22:24     ` Vudum, Lakshminarayana
2021-09-21 22:14 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
2021-09-22  0:19   ` Matt Roper

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