From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Frank Chang <frank.chang@sifive.com>, Bin Meng <bin.meng@windriver.com>, Max Hsu <max.hsu@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com>, Bin Meng <bmeng.cn@gmail.com> Subject: [PATCH RESEND v2 1/4] hw/dma: sifive_pdma: reset Next* registers when Control.claim is set Date: Sun, 12 Sep 2021 21:05:45 +0800 [thread overview] Message-ID: <20210912130553.179501-2-frank.chang@sifive.com> (raw) In-Reply-To: <20210912130553.179501-1-frank.chang@sifive.com> From: Frank Chang <frank.chang@sifive.com> Setting Control.claim clears all of the chanel's Next registers. This is effective only when Control.claim is set from 0 to 1. Signed-off-by: Frank Chang <frank.chang@sifive.com> Tested-by: Max Hsu <max.hsu@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> --- hw/dma/sifive_pdma.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/hw/dma/sifive_pdma.c b/hw/dma/sifive_pdma.c index 9b2ac2017d9..d92e27dfdc4 100644 --- a/hw/dma/sifive_pdma.c +++ b/hw/dma/sifive_pdma.c @@ -54,6 +54,13 @@ #define DMA_EXEC_DST 0x110 #define DMA_EXEC_SRC 0x118 +/* + * FU540/FU740 docs are incorrect with NextConfig.wsize/rsize reset values. + * The reset values tested on Unleashed/Unmatched boards are 6 instead of 0. + */ +#define CONFIG_WRSZ_DEFAULT 6 +#define CONFIG_RDSZ_DEFAULT 6 + enum dma_chan_state { DMA_CHAN_STATE_IDLE, DMA_CHAN_STATE_STARTED, @@ -221,6 +228,7 @@ static void sifive_pdma_write(void *opaque, hwaddr offset, { SiFivePDMAState *s = opaque; int ch = SIFIVE_PDMA_CHAN_NO(offset); + bool claimed; if (ch >= SIFIVE_PDMA_CHANS) { qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid channel no %d\n", @@ -231,6 +239,17 @@ static void sifive_pdma_write(void *opaque, hwaddr offset, offset &= 0xfff; switch (offset) { case DMA_CONTROL: + claimed = !!s->chan[ch].control & CONTROL_CLAIM; + + if (!claimed && (value & CONTROL_CLAIM)) { + /* reset Next* registers */ + s->chan[ch].next_config = (CONFIG_RDSZ_DEFAULT << CONFIG_RDSZ_SHIFT) | + (CONFIG_WRSZ_DEFAULT << CONFIG_WRSZ_SHIFT); + s->chan[ch].next_bytes = 0; + s->chan[ch].next_dst = 0; + s->chan[ch].next_src = 0; + } + s->chan[ch].control = value; if (value & CONTROL_RUN) { -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Frank Chang <frank.chang@sifive.com>, Max Hsu <max.hsu@sifive.com>, Bin Meng <bmeng.cn@gmail.com>, Alistair Francis <Alistair.Francis@wdc.com>, Bin Meng <bin.meng@windriver.com>, Palmer Dabbelt <palmer@dabbelt.com> Subject: [PATCH RESEND v2 1/4] hw/dma: sifive_pdma: reset Next* registers when Control.claim is set Date: Sun, 12 Sep 2021 21:05:45 +0800 [thread overview] Message-ID: <20210912130553.179501-2-frank.chang@sifive.com> (raw) In-Reply-To: <20210912130553.179501-1-frank.chang@sifive.com> From: Frank Chang <frank.chang@sifive.com> Setting Control.claim clears all of the chanel's Next registers. This is effective only when Control.claim is set from 0 to 1. Signed-off-by: Frank Chang <frank.chang@sifive.com> Tested-by: Max Hsu <max.hsu@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> --- hw/dma/sifive_pdma.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/hw/dma/sifive_pdma.c b/hw/dma/sifive_pdma.c index 9b2ac2017d9..d92e27dfdc4 100644 --- a/hw/dma/sifive_pdma.c +++ b/hw/dma/sifive_pdma.c @@ -54,6 +54,13 @@ #define DMA_EXEC_DST 0x110 #define DMA_EXEC_SRC 0x118 +/* + * FU540/FU740 docs are incorrect with NextConfig.wsize/rsize reset values. + * The reset values tested on Unleashed/Unmatched boards are 6 instead of 0. + */ +#define CONFIG_WRSZ_DEFAULT 6 +#define CONFIG_RDSZ_DEFAULT 6 + enum dma_chan_state { DMA_CHAN_STATE_IDLE, DMA_CHAN_STATE_STARTED, @@ -221,6 +228,7 @@ static void sifive_pdma_write(void *opaque, hwaddr offset, { SiFivePDMAState *s = opaque; int ch = SIFIVE_PDMA_CHAN_NO(offset); + bool claimed; if (ch >= SIFIVE_PDMA_CHANS) { qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid channel no %d\n", @@ -231,6 +239,17 @@ static void sifive_pdma_write(void *opaque, hwaddr offset, offset &= 0xfff; switch (offset) { case DMA_CONTROL: + claimed = !!s->chan[ch].control & CONTROL_CLAIM; + + if (!claimed && (value & CONTROL_CLAIM)) { + /* reset Next* registers */ + s->chan[ch].next_config = (CONFIG_RDSZ_DEFAULT << CONFIG_RDSZ_SHIFT) | + (CONFIG_WRSZ_DEFAULT << CONFIG_WRSZ_SHIFT); + s->chan[ch].next_bytes = 0; + s->chan[ch].next_dst = 0; + s->chan[ch].next_src = 0; + } + s->chan[ch].control = value; if (value & CONTROL_RUN) { -- 2.25.1
next prev parent reply other threads:[~2021-09-12 13:10 UTC|newest] Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-09-12 13:05 [PATCH RESEND v2 0/4] hw/dma: Align SiFive PDMA behavior with real hardware frank.chang 2021-09-12 13:05 ` frank.chang [this message] 2021-09-12 13:05 ` [PATCH RESEND v2 1/4] hw/dma: sifive_pdma: reset Next* registers when Control.claim is set frank.chang 2021-09-12 13:05 ` [PATCH RESEND v2 2/4] hw/dma: sifive_pdma: claim bit must be set before DMA transactions frank.chang 2021-09-12 13:05 ` frank.chang 2021-09-12 13:05 ` [PATCH RESEND v2 3/4] hw/dma: sifive_pdma: allow non-multiple transaction size transactions frank.chang 2021-09-12 13:05 ` frank.chang 2021-09-12 13:05 ` [PATCH RESEND v2 4/4] hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer frank.chang 2021-09-12 13:05 ` frank.chang 2021-09-14 2:24 ` Alistair Francis 2021-09-14 2:24 ` Alistair Francis
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