From: "Cédric Le Goater" <clg@kaod.org> To: Peter Maydell <peter.maydell@linaro.org> Cc: "Andrew Jeffery" <andrew@aj.id.au>, qemu-devel@nongnu.org, qemu-arm@nongnu.org, "Joel Stanley" <joel@jms.id.au>, "Rashmica Gupta" <rashmica.g@gmail.com>, "Cédric Le Goater" <clg@kaod.org> Subject: [PULL 06/14] hw: aspeed_gpio: Clarify GPIO controller name Date: Mon, 13 Sep 2021 18:12:56 +0200 [thread overview] Message-ID: <20210913161304.3805652-7-clg@kaod.org> (raw) In-Reply-To: <20210913161304.3805652-1-clg@kaod.org> From: Joel Stanley <joel@jms.id.au> There are two GPIO controllers in the ast2600; one is 3.3V and the other is 1.8V. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Rashmica Gupta <rashmica.g@gmail.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210713065854.134634-4-joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> --- hw/gpio/aspeed_gpio.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c index dc721aec5da7..dfa6d6cb40a9 100644 --- a/hw/gpio/aspeed_gpio.c +++ b/hw/gpio/aspeed_gpio.c @@ -164,12 +164,12 @@ #define GPIO_YZAAAB_DIRECTION (0x1E4 >> 2) #define GPIO_AC_DATA_VALUE (0x1E8 >> 2) #define GPIO_AC_DIRECTION (0x1EC >> 2) -#define GPIO_3_6V_MEM_SIZE 0x1F0 -#define GPIO_3_6V_REG_ARRAY_SIZE (GPIO_3_6V_MEM_SIZE >> 2) +#define GPIO_3_3V_MEM_SIZE 0x1F0 +#define GPIO_3_3V_REG_ARRAY_SIZE (GPIO_3_3V_MEM_SIZE >> 2) /* AST2600 only - 1.8V gpios */ /* - * The AST2600 two copies of the GPIO controller: the same 3.6V gpios as the + * The AST2600 two copies of the GPIO controller: the same 3.3V gpios as the * AST2400 (memory offsets 0x0-0x198) and a second controller with 1.8V gpios * (memory offsets 0x800-0x9D4). */ @@ -380,7 +380,7 @@ static uint32_t update_value_control_source(GPIOSets *regs, uint32_t old_value, return new_value; } -static const AspeedGPIOReg aspeed_3_6v_gpios[GPIO_3_6V_REG_ARRAY_SIZE] = { +static const AspeedGPIOReg aspeed_3_3v_gpios[GPIO_3_3V_REG_ARRAY_SIZE] = { /* Set ABCD */ [GPIO_ABCD_DATA_VALUE] = { 0, gpio_reg_data_value }, [GPIO_ABCD_DIRECTION] = { 0, gpio_reg_direction }, @@ -800,7 +800,7 @@ static const GPIOSetProperties ast2500_set_props[] = { [7] = {0x000000ff, 0x000000ff, {"AC"} }, }; -static GPIOSetProperties ast2600_3_6v_set_props[] = { +static GPIOSetProperties ast2600_3_3v_set_props[] = { [0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} }, [1] = {0xffffffff, 0xffffffff, {"E", "F", "G", "H"} }, [2] = {0xffffffff, 0xffffffff, {"I", "J", "K", "L"} }, @@ -927,7 +927,7 @@ static void aspeed_gpio_ast2400_class_init(ObjectClass *klass, void *data) agc->nr_gpio_pins = 216; agc->nr_gpio_sets = 7; agc->gap = 196; - agc->reg_table = aspeed_3_6v_gpios; + agc->reg_table = aspeed_3_3v_gpios; } static void aspeed_gpio_2500_class_init(ObjectClass *klass, void *data) @@ -938,17 +938,17 @@ static void aspeed_gpio_2500_class_init(ObjectClass *klass, void *data) agc->nr_gpio_pins = 228; agc->nr_gpio_sets = 8; agc->gap = 220; - agc->reg_table = aspeed_3_6v_gpios; + agc->reg_table = aspeed_3_3v_gpios; } -static void aspeed_gpio_ast2600_3_6v_class_init(ObjectClass *klass, void *data) +static void aspeed_gpio_ast2600_3_3v_class_init(ObjectClass *klass, void *data) { AspeedGPIOClass *agc = ASPEED_GPIO_CLASS(klass); - agc->props = ast2600_3_6v_set_props; + agc->props = ast2600_3_3v_set_props; agc->nr_gpio_pins = 208; agc->nr_gpio_sets = 7; - agc->reg_table = aspeed_3_6v_gpios; + agc->reg_table = aspeed_3_3v_gpios; } static void aspeed_gpio_ast2600_1_8v_class_init(ObjectClass *klass, void *data) @@ -984,10 +984,10 @@ static const TypeInfo aspeed_gpio_ast2500_info = { .instance_init = aspeed_gpio_init, }; -static const TypeInfo aspeed_gpio_ast2600_3_6v_info = { +static const TypeInfo aspeed_gpio_ast2600_3_3v_info = { .name = TYPE_ASPEED_GPIO "-ast2600", .parent = TYPE_ASPEED_GPIO, - .class_init = aspeed_gpio_ast2600_3_6v_class_init, + .class_init = aspeed_gpio_ast2600_3_3v_class_init, .instance_init = aspeed_gpio_init, }; @@ -1003,7 +1003,7 @@ static void aspeed_gpio_register_types(void) type_register_static(&aspeed_gpio_info); type_register_static(&aspeed_gpio_ast2400_info); type_register_static(&aspeed_gpio_ast2500_info); - type_register_static(&aspeed_gpio_ast2600_3_6v_info); + type_register_static(&aspeed_gpio_ast2600_3_3v_info); type_register_static(&aspeed_gpio_ast2600_1_8v_info); } -- 2.31.1
next prev parent reply other threads:[~2021-09-13 16:53 UTC|newest] Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-09-13 16:12 [PULL 00/14] aspeed queue Cédric Le Goater 2021-09-13 16:12 ` [PULL 01/14] hw: arm: aspeed: Enable eth0 interface for aspeed-ast2600-evb Cédric Le Goater 2021-09-13 16:12 ` [PULL 02/14] hw: arm: aspeed: Enable mac0/1 instead of mac1/2 for g220a Cédric Le Goater 2021-09-13 16:12 ` [PULL 03/14] watchdog: aspeed: Sanitize control register values Cédric Le Goater 2021-09-13 16:12 ` [PULL 04/14] watchdog: aspeed: Fix sequential control writes Cédric Le Goater 2021-09-13 16:12 ` [PULL 05/14] hw: aspeed_gpio: Simplify 1.8V defines Cédric Le Goater 2021-09-13 16:12 ` Cédric Le Goater [this message] 2021-09-13 16:12 ` [PULL 07/14] misc/pca9552: Fix LED status register indexing in pca955x_get_led() Cédric Le Goater 2021-09-13 16:12 ` [PULL 08/14] arm/aspeed: rainier: Add i2c eeproms and muxes Cédric Le Goater 2021-09-13 16:12 ` [PULL 09/14] aspeed: Emulate the AST2600A3 Cédric Le Goater 2021-09-13 16:13 ` [PULL 10/14] hw/misc: Add Infineon DPS310 sensor model Cédric Le Goater 2021-09-13 16:13 ` [PULL 11/14] arm/aspeed: Add DPS310 to Witherspoon and Rainier Cédric Le Goater 2021-09-13 16:13 ` [PULL 12/14] hw/arm/aspeed: Initialize AST2600 UART clock selection registers Cédric Le Goater 2021-09-13 16:13 ` [PULL 13/14] hw/arm/aspeed: Allow machine to set UART default Cédric Le Goater 2021-09-13 16:13 ` [PULL 14/14] hw/arm/aspeed: Add Fuji machine type Cédric Le Goater 2021-09-14 10:56 ` Cédric Le Goater 2021-09-14 11:59 ` Peter Delevoryas 2021-09-14 12:14 ` Joel Stanley 2021-09-14 12:26 ` Peter Maydell 2021-09-14 15:22 ` Richard Henderson 2021-09-15 7:42 ` Deprecate 32-bit hosts? (was: Re: [PULL 14/14] hw/arm/aspeed: Add Fuji machine type) Thomas Huth 2021-09-15 7:54 ` Philippe Mathieu-Daudé 2021-09-15 8:37 ` Daniel P. Berrangé 2021-09-15 8:51 ` Philippe Mathieu-Daudé 2021-09-15 9:05 ` Daniel P. Berrangé 2021-09-16 12:29 ` [PULL 14/14] hw/arm/aspeed: Add Fuji machine type Cédric Le Goater 2021-09-16 13:53 ` Philippe Mathieu-Daudé 2021-09-16 14:06 ` Cédric Le Goater 2021-09-16 14:07 ` Peter Maydell 2021-09-14 10:51 ` [PULL 00/14] aspeed queue Peter Maydell 2021-09-14 10:58 ` Cédric Le Goater 2021-09-14 11:38 ` Philippe Mathieu-Daudé -- strict thread matches above, loose matches on Subject: below -- 2021-09-20 8:09 Cédric Le Goater 2021-09-20 8:09 ` [PULL 06/14] hw: aspeed_gpio: Clarify GPIO controller name Cédric Le Goater 2021-09-03 19:40 [PULL 00/14] aspeed queue Cédric Le Goater 2021-09-03 19:41 ` [PULL 06/14] hw: aspeed_gpio: Clarify GPIO controller name Cédric Le Goater
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