[PATCH 1/8] arm: socfpga: vining: Drop meaningless comment

[PATCH 1/8] arm: socfpga: vining: Drop meaningless comment

[Marek Vasut]

The comment is no longer meaningful due to DT conversion, drop it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
---
 include/configs/socfpga_vining_fpga.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h
index 06976d804c7..38a77535893 100644
--- a/include/configs/socfpga_vining_fpga.h
+++ b/include/configs/socfpga_vining_fpga.h
@@ -17,8 +17,6 @@
 #define CONFIG_LOADADDR		0x01000000
 #define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
 
-/* Ethernet on SoC (EMAC) */
-
 /* Extra Environment */
 #define CONFIG_HOSTNAME			"socfpga_vining_fpga"
 
-- 
2.33.0

[PATCH 2/8] arm: socfpga: vining: Increase environment size

[Marek Vasut]

Increase the environment size from 4k to 16k to prevent
environment from becoming full.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
---
 configs/socfpga_vining_fpga_defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig
index b418efbf895..452e5b48f3a 100644
--- a/configs/socfpga_vining_fpga_defconfig
+++ b/configs/socfpga_vining_fpga_defconfig
@@ -1,6 +1,6 @@
 CONFIG_ARM=y
 CONFIG_ARCH_SOCFPGA=y
-CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_SIZE=0x4000
 CONFIG_ENV_OFFSET=0x100000
 CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DM_GPIO=y
-- 
2.33.0

RE: [PATCH 2/8] arm: socfpga: vining: Increase environment size

[Chee, Tien Fong]

> -----Original Message-----
> From: Marek Vasut <marex@denx.de>
> Sent: Tuesday, 14 September, 2021 11:26 AM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut <marex@denx.de>; Lim, Elly Siew Chin
> <elly.siew.chin.lim@intel.com>; Simon Goldschmidt
> <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong
> <tien.fong.chee@intel.com>
> Subject: [PATCH 2/8] arm: socfpga: vining: Increase environment size
> 
> Increase the environment size from 4k to 16k to prevent environment from
> becoming full.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
>  configs/socfpga_vining_fpga_defconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>

Regards,
TF

[PATCH 3/8] arm: socfpga: vining: Set USB gadget manufacturer to Softing with capital S

[Marek Vasut]

This was configured in downstream, so it is likely that most of the
custom software used around the device depends on it. Make upstream
compatible.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
---
 configs/socfpga_vining_fpga_defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig
index 452e5b48f3a..5d8970e57ca 100644
--- a/configs/socfpga_vining_fpga_defconfig
+++ b/configs/socfpga_vining_fpga_defconfig
@@ -91,7 +91,7 @@ CONFIG_DESIGNWARE_SPI=y
 CONFIG_USB=y
 CONFIG_USB_DWC2=y
 CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="softing"
+CONFIG_USB_GADGET_MANUFACTURER="Softing"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
 CONFIG_USB_GADGET_DWC2_OTG=y
-- 
2.33.0

RE: [PATCH 3/8] arm: socfpga: vining: Set USB gadget manufacturer to Softing with capital S

[Chee, Tien Fong]

> -----Original Message-----
> From: Marek Vasut <marex@denx.de>
> Sent: Tuesday, 14 September, 2021 11:26 AM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut <marex@denx.de>; Lim, Elly Siew Chin
> <elly.siew.chin.lim@intel.com>; Simon Goldschmidt
> <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong
> <tien.fong.chee@intel.com>
> Subject: [PATCH 3/8] arm: socfpga: vining: Set USB gadget manufacturer to
> Softing with capital S
> 
> This was configured in downstream, so it is likely that most of the custom
> software used around the device depends on it. Make upstream compatible.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
>  configs/socfpga_vining_fpga_defconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>

Regards,
TF

[PATCH 4/8] arm: socfpga: vining: Set default SPI NOR mode and frequency

[Marek Vasut]

The SPI NOR bus mode is 0 on this system, update it accordingly.
Increase frequency to 40 MHz and enable SFDP parsing, since the
flashes on this system support that and it is a huge performance
improvement.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
---
 configs/socfpga_vining_fpga_defconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig
index 5d8970e57ca..4dcf4f7bf9e 100644
--- a/configs/socfpga_vining_fpga_defconfig
+++ b/configs/socfpga_vining_fpga_defconfig
@@ -74,6 +74,9 @@ CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=70
 CONFIG_MMC_DW=y
 CONFIG_MTD=y
+CONFIG_SF_DEFAULT_MODE=0x0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
-- 
2.33.0

RE: [PATCH 4/8] arm: socfpga: vining: Set default SPI NOR mode and frequency

[Chee, Tien Fong]

> -----Original Message-----
> From: Marek Vasut <marex@denx.de>
> Sent: Tuesday, 14 September, 2021 11:26 AM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut <marex@denx.de>; Lim, Elly Siew Chin
> <elly.siew.chin.lim@intel.com>; Simon Goldschmidt
> <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong
> <tien.fong.chee@intel.com>
> Subject: [PATCH 4/8] arm: socfpga: vining: Set default SPI NOR mode and
> frequency
> 
> The SPI NOR bus mode is 0 on this system, update it accordingly.
> Increase frequency to 40 MHz and enable SFDP parsing, since the flashes on
> this system support that and it is a huge performance improvement.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
>  configs/socfpga_vining_fpga_defconfig | 3 +++
>  1 file changed, 3 insertions(+)
> 

Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>

Regards,
TF

[PATCH 5/8] arm: socfpga: vining: Un-disable WDT in DT

[Marek Vasut]

The WDT on this system should be enabled, make it so.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi
index 2e4468e8d80..9e8be282005 100644
--- a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi
@@ -15,10 +15,6 @@
 	};
 };
 
-&watchdog0 {
-	status = "disabled";
-};
-
 &mmc {
 	status = "disabled";
 };
-- 
2.33.0

RE: [PATCH 5/8] arm: socfpga: vining: Un-disable WDT in DT

[Chee, Tien Fong]

> -----Original Message-----
> From: Marek Vasut <marex@denx.de>
> Sent: Tuesday, 14 September, 2021 11:26 AM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut <marex@denx.de>; Lim, Elly Siew Chin
> <elly.siew.chin.lim@intel.com>; Simon Goldschmidt
> <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong
> <tien.fong.chee@intel.com>
> Subject: [PATCH 5/8] arm: socfpga: vining: Un-disable WDT in DT
> 
> The WDT on this system should be enabled, make it so.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
>  arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi | 4 ----
>  1 file changed, 4 deletions(-)
> 

Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>

Regards,
TF

[PATCH 6/8] arm: socfpga: vining: Fix UDC controller phandle in DT

[Marek Vasut]

The USB peripheral controller is the DWC2 controller 1, not 0.
Update the phandle to fix UDC support on this board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
---
 arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi
index 9e8be282005..fb05c31d87b 100644
--- a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi
@@ -11,7 +11,7 @@
 /{
 	aliases {
 		spi0 = "/soc/spi@ff705000";
-		udc0 = &usb0;
+		udc0 = &usb1;
 	};
 };
 
-- 
2.33.0

RE: [PATCH 6/8] arm: socfpga: vining: Fix UDC controller phandle in DT

[Chee, Tien Fong]

> -----Original Message-----
> From: Marek Vasut <marex@denx.de>
> Sent: Tuesday, 14 September, 2021 11:26 AM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut <marex@denx.de>; Lim, Elly Siew Chin
> <elly.siew.chin.lim@intel.com>; Simon Goldschmidt
> <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong
> <tien.fong.chee@intel.com>
> Subject: [PATCH 6/8] arm: socfpga: vining: Fix UDC controller phandle in DT
> 
> The USB peripheral controller is the DWC2 controller 1, not 0.
> Update the phandle to fix UDC support on this board.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
>  arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>

Regards,
TF

[PATCH 7/8] arm: socfpga: vining: Enable DW I2C driver

[Marek Vasut]

The Designware I2C IP is used to communicate with I2C peripherals on
SoCFPGA, and required to access I2C EEPROM on this board. Enable it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
---
 configs/socfpga_vining_fpga_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig
index 4dcf4f7bf9e..cbdb897f19f 100644
--- a/configs/socfpga_vining_fpga_defconfig
+++ b/configs/socfpga_vining_fpga_defconfig
@@ -56,6 +56,7 @@ CONFIG_DFU_SF=y
 CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000
 CONFIG_DWAPB_GPIO=y
 CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
 CONFIG_LED_STATUS=y
 CONFIG_LED_STATUS_GPIO=y
 CONFIG_LED_STATUS0=y
-- 
2.33.0

RE: [PATCH 7/8] arm: socfpga: vining: Enable DW I2C driver

[Chee, Tien Fong]

> -----Original Message-----
> From: Marek Vasut <marex@denx.de>
> Sent: Tuesday, 14 September, 2021 11:26 AM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut <marex@denx.de>; Lim, Elly Siew Chin
> <elly.siew.chin.lim@intel.com>; Simon Goldschmidt
> <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong
> <tien.fong.chee@intel.com>
> Subject: [PATCH 7/8] arm: socfpga: vining: Enable DW I2C driver
> 
> The Designware I2C IP is used to communicate with I2C peripherals on
> SoCFPGA, and required to access I2C EEPROM on this board. Enable it.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
>  configs/socfpga_vining_fpga_defconfig | 1 +
>  1 file changed, 1 insertion(+)
> 

Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>

Regards,
TF

[PATCH 8/8] arm: socfpga: vining: Let DWMAC configure PHY reset GPIO

[Marek Vasut]

The DM DWMAC driver is perfectly capable of configuring the ethernet
PHY reset GPIO, let the driver do it instead of doing it in the board
file.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
---
 board/softing/vining_fpga/socfpga.c | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/board/softing/vining_fpga/socfpga.c b/board/softing/vining_fpga/socfpga.c
index aaedf034504..22992273911 100644
--- a/board/softing/vining_fpga/socfpga.c
+++ b/board/softing/vining_fpga/socfpga.c
@@ -23,7 +23,6 @@ DECLARE_GLOBAL_DATA_PTR;
  */
 int board_late_init(void)
 {
-	const unsigned int phy_nrst_gpio = 0;
 	const unsigned int usb_nrst_gpio = 35;
 	int ret;
 
@@ -33,12 +32,6 @@ int board_late_init(void)
 	/* Address of boot parameters for ATAG (if ATAG is used) */
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
-	ret = gpio_request(phy_nrst_gpio, "phy_nrst_gpio");
-	if (!ret)
-		gpio_direction_output(phy_nrst_gpio, 1);
-	else
-		printf("Cannot remove PHY from reset!\n");
-
 	ret = gpio_request(usb_nrst_gpio, "usb_nrst_gpio");
 	if (!ret)
 		gpio_direction_output(usb_nrst_gpio, 1);
-- 
2.33.0

RE: [PATCH 8/8] arm: socfpga: vining: Let DWMAC configure PHY reset GPIO

[Chee, Tien Fong]

> -----Original Message-----
> From: Marek Vasut <marex@denx.de>
> Sent: Tuesday, 14 September, 2021 11:26 AM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut <marex@denx.de>; Lim, Elly Siew Chin
> <elly.siew.chin.lim@intel.com>; Simon Goldschmidt
> <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong
> <tien.fong.chee@intel.com>
> Subject: [PATCH 8/8] arm: socfpga: vining: Let DWMAC configure PHY reset
> GPIO
> 
> The DM DWMAC driver is perfectly capable of configuring the ethernet PHY
> reset GPIO, let the driver do it instead of doing it in the board file.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
>  board/softing/vining_fpga/socfpga.c | 7 -------
>  1 file changed, 7 deletions(-)
> 

Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>

Regards,
TF

RE: [PATCH 1/8] arm: socfpga: vining: Drop meaningless comment

[Chee, Tien Fong]

> -----Original Message-----
> From: Marek Vasut <marex@denx.de>
> Sent: Tuesday, 14 September, 2021 11:25 AM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut <marex@denx.de>; Lim, Elly Siew Chin
> <elly.siew.chin.lim@intel.com>; Simon Goldschmidt
> <simon.k.r.goldschmidt@gmail.com>; Chee, Tien Fong
> <tien.fong.chee@intel.com>
> Subject: [PATCH 1/8] arm: socfpga: vining: Drop meaningless comment
> 
> The comment is no longer meaningful due to DT conversion, drop it.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
>  include/configs/socfpga_vining_fpga.h | 2 --
>  1 file changed, 2 deletions(-)
> 

Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>

Regards,
TF