* [PATCH] ARM: dts: ux500: Tag Janice display SPI correct
@ 2021-09-14 16:27 Linus Walleij
0 siblings, 0 replies; only message in thread
From: Linus Walleij @ 2021-09-14 16:27 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Linus Walleij
The s6e63m0 display used "type 3" SPI communication so
flag the device as using negative clocking and polarity
on the SPI bus.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/boot/dts/ste-ux500-samsung-janice.dts | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts
index f14cf316a70a..825b62146134 100644
--- a/arch/arm/boot/dts/ste-ux500-samsung-janice.dts
+++ b/arch/arm/boot/dts/ste-ux500-samsung-janice.dts
@@ -266,6 +266,9 @@ panel@0 {
pinctrl-names = "default";
pinctrl-0 = <&panel_default_mode>;
spi-3wire;
+ /* TYPE 3: inverse clock polarity and phase */
+ spi-cpha;
+ spi-cpol;
port {
panel_in: endpoint {
--
2.31.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] only message in thread
only message in thread, other threads:[~2021-09-14 16:32 UTC | newest]
Thread overview: (only message) (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-09-14 16:27 [PATCH] ARM: dts: ux500: Tag Janice display SPI correct Linus Walleij
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.