* [PATCH v1 1/9] soc: mediatek: mmsys: expand MDP enum for chip independence architecture
@ 2021-09-17 2:51 roy-cw.yeh
2021-09-17 2:51 ` [PATCH v1 2/9] soc: mediatek: mutex: expand parameter for mdp mutex function roy-cw.yeh
` (6 more replies)
0 siblings, 7 replies; 9+ messages in thread
From: roy-cw.yeh @ 2021-09-17 2:51 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, Roy-CW . Yeh,
jason-jh . lin, daoyuan huang, Ping-Hsun Wu, Moudy Ho,
Enric Balletbo i Serra, Yongqiang Niu, devicetree, linux-kernel,
linux-media, linux-arm-kernel, linux-mediatek
From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
Expand mdp related enum for chip independence architecture
Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
drivers/soc/mediatek/mtk-mmsys.c | 2 -
include/linux/soc/mediatek/mtk-mmsys.h | 89 ++++++++++++++++++++------
2 files changed, 70 insertions(+), 21 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index b16e6a2628c5..cbae8063a187 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -128,7 +128,6 @@ void mtk_mmsys_mdp_connect(struct device *dev, struct mmsys_cmdq_cmd *cmd,
int i;
WARN_ON(!routes);
- WARN_ON(mmsys->subsys_id == 0);
for (i = 0; i < mmsys->data->mdp_num_routes; i++)
if (cur == routes[i].from_comp && next == routes[i].to_comp)
cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id,
@@ -145,7 +144,6 @@ void mtk_mmsys_mdp_disconnect(struct device *dev, struct mmsys_cmdq_cmd *cmd,
const struct mtk_mmsys_routes *routes = mmsys->data->mdp_routes;
int i;
- WARN_ON(mmsys->subsys_id == 0);
for (i = 0; i < mmsys->data->mdp_num_routes; i++)
if (cur == routes[i].from_comp && next == routes[i].to_comp)
cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id,
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 113d33e2155f..acf4bd3deac1 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -76,33 +76,84 @@ enum mtk_mdp_comp_id {
/* MDP */
MDP_COMP_CAMIN, /* 9 */
MDP_COMP_CAMIN2, /* 10 */
- MDP_COMP_RDMA0, /* 11 */
- MDP_COMP_AAL0, /* 12 */
- MDP_COMP_CCORR0, /* 13 */
- MDP_COMP_RSZ0, /* 14 */
- MDP_COMP_RSZ1, /* 15 */
- MDP_COMP_TDSHP0, /* 16 */
- MDP_COMP_COLOR0, /* 17 */
- MDP_COMP_PATH0_SOUT, /* 18 */
- MDP_COMP_PATH1_SOUT, /* 19 */
- MDP_COMP_WROT0, /* 20 */
- MDP_COMP_WDMA, /* 21 */
-
- /* Dummy Engine */
- MDP_COMP_RDMA1, /* 22 */
- MDP_COMP_RSZ2, /* 23 */
- MDP_COMP_TDSHP1, /* 24 */
- MDP_COMP_WROT1, /* 25 */
+ MDP_COMP_SPLIT, /* 11 */
+ MDP_COMP_SPLIT2, /* 12 */
+ MDP_COMP_RDMA0, /* 13 */
+ MDP_COMP_RDMA1, /* 14 */
+ MDP_COMP_RDMA2, /* 15 */
+ MDP_COMP_RDMA3, /* 16 */
+ MDP_COMP_STITCH, /* 17 */
+ MDP_COMP_FG0, /* 18 */
+ MDP_COMP_FG1, /* 19 */
+ MDP_COMP_FG2, /* 20 */
+ MDP_COMP_FG3, /* 21 */
+ MDP_COMP_TO_SVPP2MOUT, /* 22 */
+ MDP_COMP_TO_SVPP3MOUT, /* 23 */
+ MDP_COMP_TO_WARP0MOUT, /* 24 */
+ MDP_COMP_TO_WARP1MOUT, /* 25 */
+ MDP_COMP_VPP0_SOUT, /* 26 */
+ MDP_COMP_VPP1_SOUT, /* 27 */
+ MDP_COMP_PQ0_SOUT, /* 28 */
+ MDP_COMP_PQ1_SOUT, /* 29 */
+ MDP_COMP_HDR0, /* 30 */
+ MDP_COMP_HDR1, /* 31 */
+ MDP_COMP_HDR2, /* 32 */
+ MDP_COMP_HDR3, /* 33 */
+ MDP_COMP_AAL0, /* 34 */
+ MDP_COMP_AAL1, /* 35 */
+ MDP_COMP_AAL2, /* 36 */
+ MDP_COMP_AAL3, /* 37 */
+ MDP_COMP_CCORR0, /* 38 */
+ MDP_COMP_RSZ0, /* 39 */
+ MDP_COMP_RSZ1, /* 40 */
+ MDP_COMP_RSZ2, /* 41 */
+ MDP_COMP_RSZ3, /* 42 */
+ MDP_COMP_TDSHP0, /* 43 */
+ MDP_COMP_TDSHP1, /* 44 */
+ MDP_COMP_TDSHP2, /* 45 */
+ MDP_COMP_TDSHP3, /* 46 */
+ MDP_COMP_COLOR0, /* 47 */
+ MDP_COMP_COLOR1, /* 48 */
+ MDP_COMP_COLOR2, /* 49 */
+ MDP_COMP_COLOR3, /* 50 */
+ MDP_COMP_OVL0, /* 51 */
+ MDP_COMP_OVL1, /* 52 */
+ MDP_COMP_PAD0, /* 53 */
+ MDP_COMP_PAD1, /* 54 */
+ MDP_COMP_PAD2, /* 55 */
+ MDP_COMP_PAD3, /* 56 */
+ MDP_COMP_TCC0, /* 56 */
+ MDP_COMP_TCC1, /* 57 */
+ MDP_COMP_WROT0, /* 58 */
+ MDP_COMP_WROT1, /* 59 */
+ MDP_COMP_WROT2, /* 60 */
+ MDP_COMP_WROT3, /* 61 */
+ MDP_COMP_WDMA, /* 62 */
+ MDP_COMP_MERGE2, /* 63 */
+ MDP_COMP_MERGE3, /* 64 */
+ MDP_COMP_PATH0_SOUT, /* 65 */
+ MDP_COMP_PATH1_SOUT, /* 66 */
+ MDP_COMP_VDO0DL0, /* 67 */
+ MDP_COMP_VDO1DL0, /* 68 */
+ MDP_COMP_VDO0DL1, /* 69 */
+ MDP_COMP_VDO1DL1, /* 70 */
MDP_MAX_COMP_COUNT /* ALWAYS keep at the end */
};
enum mtk_mdp_pipe_id {
+ MDP_PIPE_IMGI = 0,
MDP_PIPE_RDMA0,
- MDP_PIPE_IMGI,
MDP_PIPE_WPEI,
MDP_PIPE_WPEI2,
- MDP_PIPE_MAX
+ MDP_PIPE_RDMA1,
+ MDP_PIPE_RDMA2,
+ MDP_PIPE_RDMA3,
+ MDP_PIPE_SPLIT,
+ MDP_PIPE_SPLIT2,
+ MDP_PIPE_VPP0_SOUT,
+ MDP_PIPE_VPP1_SOUT,
+ MDP_PIPE_MAX,
};
enum mtk_isp_ctrl {
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v1 2/9] soc: mediatek: mutex: expand parameter for mdp mutex function
2021-09-17 2:51 [PATCH v1 1/9] soc: mediatek: mmsys: expand MDP enum for chip independence architecture roy-cw.yeh
@ 2021-09-17 2:51 ` roy-cw.yeh
2021-09-17 2:51 ` [PATCH v1 3/9] media: platform: mtk-mdp3: add chip independence architecture roy-cw.yeh
` (5 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: roy-cw.yeh @ 2021-09-17 2:51 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, Roy-CW . Yeh,
jason-jh . lin, daoyuan huang, Ping-Hsun Wu, Moudy Ho,
Enric Balletbo i Serra, Yongqiang Niu, devicetree, linux-kernel,
linux-media, linux-arm-kernel, linux-mediatek
From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
Expand parameter for mdp mutex function
Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
drivers/soc/mediatek/mtk-mutex.c | 26 ++++++++++++++++++--------
include/linux/soc/mediatek/mtk-mutex.h | 2 +-
2 files changed, 19 insertions(+), 9 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 814f58f692cf..c100a5249016 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -25,8 +25,9 @@
#define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
#define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
#define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
-#define DISP_REG_MUTEX_MOD(mutex_mod_reg, n) (mutex_mod_reg + 0x20 * (n))
-#define DISP_REG_MUTEX_SOF(mutex_sof_reg, n) (mutex_sof_reg + 0x20 * (n))
+#define DISP_REG_MUTEX_MOD(mutex_mod_reg, n) ((mutex_mod_reg) + 0x20 * (n))
+#define DISP_REG_MUTEX_MOD1(mutex_mod_reg, n) ((mutex_mod_reg) + 0x20 * (n) + 0x4)
+#define DISP_REG_MUTEX_SOF(mutex_sof_reg, n) ((mutex_sof_reg) + 0x20 * (n))
#define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n))
#define INT_MUTEX BIT(1)
@@ -116,6 +117,11 @@
#define MT8183_MUTEX_MDP_MOD_MASK 0x07FFFFFF
#define MT8183_MUTEX_MDP_SOF_MASK 0x00000007
+#define MT8183_MDP_PIPE_IMGI MT8183_MUTEX_MDP_START
+#define MT8183_MDP_PIPE_RDMA0 (MT8183_MUTEX_MDP_START + 1)
+#define MT8183_MDP_PIPE_WPEI (MT8183_MUTEX_MDP_START + 2)
+#define MT8183_MDP_PIPE_WPEI2 (MT8183_MUTEX_MDP_START + 3)
+
struct mtk_mutex {
int id;
bool claimed;
@@ -254,10 +260,10 @@ static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
/* indicate which mutex is used by each pipepline */
static const unsigned int mt8183_mutex_mdp_offset[MDP_PIPE_MAX] = {
- [MDP_PIPE_IMGI] = MT8183_MUTEX_MDP_START,
- [MDP_PIPE_RDMA0] = MT8183_MUTEX_MDP_START + 1,
- [MDP_PIPE_WPEI] = MT8183_MUTEX_MDP_START + 2,
- [MDP_PIPE_WPEI2] = MT8183_MUTEX_MDP_START + 3
+ [MDP_PIPE_IMGI] = MT8183_MDP_PIPE_IMGI,
+ [MDP_PIPE_RDMA0] = MT8183_MDP_PIPE_RDMA0,
+ [MDP_PIPE_WPEI] = MT8183_MDP_PIPE_WPEI,
+ [MDP_PIPE_WPEI2] = MT8183_MDP_PIPE_WPEI2,
};
static const struct mtk_mutex_data mt2701_mutex_driver_data = {
@@ -410,7 +416,7 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
EXPORT_SYMBOL_GPL(mtk_mutex_add_comp);
void mtk_mutex_add_mdp_mod(struct mtk_mutex *mutex, u32 mod,
- struct mmsys_cmdq_cmd *cmd)
+ u32 mod1, u32 sof, struct mmsys_cmdq_cmd *cmd)
{
struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
mutex[mutex->id]);
@@ -422,9 +428,13 @@ void mtk_mutex_add_mdp_mod(struct mtk_mutex *mutex, u32 mod,
cmdq_pkt_write_mask(cmd->pkt, mtx->subsys_id, mtx->addr + offset,
mod, mtx->data->mutex_mdp_mod_mask);
+ offset = DISP_REG_MUTEX_MOD1(mtx->data->mutex_mod_reg, mutex->id);
+ cmdq_pkt_write_mask(cmd->pkt, mtx->subsys_id, mtx->addr + offset,
+ mod1, mtx->data->mutex_mdp_mod_mask);
+
offset = DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id);
cmdq_pkt_write_mask(cmd->pkt, mtx->subsys_id, mtx->addr + offset,
- 0, mtx->data->mutex_mdp_sof_mask);
+ sof, mtx->data->mutex_mdp_sof_mask);
}
EXPORT_SYMBOL_GPL(mtk_mutex_add_mdp_mod);
diff --git a/include/linux/soc/mediatek/mtk-mutex.h b/include/linux/soc/mediatek/mtk-mutex.h
index d08b98419dd9..a2b81ce55b5d 100644
--- a/include/linux/soc/mediatek/mtk-mutex.h
+++ b/include/linux/soc/mediatek/mtk-mutex.h
@@ -17,7 +17,7 @@ int mtk_mutex_prepare(struct mtk_mutex *mutex);
void mtk_mutex_add_comp(struct mtk_mutex *mutex,
enum mtk_ddp_comp_id id);
void mtk_mutex_add_mdp_mod(struct mtk_mutex *mutex, u32 mod,
- struct mmsys_cmdq_cmd *cmd);
+ u32 mod1, u32 sof, struct mmsys_cmdq_cmd *cmd);
void mtk_mutex_enable(struct mtk_mutex *mutex);
void mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex,
struct mmsys_cmdq_cmd *cmd);
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v1 3/9] media: platform: mtk-mdp3: add chip independence architecture
2021-09-17 2:51 [PATCH v1 1/9] soc: mediatek: mmsys: expand MDP enum for chip independence architecture roy-cw.yeh
2021-09-17 2:51 ` [PATCH v1 2/9] soc: mediatek: mutex: expand parameter for mdp mutex function roy-cw.yeh
@ 2021-09-17 2:51 ` roy-cw.yeh
2021-09-17 2:51 ` [PATCH v1 4/9] dt-bindings: media: mediatek: mdp3: add additional function block yaml roy-cw.yeh
` (4 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: roy-cw.yeh @ 2021-09-17 2:51 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, Roy-CW . Yeh,
jason-jh . lin, daoyuan huang, Ping-Hsun Wu, Moudy Ho,
Enric Balletbo i Serra, Yongqiang Niu, devicetree, linux-kernel,
linux-media, linux-arm-kernel, linux-mediatek
From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
Add chip independence architecture
- Add hal architecture for mt8183
- Add driver data to adapt other soc
Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
.../media/platform/mtk-mdp3/mtk-mdp3-cmdq.c | 154 ++++---
.../media/platform/mtk-mdp3/mtk-mdp3-comp.c | 181 ++++-----
.../media/platform/mtk-mdp3/mtk-mdp3-comp.h | 193 ++++++++-
.../media/platform/mtk-mdp3/mtk-mdp3-core.c | 383 +++++++++++++++++-
.../media/platform/mtk-mdp3/mtk-mdp3-core.h | 19 +
.../media/platform/mtk-mdp3/mtk-mdp3-m2m.c | 2 +
.../media/platform/mtk-mdp3/mtk-mdp3-regs.c | 233 +----------
.../media/platform/mtk-mdp3/mtk-mdp3-regs.h | 262 ++++++------
8 files changed, 908 insertions(+), 519 deletions(-)
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
index 1636b60251ce..8972cb8de755 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
@@ -42,16 +42,43 @@ static bool is_output_disable(const struct img_compparam *param, u32 count)
true;
}
+static int mdp_get_mutex_idx(const struct mtk_mdp_driver_data *data, enum mtk_mdp_pipe_id pipe_id)
+{
+ int i = 0;
+
+ for (i = 0; i < data->pipe_info_len; i++) {
+ if (pipe_id == data->pipe_info[i].pipe_id)
+ return i;
+ }
+
+ return -ENODEV;
+}
+
+int mdp_get_event_idx(struct mdp_dev *mdp, enum mdp_comp_event event)
+{
+ int i = 0;
+
+ for (i = 0; i < mdp->mdp_data->event_len; i++) {
+ if (event == mdp->mdp_data->event[i])
+ return i;
+ }
+
+ return -ENODEV;
+}
+
static int mdp_path_subfrm_require(struct mdp_path_subfrm *subfrm,
const struct mdp_path *path,
struct mmsys_cmdq_cmd *cmd, u32 count)
{
const struct img_config *config = path->config;
const struct mdp_comp_ctx *ctx;
+ const struct mtk_mdp_driver_data *data = path->mdp_dev->mdp_data;
struct device *dev = &path->mdp_dev->pdev->dev;
struct mtk_mutex **mutex = path->mdp_dev->mdp_mutex;
s32 mutex_id = -1;
- int index;
+ u32 mutex_sof = 0;
+ int index, j;
+ enum mtk_mdp_comp_id mtk_comp_id = MDP_COMP_NONE;
/* Default value */
memset(subfrm, 0, sizeof(*subfrm));
@@ -60,62 +87,54 @@ static int mdp_path_subfrm_require(struct mdp_path_subfrm *subfrm,
ctx = &path->comps[index];
if (is_output_disable(ctx->param, count))
continue;
- switch (ctx->comp->id) {
- /**********************************************
- * Name MSB LSB
- * DISP_MUTEX_MOD 23 0
- *
- * Specifies which modules are in this mutex.
- * Every bit denotes a module. Bit definition:
- * 2 mdp_rdma0
- * 4 mdp_rsz0
- * 5 mdp_rsz1
- * 6 mdp_tdshp
- * 7 mdp_wrot0
- * 8 mdp_wdma
- * 13 mdp_color
- * 23 mdp_aal
- * 24 mdp_ccorr
- **********************************************/
+
+ mtk_comp_id = data->comp_data[ctx->comp->id].match.public_id;
+ switch (mtk_comp_id) {
case MDP_COMP_AAL0:
- subfrm->mutex_mod |= 1 << 23;
+ subfrm->mutex_mod |= data->comp_data[ctx->comp->id].mutex.mod;
break;
case MDP_COMP_CCORR0:
- subfrm->mutex_mod |= 1 << 24;
+ subfrm->mutex_mod |= data->comp_data[ctx->comp->id].mutex.mod;
break;
case MDP_COMP_WDMA:
- subfrm->mutex_mod |= 1 << 8;
+ subfrm->mutex_mod |= data->comp_data[ctx->comp->id].mutex.mod;
subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_WDMA;
break;
case MDP_COMP_WROT0:
- subfrm->mutex_mod |= 1 << 7;
+ subfrm->mutex_mod |= data->comp_data[ctx->comp->id].mutex.mod;
subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_WROT0;
break;
case MDP_COMP_TDSHP0:
- subfrm->mutex_mod |= 1 << 6;
+ subfrm->mutex_mod |= data->comp_data[ctx->comp->id].mutex.mod;
subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_TDSHP0;
break;
case MDP_COMP_RSZ1:
- subfrm->mutex_mod |= 1 << 5;
+ subfrm->mutex_mod |= data->comp_data[ctx->comp->id].mutex.mod;
subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_RSZ1;
break;
case MDP_COMP_RSZ0:
- subfrm->mutex_mod |= 1 << 4;
+ subfrm->mutex_mod |= data->comp_data[ctx->comp->id].mutex.mod;
subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_RSZ0;
break;
case MDP_COMP_RDMA0:
- mutex_id = MDP_PIPE_RDMA0;
- subfrm->mutex_mod |= 1 << 2;
+ j = mdp_get_mutex_idx(data, MDP_PIPE_RDMA0);
+ mutex_id = data->pipe_info[j].mutex_id;
+ subfrm->mutex_mod |= data->comp_data[ctx->comp->id].mutex.mod;
subfrm->sofs[subfrm->num_sofs++] = MDP_COMP_RDMA0;
break;
case MDP_COMP_ISP_IMGI:
- mutex_id = MDP_PIPE_IMGI;
+ j = mdp_get_mutex_idx(data, MDP_PIPE_IMGI);
+ mutex_id = data->pipe_info[j].mutex_id;
break;
case MDP_COMP_WPEI:
- mutex_id = MDP_PIPE_WPEI;
+ j = mdp_get_mutex_idx(data, MDP_PIPE_WPEI);
+ mutex_id = data->pipe_info[j].mutex_id;
+ subfrm->mutex_mod |= data->comp_data[ctx->comp->id].mutex.mod;
break;
case MDP_COMP_WPEI2:
- mutex_id = MDP_PIPE_WPEI2;
+ j = mdp_get_mutex_idx(data, MDP_PIPE_WPEI2);
+ mutex_id = data->pipe_info[j].mutex_id;
+ subfrm->mutex_mod |= data->comp_data[ctx->comp->id].mutex.mod;
break;
default:
break;
@@ -129,8 +148,10 @@ static int mdp_path_subfrm_require(struct mdp_path_subfrm *subfrm,
}
/* Set mutex modules */
- if (subfrm->mutex_mod)
- mtk_mutex_add_mdp_mod(mutex[mutex_id], subfrm->mutex_mod, cmd);
+ if (subfrm->mutex_mod) {
+ mtk_mutex_add_mdp_mod(mutex[mutex_id], subfrm->mutex_mod,
+ 0, mutex_sof, cmd);
+ }
return 0;
}
@@ -149,33 +170,36 @@ static int mdp_path_subfrm_run(const struct mdp_path_subfrm *subfrm,
}
if (subfrm->mutex_mod) {
- int index;
+ int index, evt;
/* Wait WROT SRAM shared to DISP RDMA */
/* Clear SOF event for each engine */
for (index = 0; index < subfrm->num_sofs; index++) {
switch (subfrm->sofs[index]) {
case MDP_COMP_RDMA0:
- MM_REG_CLEAR(cmd, RDMA0_SOF);
+ evt = mdp_get_event_idx(path->mdp_dev, RDMA0_SOF);
break;
case MDP_COMP_TDSHP0:
- MM_REG_CLEAR(cmd, TDSHP0_SOF);
+ evt = mdp_get_event_idx(path->mdp_dev, TDSHP0_SOF);
break;
case MDP_COMP_RSZ0:
- MM_REG_CLEAR(cmd, RSZ0_SOF);
+ evt = mdp_get_event_idx(path->mdp_dev, RSZ0_SOF);
break;
case MDP_COMP_RSZ1:
- MM_REG_CLEAR(cmd, RSZ1_SOF);
+ evt = mdp_get_event_idx(path->mdp_dev, RSZ1_SOF);
break;
case MDP_COMP_WDMA:
- MM_REG_CLEAR(cmd, WDMA0_SOF);
+ evt = mdp_get_event_idx(path->mdp_dev, WDMA0_SOF);
break;
case MDP_COMP_WROT0:
- MM_REG_CLEAR(cmd, WROT0_SOF);
+ evt = mdp_get_event_idx(path->mdp_dev, WROT0_SOF);
break;
default:
+ evt = -1;
break;
}
+ if (evt > 0)
+ MM_REG_CLEAR(cmd, evt);
}
/* Enable the mutex */
@@ -185,26 +209,29 @@ static int mdp_path_subfrm_run(const struct mdp_path_subfrm *subfrm,
for (index = 0; index < subfrm->num_sofs; index++) {
switch (subfrm->sofs[index]) {
case MDP_COMP_RDMA0:
- MM_REG_WAIT(cmd, RDMA0_SOF);
+ evt = mdp_get_event_idx(path->mdp_dev, RDMA0_SOF);
break;
case MDP_COMP_TDSHP0:
- MM_REG_WAIT(cmd, TDSHP0_SOF);
+ evt = mdp_get_event_idx(path->mdp_dev, TDSHP0_SOF);
break;
case MDP_COMP_RSZ0:
- MM_REG_WAIT(cmd, RSZ0_SOF);
+ evt = mdp_get_event_idx(path->mdp_dev, RSZ0_SOF);
break;
case MDP_COMP_RSZ1:
- MM_REG_WAIT(cmd, RSZ1_SOF);
+ evt = mdp_get_event_idx(path->mdp_dev, RSZ1_SOF);
break;
case MDP_COMP_WDMA:
- MM_REG_WAIT(cmd, WDMA0_SOF);
+ evt = mdp_get_event_idx(path->mdp_dev, WDMA0_SOF);
break;
case MDP_COMP_WROT0:
- MM_REG_WAIT(cmd, WROT0_SOF);
+ evt = mdp_get_event_idx(path->mdp_dev, WROT0_SOF);
break;
default:
+ evt = -1;
break;
}
+ if (evt > 0)
+ MM_REG_WAIT(cmd, evt);
}
}
return 0;
@@ -235,7 +262,9 @@ static int mdp_path_config_subfrm(struct mmsys_cmdq_cmd *cmd,
struct mdp_path_subfrm subfrm;
const struct img_config *config = path->config;
struct device *mmsys_dev = path->mdp_dev->mdp_mmsys;
+ const struct mtk_mdp_driver_data *data = path->mdp_dev->mdp_data;
struct mdp_comp_ctx *ctx;
+ enum mdp_comp_id cur, next;
int index, ret;
/* Acquire components */
@@ -243,10 +272,14 @@ static int mdp_path_config_subfrm(struct mmsys_cmdq_cmd *cmd,
if (ret)
return ret;
/* Enable mux settings */
- for (index = 0; index < (config->num_components - 1); index++)
+ for (index = 0; index < (config->num_components - 1); index++) {
+ cur = path->comps[index].comp->id;
+ next = path->comps[index + 1].comp->id;
mtk_mmsys_mdp_connect(mmsys_dev, cmd,
- path->comps[index].comp->id,
- path->comps[index + 1].comp->id);
+ data->comp_data[cur].match.public_id,
+ data->comp_data[next].match.public_id);
+ }
+
/* Config sub-frame information */
for (index = (config->num_components - 1); index >= 0; index--) {
ctx = &path->comps[index];
@@ -277,10 +310,14 @@ static int mdp_path_config_subfrm(struct mmsys_cmdq_cmd *cmd,
return ret;
}
/* Disable mux settings */
- for (index = 0; index < (config->num_components - 1); index++)
+ for (index = 0; index < (config->num_components - 1); index++) {
+ cur = path->comps[index].comp->id;
+ next = path->comps[index + 1].comp->id;
mtk_mmsys_mdp_disconnect(mmsys_dev, cmd,
- path->comps[index].comp->id,
- path->comps[index + 1].comp->id);
+ data->comp_data[cur].match.public_id,
+ data->comp_data[next].match.public_id);
+ }
+
return 0;
}
@@ -330,12 +367,14 @@ static void mdp_auto_release_work(struct work_struct *work)
{
struct mdp_cmdq_cb_param *cb_param;
struct mdp_dev *mdp;
+ int i;
cb_param = container_of(work, struct mdp_cmdq_cb_param,
auto_release_work);
mdp = cb_param->mdp;
- mtk_mutex_unprepare(mdp->mdp_mutex[MDP_PIPE_RDMA0]);
+ i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA0);
+ mtk_mutex_unprepare(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].mutex_id]);
mdp_comp_clocks_off(&mdp->pdev->dev, cb_param->comps,
cb_param->num_comps);
@@ -351,6 +390,7 @@ static void mdp_handle_cmdq_callback(struct cmdq_cb_data data)
struct mdp_cmdq_cb_param *cb_param;
struct mdp_dev *mdp;
struct device *dev;
+ int i;
if (!data.data) {
pr_info("%s:no callback data\n", __func__);
@@ -376,7 +416,8 @@ static void mdp_handle_cmdq_callback(struct cmdq_cb_data data)
INIT_WORK(&cb_param->auto_release_work, mdp_auto_release_work);
if (!queue_work(mdp->clock_wq, &cb_param->auto_release_work)) {
dev_err(dev, "%s:queue_work fail!\n", __func__);
- mtk_mutex_unprepare(mdp->mdp_mutex[MDP_PIPE_RDMA0]);
+ i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA0);
+ mtk_mutex_unprepare(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].mutex_id]);
mdp_comp_clocks_off(&mdp->pdev->dev, cb_param->comps,
cb_param->num_comps);
@@ -430,7 +471,9 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param)
goto err_destroy_pkt;
}
- mtk_mutex_prepare(mdp->mdp_mutex[MDP_PIPE_RDMA0]);
+ i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA0);
+ mtk_mutex_prepare(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].mutex_id]);
+
for (i = 0; i < param->config->num_components; i++)
mdp_comp_clock_on(&mdp->pdev->dev, path.comps[i].comp);
@@ -475,7 +518,8 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param)
return 0;
err_clock_off:
- mtk_mutex_unprepare(mdp->mdp_mutex[MDP_PIPE_RDMA0]);
+ i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA0);
+ mtk_mutex_unprepare(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].mutex_id]);
mdp_comp_clocks_off(&mdp->pdev->dev, cb_param->comps,
cb_param->num_comps);
err_destroy_pkt:
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c
index 27c70289cc90..f690502ee42b 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c
@@ -19,6 +19,38 @@
#include "mdp_reg_wdma.h"
#include "mdp_reg_isp.h"
+static struct mdp_comp_list comp_list;
+
+enum mdp_comp_id get_comp_camin(void)
+{
+ return comp_list.camin;
+}
+
+enum mdp_comp_id get_comp_camin2(void)
+{
+ return comp_list.camin2;
+}
+
+enum mdp_comp_id get_comp_rdma0(void)
+{
+ return comp_list.rdma0;
+}
+
+enum mdp_comp_id get_comp_rsz1(void)
+{
+ return comp_list.rsz1;
+}
+
+enum mdp_comp_id get_comp_merge2(void)
+{
+ return comp_list.merge2;
+}
+
+enum mdp_comp_id get_comp_merge3(void)
+{
+ return comp_list.merge3;
+}
+
static const struct mdp_platform_config *__get_plat_cfg(const struct mdp_comp_ctx *ctx)
{
if (!ctx)
@@ -32,8 +64,8 @@ static s64 get_comp_flag(const struct mdp_comp_ctx *ctx)
const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx);
if (mdp_cfg && mdp_cfg->rdma_rsz1_sram_sharing)
- if (ctx->comp->id == MDP_COMP_RDMA0)
- return (1 << MDP_COMP_RDMA0) | (1 << MDP_COMP_RSZ1);
+ if (ctx->comp->id == MDP_RDMA0)
+ return (1 << MDP_RDMA0) | (1 << MDP_RSZ1);
return 1 << ctx->comp->id;
}
@@ -45,10 +77,10 @@ static int init_rdma(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
u8 subsys_id = ctx->comp->subsys_id;
if (mdp_cfg && mdp_cfg->rdma_support_10bit) {
- struct mdp_comp *prz1 = ctx->comp->mdp_dev->comp[MDP_COMP_RSZ1];
+ struct mdp_comp *prz1 = ctx->comp->mdp_dev->comp[MDP_RSZ1];
/* Disable RSZ1 */
- if (ctx->comp->id == MDP_COMP_RDMA0 && prz1)
+ if (ctx->comp->id == MDP_RDMA0 && prz1)
MM_REG_WRITE(cmd, subsys_id, prz1->reg_base, PRZ_ENABLE,
0x00000000, 0x00000001);
}
@@ -197,12 +229,15 @@ static int wait_rdma_event(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
{
phys_addr_t base = ctx->comp->reg_base;
u8 subsys_id = ctx->comp->subsys_id;
+ int evt = -1;
if (ctx->comp->alias_id == 0)
- MM_REG_WAIT(cmd, RDMA0_DONE);
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, RDMA0_DONE);
else
pr_err("Do not support RDMA1_DONE event\n");
+ if (evt > 0)
+ MM_REG_WAIT(cmd, evt);
/* Disable RDMA */
MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_EN, 0x00000000,
0x00000001);
@@ -438,12 +473,16 @@ static int wait_wrot_event(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
const struct mdp_platform_config *mdp_cfg = __get_plat_cfg(ctx);
phys_addr_t base = ctx->comp->reg_base;
u8 subsys_id = ctx->comp->subsys_id;
+ int evt = -1;
if (ctx->comp->alias_id == 0)
- MM_REG_WAIT(cmd, WROT0_DONE);
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, WROT0_DONE);
else
pr_err("Do not support WROT1_DONE event\n");
+ if (evt > 0)
+ MM_REG_WAIT(cmd, evt);
+
if (mdp_cfg && mdp_cfg->wrot_filter_constraint)
MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, 0,
0x00000077);
@@ -549,8 +588,11 @@ static int wait_wdma_event(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
{
phys_addr_t base = ctx->comp->reg_base;
u8 subsys_id = ctx->comp->subsys_id;
+ int evt;
- MM_REG_WAIT(cmd, WDMA0_DONE);
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, WDMA0_DONE);
+ if (evt > 0)
+ MM_REG_WAIT(cmd, evt);
/* Disable WDMA */
MM_REG_WRITE(cmd, subsys_id, base, WDMA_EN, 0x00, 0x00000001);
return 0;
@@ -619,13 +661,13 @@ static int init_isp(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
const struct isp_data *isp = &ctx->param->isp;
/* Direct link */
- if (isp->dl_flags & (1 << MDP_COMP_CAMIN)) {
- dev_info(dev, "SW_RST ASYNC");
+ if (isp->dl_flags & (1 << MDP_CAMIN)) {
+ dev_err(dev, "SW_RST ASYNC");
mtk_mmsys_mdp_isp_ctrl(dev, cmd, MDP_COMP_CAMIN);
}
- if (isp->dl_flags & (1 << MDP_COMP_CAMIN2)) {
- dev_info(dev, "SW_RST ASYNC2");
+ if (isp->dl_flags & (1 << MDP_CAMIN2)) {
+ dev_err(dev, "SW_RST ASYNC2");
mtk_mmsys_mdp_isp_ctrl(dev, cmd, MDP_COMP_CAMIN2);
}
@@ -736,13 +778,14 @@ static int wait_isp_event(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
struct device *dev = &ctx->comp->mdp_dev->pdev->dev;
phys_addr_t base = ctx->comp->reg_base;
u8 subsys_id = ctx->comp->subsys_id;
+ int evt;
/* MDP_DL_SEL: select MDP_CROP */
- if (isp->dl_flags & (1 << MDP_COMP_CAMIN))
+ if (isp->dl_flags & (1 << MDP_CAMIN))
MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x0030, 0x00000000,
0x00000200);
/* MDP2_DL_SEL: select MDP_CROP2 */
- if (isp->dl_flags & (1 << MDP_COMP_CAMIN2))
+ if (isp->dl_flags & (1 << MDP_CAMIN2))
MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x0030, 0x00000000,
0x00000C00);
@@ -750,68 +793,70 @@ static int wait_isp_event(struct mdp_comp_ctx *ctx, struct mmsys_cmdq_cmd *cmd)
case ISP_DRV_DIP_CQ_THRE0:
MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, 0x0001,
0x00000001);
- MM_REG_WAIT(cmd, ISP_P2_0_DONE);
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_0_DONE);
break;
case ISP_DRV_DIP_CQ_THRE1:
MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, 0x0002,
0x00000002);
- MM_REG_WAIT(cmd, ISP_P2_1_DONE);
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_1_DONE);
break;
case ISP_DRV_DIP_CQ_THRE2:
MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, 0x0004,
0x00000004);
- MM_REG_WAIT(cmd, ISP_P2_2_DONE);
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_2_DONE);
break;
case ISP_DRV_DIP_CQ_THRE3:
MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, 0x0008,
0x00000008);
- MM_REG_WAIT(cmd, ISP_P2_3_DONE);
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_3_DONE);
break;
case ISP_DRV_DIP_CQ_THRE4:
MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, 0x0010,
0x00000010);
- MM_REG_WAIT(cmd, ISP_P2_4_DONE);
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_4_DONE);
break;
case ISP_DRV_DIP_CQ_THRE5:
MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, 0x0020,
0x00000020);
- MM_REG_WAIT(cmd, ISP_P2_5_DONE);
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_5_DONE);
break;
case ISP_DRV_DIP_CQ_THRE6:
MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, 0x0040,
0x00000040);
- MM_REG_WAIT(cmd, ISP_P2_6_DONE);
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_6_DONE);
break;
case ISP_DRV_DIP_CQ_THRE7:
MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, 0x0080,
0x00000080);
- MM_REG_WAIT(cmd, ISP_P2_7_DONE);
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_7_DONE);
break;
case ISP_DRV_DIP_CQ_THRE8:
MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, 0x0100,
0x00000100);
- MM_REG_WAIT(cmd, ISP_P2_8_DONE);
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_8_DONE);
break;
case ISP_DRV_DIP_CQ_THRE9:
MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, 0x0200,
0x00000200);
- MM_REG_WAIT(cmd, ISP_P2_9_DONE);
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_9_DONE);
break;
case ISP_DRV_DIP_CQ_THRE10:
MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, 0x0400,
0x00000400);
- MM_REG_WAIT(cmd, ISP_P2_10_DONE);
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_10_DONE);
break;
case ISP_DRV_DIP_CQ_THRE11:
MM_REG_WRITE_MASK(cmd, subsys_id, base, 0x2000, 0x0800,
0x00000800);
- MM_REG_WAIT(cmd, ISP_P2_11_DONE);
+ evt = mdp_get_event_idx(ctx->comp->mdp_dev, ISP_P2_11_DONE);
break;
default:
dev_err(dev, "Do not support this cq (%d)", isp->cq_idx);
return -EINVAL;
}
+ MM_REG_WAIT(cmd, evt);
+
return 0;
}
@@ -874,32 +919,6 @@ static const struct mdp_comp_ops *mdp_comp_ops[MDP_COMP_TYPE_COUNT] = {
[MDP_COMP_TYPE_DL_PATH2] = &camin_ops,
};
-struct mdp_comp_match {
- enum mdp_comp_type type;
- u32 alias_id;
-};
-
-static const struct mdp_comp_match mdp_comp_matches[MDP_MAX_COMP_COUNT] = {
- [MDP_COMP_WPEI] = { MDP_COMP_TYPE_WPEI, 0 },
- [MDP_COMP_WPEO] = { MDP_COMP_TYPE_EXTO, 2 },
- [MDP_COMP_WPEI2] = { MDP_COMP_TYPE_WPEI, 1 },
- [MDP_COMP_WPEO2] = { MDP_COMP_TYPE_EXTO, 3 },
- [MDP_COMP_ISP_IMGI] = { MDP_COMP_TYPE_IMGI, 0 },
- [MDP_COMP_ISP_IMGO] = { MDP_COMP_TYPE_EXTO, 0 },
- [MDP_COMP_ISP_IMG2O] = { MDP_COMP_TYPE_EXTO, 1 },
-
- [MDP_COMP_CAMIN] = { MDP_COMP_TYPE_DL_PATH1, 0 },
- [MDP_COMP_CAMIN2] = { MDP_COMP_TYPE_DL_PATH2, 1 },
- [MDP_COMP_RDMA0] = { MDP_COMP_TYPE_RDMA, 0 },
- [MDP_COMP_CCORR0] = { MDP_COMP_TYPE_CCORR, 0 },
- [MDP_COMP_RSZ0] = { MDP_COMP_TYPE_RSZ, 0 },
- [MDP_COMP_RSZ1] = { MDP_COMP_TYPE_RSZ, 1 },
- [MDP_COMP_PATH0_SOUT] = { MDP_COMP_TYPE_PATH1, 0 },
- [MDP_COMP_PATH1_SOUT] = { MDP_COMP_TYPE_PATH2, 1 },
- [MDP_COMP_WROT0] = { MDP_COMP_TYPE_WROT, 0 },
- [MDP_COMP_WDMA] = { MDP_COMP_TYPE_WDMA, 0 },
-};
-
static const struct of_device_id mdp_comp_dt_ids[] = {
{
.compatible = "mediatek,mt8183-mdp3-rdma",
@@ -943,34 +962,13 @@ static const struct of_device_id mdp_sub_comp_dt_ids[] = {
{}
};
-/* Used to describe the item order in MDP property */
-struct mdp_comp_info {
- u32 clk_num;
- u32 clk_ofst;
- u32 dts_reg_ofst;
-};
-
-static const struct mdp_comp_info mdp_comp_dt_info[MDP_COMP_TYPE_COUNT] = {
- [MDP_COMP_TYPE_RDMA] = {2, 0, 0},
- [MDP_COMP_TYPE_RSZ] = {1, 0, 0},
- [MDP_COMP_TYPE_WROT] = {1, 0, 0},
- [MDP_COMP_TYPE_WDMA] = {1, 0, 0},
- [MDP_COMP_TYPE_PATH1] = {0, 0, 2},
- [MDP_COMP_TYPE_PATH2] = {0, 0, 3},
- [MDP_COMP_TYPE_CCORR] = {1, 0, 0},
- [MDP_COMP_TYPE_IMGI] = {0, 0, 4},
- [MDP_COMP_TYPE_EXTO] = {0, 0, 4},
- [MDP_COMP_TYPE_DL_PATH1] = {2, 2, 1},
- [MDP_COMP_TYPE_DL_PATH2] = {2, 4, 1},
-};
-
-static int mdp_comp_get_id(enum mdp_comp_type type, u32 alias_id)
+static int mdp_comp_get_id(struct mdp_dev *mdp, enum mdp_comp_type type, u32 alias_id)
{
int i;
- for (i = 0; i < ARRAY_SIZE(mdp_comp_matches); i++)
- if (mdp_comp_matches[i].type == type &&
- mdp_comp_matches[i].alias_id == alias_id)
+ for (i = 0; i < mdp->mdp_data->comp_data_len; i++)
+ if (mdp->mdp_data->comp_data[i].match.type == type &&
+ mdp->mdp_data->comp_data[i].match.alias_id == alias_id)
return i;
return -ENODEV;
}
@@ -1028,7 +1026,7 @@ void mdp_comp_clocks_off(struct device *dev, struct mdp_comp *comps, int num)
mdp_comp_clock_off(dev, &comps[i]);
}
-static int mdp_get_subsys_id(struct device *dev, struct device_node *node,
+static int mdp_get_subsys_id(struct mdp_dev *mdp, struct device *dev, struct device_node *node,
struct mdp_comp *comp)
{
struct platform_device *comp_pdev;
@@ -1047,7 +1045,7 @@ static int mdp_get_subsys_id(struct device *dev, struct device_node *node,
return -ENODEV;
}
- index = mdp_comp_dt_info[comp->type].dts_reg_ofst;
+ index = mdp->mdp_data->comp_info[comp->type].dts_reg_ofst;
ret = cmdq_dev_get_client_reg(&comp_pdev->dev, &cmdq_reg, index);
if (ret != 0) {
dev_err(&comp_pdev->dev, "cmdq_dev_get_subsys fail!\n");
@@ -1065,7 +1063,7 @@ static void __mdp_comp_init(struct mdp_dev *mdp, struct device_node *node,
{
struct resource res;
phys_addr_t base;
- int index = mdp_comp_dt_info[comp->type].dts_reg_ofst;
+ int index = mdp->mdp_data->comp_info[comp->type].dts_reg_ofst;
if (of_address_to_resource(node, index, &res) < 0)
base = 0L;
@@ -1078,7 +1076,7 @@ static void __mdp_comp_init(struct mdp_dev *mdp, struct device_node *node,
}
static int mdp_comp_init(struct mdp_dev *mdp, struct device_node *node,
- struct mdp_comp *comp, enum mtk_mdp_comp_id id)
+ struct mdp_comp *comp, enum mdp_comp_id id)
{
struct device *dev = &mdp->pdev->dev;
int clk_num;
@@ -1090,14 +1088,14 @@ static int mdp_comp_init(struct mdp_dev *mdp, struct device_node *node,
return -EINVAL;
}
- comp->type = mdp_comp_matches[id].type;
+ comp->type = mdp->mdp_data->comp_data[id].match.type;
comp->id = id;
- comp->alias_id = mdp_comp_matches[id].alias_id;
+ comp->alias_id = mdp->mdp_data->comp_data[id].match.alias_id;
comp->ops = mdp_comp_ops[comp->type];
__mdp_comp_init(mdp, node, comp);
- clk_num = mdp_comp_dt_info[comp->type].clk_num;
- clk_ofst = mdp_comp_dt_info[comp->type].clk_ofst;
+ clk_num = mdp->mdp_data->comp_info[comp->type].clk_num;
+ clk_ofst = mdp->mdp_data->comp_info[comp->type].clk_ofst;
for (i = 0; i < clk_num; i++) {
comp->clks[i] = of_clk_get(node, i + clk_ofst);
@@ -1105,14 +1103,14 @@ static int mdp_comp_init(struct mdp_dev *mdp, struct device_node *node,
break;
}
- mdp_get_subsys_id(dev, node, comp);
+ mdp_get_subsys_id(mdp, dev, node, comp);
return 0;
}
static struct mdp_comp *mdp_comp_create(struct mdp_dev *mdp,
struct device_node *node,
- enum mtk_mdp_comp_id id)
+ enum mdp_comp_id id)
{
struct device *dev = &mdp->pdev->dev;
struct mdp_comp *comp;
@@ -1148,7 +1146,7 @@ static int mdp_sub_comps_create(struct mdp_dev *mdp, struct device_node *node)
of_property_for_each_string(node, "mdp3-comps", prop, name) {
const struct of_device_id *matches = mdp_sub_comp_dt_ids;
- enum mdp_comp_type type = MDP_COMP_NONE;
+ enum mdp_comp_type type = MDP_COMP_INVALID;
u32 alias_id;
int id, ret;
struct mdp_comp *comp;
@@ -1168,7 +1166,7 @@ static int mdp_sub_comps_create(struct mdp_dev *mdp, struct device_node *node)
return ret;
}
- id = mdp_comp_get_id(type, alias_id);
+ id = mdp_comp_get_id(mdp, type, alias_id);
if (id < 0) {
dev_err(dev, "Failed to get comp id: %s (%d, %d)\n",
name, type, alias_id);
@@ -1197,8 +1195,8 @@ void mdp_component_deinit(struct mdp_dev *mdp)
{
int i;
- for (i = 0; i < MDP_PIPE_MAX; i++)
- mtk_mutex_put(mdp->mdp_mutex[i]);
+ for (i = 0; i < mdp->mdp_data->pipe_info_len; i++)
+ mtk_mutex_put(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].pipe_id]);
for (i = 0; i < ARRAY_SIZE(mdp->comp); i++) {
if (mdp->comp[i]) {
@@ -1216,6 +1214,7 @@ int mdp_component_init(struct mdp_dev *mdp)
u32 alias_id;
int i, ret;
+ memcpy(&comp_list, mdp->mdp_data->comp_list, sizeof(struct mdp_comp_list));
parent = dev->of_node->parent;
/* Iterate over sibling MDP function blocks */
for_each_child_of_node(parent, node) {
@@ -1241,7 +1240,7 @@ int mdp_component_init(struct mdp_dev *mdp)
node);
continue;
}
- id = mdp_comp_get_id(type, alias_id);
+ id = mdp_comp_get_id(mdp, type, alias_id);
if (id < 0) {
dev_err(dev,
"Fail to get component id: type %d alias %d\n",
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h
index 7b34f9c42410..02957abd12d0 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h
@@ -38,31 +38,94 @@
(((mask) & (ofst##_MASK)) == (ofst##_MASK)) ? \
(0xffffffff) : (mask), ##__VA_ARGS__)
+#define MDP_CAMIN get_comp_camin()
+#define MDP_CAMIN2 get_comp_camin2()
+#define MDP_RDMA0 get_comp_rdma0()
+#define MDP_RSZ1 get_comp_rsz1()
+#define MDP_MERGE2 get_comp_merge2()
+#define MDP_MERGE3 get_comp_merge3()
+
enum mdp_comp_type {
MDP_COMP_TYPE_INVALID = 0,
+ MDP_COMP_TYPE_IMGI,
+ MDP_COMP_TYPE_WPEI,
+
MDP_COMP_TYPE_RDMA,
MDP_COMP_TYPE_RSZ,
MDP_COMP_TYPE_WROT,
MDP_COMP_TYPE_WDMA,
MDP_COMP_TYPE_PATH1,
MDP_COMP_TYPE_PATH2,
+ MDP_COMP_TYPE_SPLIT,
+ MDP_COMP_TYPE_STITCH,
+ MDP_COMP_TYPE_FG,
+ MDP_COMP_TYPE_OVL,
+ MDP_COMP_TYPE_PAD,
+ MDP_COMP_TYPE_MERGE,
MDP_COMP_TYPE_TDSHP,
MDP_COMP_TYPE_COLOR,
MDP_COMP_TYPE_DRE,
MDP_COMP_TYPE_CCORR,
MDP_COMP_TYPE_HDR,
+ MDP_COMP_TYPE_AAL,
+ MDP_COMP_TYPE_TCC,
- MDP_COMP_TYPE_IMGI,
- MDP_COMP_TYPE_WPEI,
MDP_COMP_TYPE_EXTO, /* External path */
MDP_COMP_TYPE_DL_PATH1, /* Direct-link path1 */
MDP_COMP_TYPE_DL_PATH2, /* Direct-link path2 */
+ MDP_COMP_TYPE_DL_PATH3, /* Direct-link path3 */
+ MDP_COMP_TYPE_DL_PATH4, /* Direct-link path4 */
+ MDP_COMP_TYPE_DL_PATH5, /* Direct-link path5 */
+ MDP_COMP_TYPE_DL_PATH6, /* Direct-link path6 */
+ MDP_COMP_TYPE_DUMMY,
MDP_COMP_TYPE_COUNT /* ALWAYS keep at the end */
};
+enum mdp_comp_id {
+ MDP_COMP_INVALID = -1, /* Invalid engine */
+
+ /* MT8183 Comp id */
+ /* ISP */
+ MT8183_MDP_COMP_WPEI = 0,
+ MT8183_MDP_COMP_WPEO, /* 1 */
+ MT8183_MDP_COMP_WPEI2, /* 2 */
+ MT8183_MDP_COMP_WPEO2, /* 3 */
+ MT8183_MDP_COMP_ISP_IMGI, /* 4 */
+ MT8183_MDP_COMP_ISP_IMGO, /* 5 */
+ MT8183_MDP_COMP_ISP_IMG2O, /* 6 */
+
+ /* IPU */
+ MT8183_MDP_COMP_IPUI, /* 7 */
+ MT8183_MDP_COMP_IPUO, /* 8 */
+
+ /* MDP */
+ MT8183_MDP_COMP_CAMIN, /* 9 */
+ MT8183_MDP_COMP_CAMIN2, /* 10 */
+ MT8183_MDP_COMP_RDMA0, /* 11 */
+ MT8183_MDP_COMP_AAL0, /* 12 */
+ MT8183_MDP_COMP_CCORR0, /* 13 */
+ MT8183_MDP_COMP_RSZ0, /* 14 */
+ MT8183_MDP_COMP_RSZ1, /* 15 */
+ MT8183_MDP_COMP_TDSHP0, /* 16 */
+ MT8183_MDP_COMP_COLOR0, /* 17 */
+ MT8183_MDP_COMP_PATH0_SOUT, /* 18 */
+ MT8183_MDP_COMP_PATH1_SOUT, /* 19 */
+ MT8183_MDP_COMP_WROT0, /* 20 */
+ MT8183_MDP_COMP_WDMA, /* 21 */
+
+ /* Dummy Engine */
+ MT8183_MDP_COMP_RDMA1, /* 22 */
+ MT8183_MDP_COMP_RSZ2, /* 23 */
+ MT8183_MDP_COMP_TDSHP1, /* 24 */
+ MT8183_MDP_COMP_WROT1, /* 25 */
+ MT8183_MDP_MAX_COMP_COUNT,
+
+ MDP_MAX_COMP /* ALWAYS keep at the end */
+};
+
enum mdp_comp_event {
RDMA0_SOF,
RDMA0_DONE,
@@ -73,6 +136,18 @@ enum mdp_comp_event {
WROT0_DONE,
WDMA0_SOF,
WDMA0_DONE,
+ RDMA1_SOF,
+ RDMA2_SOF,
+ RDMA3_SOF,
+ WROT1_SOF,
+ WROT2_SOF,
+ WROT3_SOF,
+ RDMA1_FRAME_DONE,
+ RDMA2_FRAME_DONE,
+ RDMA3_FRAME_DONE,
+ WROT1_FRAME_DONE,
+ WROT2_FRAME_DONE,
+ WROT3_FRAME_DONE,
ISP_P2_0_DONE,
ISP_P2_1_DONE,
@@ -96,6 +171,104 @@ enum mdp_comp_event {
MDP_MAX_EVENT_COUNT /* ALWAYS keep at the end */
};
+enum mdp_mmsys_config_id {
+ CONFIG_VPP0_HW_DCM_1ST_DIS0,
+ CONFIG_VPP0_DL_IRELAY_WR,
+ CONFIG_VPP1_HW_DCM_1ST_DIS0,
+ CONFIG_VPP1_HW_DCM_1ST_DIS1,
+ CONFIG_VPP1_HW_DCM_2ND_DIS0,
+ CONFIG_VPP1_HW_DCM_2ND_DIS1,
+ CONFIG_SVPP2_BUF_BF_RSZ_SWITCH,
+ CONFIG_SVPP3_BUF_BF_RSZ_SWITCH,
+ MDP_MAX_CONFIG_COUNT
+};
+
+struct mdp_comp_list {
+ enum mdp_comp_id wpei;
+ enum mdp_comp_id wpeo;
+ enum mdp_comp_id wpei2;
+ enum mdp_comp_id wpeo2;
+ enum mdp_comp_id camin;
+ enum mdp_comp_id camin2;
+ enum mdp_comp_id split;
+ enum mdp_comp_id split2;
+ enum mdp_comp_id rdma0;
+ enum mdp_comp_id rdma1;
+ enum mdp_comp_id rdma2;
+ enum mdp_comp_id rdma3;
+ enum mdp_comp_id stitch;
+ enum mdp_comp_id fg0;
+ enum mdp_comp_id fg1;
+ enum mdp_comp_id fg2;
+ enum mdp_comp_id fg3;
+ enum mdp_comp_id hdr0;
+ enum mdp_comp_id hdr1;
+ enum mdp_comp_id hdr2;
+ enum mdp_comp_id hdr3;
+ enum mdp_comp_id aal0;
+ enum mdp_comp_id aal1;
+ enum mdp_comp_id aal2;
+ enum mdp_comp_id aal3;
+ enum mdp_comp_id rsz0;
+ enum mdp_comp_id rsz1;
+ enum mdp_comp_id rsz2;
+ enum mdp_comp_id rsz3;
+ enum mdp_comp_id tdshp0;
+ enum mdp_comp_id tdshp1;
+ enum mdp_comp_id tdshp2;
+ enum mdp_comp_id tdshp3;
+ enum mdp_comp_id color0;
+ enum mdp_comp_id color1;
+ enum mdp_comp_id color2;
+ enum mdp_comp_id color3;
+ enum mdp_comp_id ccorr0;
+ enum mdp_comp_id ovl0;
+ enum mdp_comp_id ovl1;
+ enum mdp_comp_id pad0;
+ enum mdp_comp_id pad1;
+ enum mdp_comp_id pad2;
+ enum mdp_comp_id pad3;
+ enum mdp_comp_id tcc0;
+ enum mdp_comp_id tcc1;
+ enum mdp_comp_id wrot0;
+ enum mdp_comp_id wrot1;
+ enum mdp_comp_id wrot2;
+ enum mdp_comp_id wrot3;
+ enum mdp_comp_id merge2;
+ enum mdp_comp_id merge3;
+ enum mdp_comp_id wdma;
+ enum mdp_comp_id vdo0dl0;
+ enum mdp_comp_id vdo1dl0;
+ enum mdp_comp_id vdo0dl1;
+ enum mdp_comp_id vdo1dl1;
+ enum mdp_comp_id path0_sout;
+ enum mdp_comp_id path1_sout;
+};
+
+struct mdp_comp_match {
+ enum mdp_comp_type type;
+ u32 alias_id;
+ enum mtk_mdp_comp_id public_id;
+};
+
+struct mdp_mutex_info {
+ u32 mmsys_id;
+ u32 mod;
+ u32 mod2;
+};
+
+struct mdp_comp_data {
+ struct mdp_comp_match match;
+ struct mdp_mutex_info mutex;
+};
+
+/* Used to describe the item order in MDP property */
+struct mdp_comp_info {
+ u32 clk_num;
+ u32 clk_ofst;
+ u32 dts_reg_ofst;
+};
+
struct mdp_comp_ops;
struct mdp_comp {
@@ -106,7 +279,7 @@ struct mdp_comp {
struct clk *clks[6];
struct device *comp_dev;
enum mdp_comp_type type;
- enum mtk_mdp_comp_id id;
+ enum mdp_comp_id id;
u32 alias_id;
const struct mdp_comp_ops *ops;
};
@@ -134,6 +307,18 @@ struct mdp_comp_ops {
struct mdp_dev;
+enum mdp_comp_id get_comp_camin(void);
+enum mdp_comp_id get_comp_camin2(void);
+enum mdp_comp_id get_comp_rdma0(void);
+enum mdp_comp_id get_comp_aal0(void);
+enum mdp_comp_id get_comp_ccorr0(void);
+enum mdp_comp_id get_comp_rsz0(void);
+enum mdp_comp_id get_comp_rsz1(void);
+enum mdp_comp_id get_comp_tdshp0(void);
+enum mdp_comp_id get_comp_color0(void);
+enum mdp_comp_id get_comp_wrot0(void);
+enum mdp_comp_id get_comp_wdma(void);
+
int mdp_component_init(struct mdp_dev *mdp);
void mdp_component_deinit(struct mdp_dev *mdp);
void mdp_comp_clock_on(struct device *dev, struct mdp_comp *comp);
@@ -144,4 +329,6 @@ int mdp_comp_ctx_init(struct mdp_dev *mdp, struct mdp_comp_ctx *ctx,
const struct img_compparam *param,
const struct img_ipi_frameparam *frame);
+int mdp_get_event_idx(struct mdp_dev *mdp, enum mdp_comp_event event);
+
#endif /* __MTK_MDP3_COMP_H__ */
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c
index 8459b0afa84c..4f7d8bc1bf24 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c
@@ -26,8 +26,375 @@ static const struct mdp_platform_config mt8183_plat_cfg = {
.gce_event_offset = 0,
};
+static const struct mdp_comp_list mt8183_comp_list = {
+ .wpei = MT8183_MDP_COMP_WPEI,
+ .wpeo = MT8183_MDP_COMP_WPEO,
+ .wpei2 = MT8183_MDP_COMP_WPEI2,
+ .wpeo2 = MT8183_MDP_COMP_WPEO2,
+ .camin = MT8183_MDP_COMP_CAMIN,
+ .camin2 = MT8183_MDP_COMP_CAMIN2,
+ .split = MDP_COMP_INVALID,
+ .split2 = MDP_COMP_INVALID,
+ .rdma0 = MT8183_MDP_COMP_RDMA0,
+ .rdma1 = MDP_COMP_INVALID,
+ .rdma2 = MDP_COMP_INVALID,
+ .rdma3 = MDP_COMP_INVALID,
+ .stitch = MDP_COMP_INVALID,
+ .fg0 = MDP_COMP_INVALID,
+ .fg1 = MDP_COMP_INVALID,
+ .fg2 = MDP_COMP_INVALID,
+ .fg3 = MDP_COMP_INVALID,
+ .hdr0 = MDP_COMP_INVALID,
+ .hdr1 = MDP_COMP_INVALID,
+ .hdr2 = MDP_COMP_INVALID,
+ .hdr3 = MDP_COMP_INVALID,
+ .aal0 = MT8183_MDP_COMP_AAL0,
+ .aal1 = MDP_COMP_INVALID,
+ .aal2 = MDP_COMP_INVALID,
+ .aal3 = MDP_COMP_INVALID,
+ .rsz0 = MT8183_MDP_COMP_RSZ0,
+ .rsz1 = MT8183_MDP_COMP_RSZ1,
+ .rsz2 = MDP_COMP_INVALID,
+ .rsz3 = MDP_COMP_INVALID,
+ .tdshp0 = MT8183_MDP_COMP_TDSHP0,
+ .tdshp1 = MDP_COMP_INVALID,
+ .tdshp2 = MDP_COMP_INVALID,
+ .tdshp3 = MDP_COMP_INVALID,
+ .color0 = MT8183_MDP_COMP_COLOR0,
+ .color1 = MDP_COMP_INVALID,
+ .color2 = MDP_COMP_INVALID,
+ .color3 = MDP_COMP_INVALID,
+ .ccorr0 = MT8183_MDP_COMP_CCORR0,
+ .ovl0 = MDP_COMP_INVALID,
+ .ovl1 = MDP_COMP_INVALID,
+ .pad0 = MDP_COMP_INVALID,
+ .pad1 = MDP_COMP_INVALID,
+ .pad2 = MDP_COMP_INVALID,
+ .pad3 = MDP_COMP_INVALID,
+ .tcc0 = MDP_COMP_INVALID,
+ .tcc1 = MDP_COMP_INVALID,
+ .wrot0 = MT8183_MDP_COMP_WROT0,
+ .wrot1 = MDP_COMP_INVALID,
+ .wrot2 = MDP_COMP_INVALID,
+ .wrot3 = MDP_COMP_INVALID,
+ .merge2 = MDP_COMP_INVALID,
+ .merge3 = MDP_COMP_INVALID,
+ .wdma = MT8183_MDP_COMP_WDMA,
+ .vdo0dl0 = MDP_COMP_INVALID,
+ .vdo1dl0 = MDP_COMP_INVALID,
+ .vdo0dl1 = MDP_COMP_INVALID,
+ .vdo1dl1 = MDP_COMP_INVALID,
+ .path0_sout = MT8183_MDP_COMP_PATH0_SOUT,
+ .path1_sout = MT8183_MDP_COMP_PATH1_SOUT,
+};
+
+static const struct mdp_comp_data mt8183_mdp_comp_data[MT8183_MDP_MAX_COMP_COUNT] = {
+ [MT8183_MDP_COMP_WPEI] = { {MDP_COMP_TYPE_WPEI, 0, MDP_COMP_WPEI}, {0, 0, 0} },
+ [MT8183_MDP_COMP_WPEO] = { {MDP_COMP_TYPE_EXTO, 2, MDP_COMP_WPEO}, {0, 0, 0} },
+ [MT8183_MDP_COMP_WPEI2] = { {MDP_COMP_TYPE_WPEI, 1, MDP_COMP_WPEI2}, {0, 0, 0} },
+ [MT8183_MDP_COMP_WPEO2] = { {MDP_COMP_TYPE_EXTO, 3, MDP_COMP_WPEO2}, {0, 0, 0} },
+ [MT8183_MDP_COMP_ISP_IMGI] = { {MDP_COMP_TYPE_IMGI, 0, MDP_COMP_ISP_IMGI}, {0, 0, 0} },
+ [MT8183_MDP_COMP_ISP_IMGO] = { {MDP_COMP_TYPE_EXTO, 0, MDP_COMP_ISP_IMGO}, {0, 0, 0} },
+ [MT8183_MDP_COMP_ISP_IMG2O] = { {MDP_COMP_TYPE_EXTO, 1, MDP_COMP_ISP_IMG2O}, {0, 0, 0} },
+
+ [MT8183_MDP_COMP_CAMIN] = { {MDP_COMP_TYPE_DL_PATH1, 0, MDP_COMP_CAMIN}, {0, 0, 0} },
+ [MT8183_MDP_COMP_CAMIN2] = { {MDP_COMP_TYPE_DL_PATH2, 1, MDP_COMP_CAMIN2}, {0, 0, 0} },
+ [MT8183_MDP_COMP_RDMA0] = { {MDP_COMP_TYPE_RDMA, 0, MDP_COMP_RDMA0}, {0, BIT(2), 0} },
+ [MT8183_MDP_COMP_AAL0] = { {MDP_COMP_TYPE_AAL, 0, MDP_COMP_AAL0}, {0, BIT(23), 0} },
+ [MT8183_MDP_COMP_CCORR0] = { {MDP_COMP_TYPE_CCORR, 0, MDP_COMP_CCORR0}, {0, BIT(24), 0} },
+ [MT8183_MDP_COMP_RSZ0] = { {MDP_COMP_TYPE_RSZ, 0, MDP_COMP_RSZ0}, {0, BIT(4), 0} },
+ [MT8183_MDP_COMP_RSZ1] = { {MDP_COMP_TYPE_RSZ, 1, MDP_COMP_RSZ1}, {0, BIT(5), 0} },
+ [MT8183_MDP_COMP_TDSHP0] = { {MDP_COMP_TYPE_TDSHP, 0, MDP_COMP_TDSHP0}, {0, BIT(6), 0} },
+ [MT8183_MDP_COMP_PATH0_SOUT] = { {MDP_COMP_TYPE_PATH1, 0, MDP_COMP_PATH0_SOUT}, {0, 0, 0} },
+ [MT8183_MDP_COMP_PATH1_SOUT] = { {MDP_COMP_TYPE_PATH2, 1, MDP_COMP_PATH1_SOUT}, {0, 0, 0} },
+ [MT8183_MDP_COMP_WROT0] = { {MDP_COMP_TYPE_WROT, 0, MDP_COMP_WROT0}, {0, BIT(7), 0} },
+ [MT8183_MDP_COMP_WDMA] = { {MDP_COMP_TYPE_WDMA, 0, MDP_COMP_WDMA}, {0, BIT(8), 0} },
+};
+
+static const enum mdp_comp_event mt8183_mdp_event[] = {
+ RDMA0_SOF,
+ RDMA0_DONE,
+ RSZ0_SOF,
+ RSZ1_SOF,
+ TDSHP0_SOF,
+ WROT0_SOF,
+ WROT0_DONE,
+ WDMA0_SOF,
+ WDMA0_DONE,
+ ISP_P2_0_DONE,
+ ISP_P2_1_DONE,
+ ISP_P2_2_DONE,
+ ISP_P2_3_DONE,
+ ISP_P2_4_DONE,
+ ISP_P2_5_DONE,
+ ISP_P2_6_DONE,
+ ISP_P2_7_DONE,
+ ISP_P2_8_DONE,
+ ISP_P2_9_DONE,
+ ISP_P2_10_DONE,
+ ISP_P2_11_DONE,
+ ISP_P2_12_DONE,
+ ISP_P2_13_DONE,
+ ISP_P2_14_DONE,
+ WPE_DONE,
+ WPE_B_DONE
+};
+
+static const struct mdp_comp_info mt8183_comp_dt_info[] = {
+ [MDP_COMP_TYPE_RDMA] = {2, 0, 0},
+ [MDP_COMP_TYPE_RSZ] = {1, 0, 0},
+ [MDP_COMP_TYPE_WROT] = {1, 0, 0},
+ [MDP_COMP_TYPE_WDMA] = {1, 0, 0},
+ [MDP_COMP_TYPE_PATH1] = {0, 0, 2},
+ [MDP_COMP_TYPE_PATH2] = {0, 0, 3},
+ [MDP_COMP_TYPE_CCORR] = {1, 0, 0},
+ [MDP_COMP_TYPE_IMGI] = {0, 0, 2},
+ [MDP_COMP_TYPE_EXTO] = {0, 0, 2},
+ [MDP_COMP_TYPE_DL_PATH1] = {2, 2, 1},
+ [MDP_COMP_TYPE_DL_PATH2] = {2, 4, 1},
+};
+
+static const struct mdp_pipe_info mt8183_pipe_info[] = {
+ {MDP_PIPE_IMGI, 0, 0},
+ {MDP_PIPE_RDMA0, 0, 1},
+ {MDP_PIPE_WPEI, 0, 2},
+ {MDP_PIPE_WPEI2, 0, 3}
+};
+
+static const struct mdp_format mt8183_formats[] = {
+ {
+ .pixelformat = V4L2_PIX_FMT_GREY,
+ .mdp_color = MDP_COLOR_GREY,
+ .depth = { 8 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_RGB565X,
+ .mdp_color = MDP_COLOR_RGB565,
+ .depth = { 16 },
+ .row_depth = { 16 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_RGB565,
+ .mdp_color = MDP_COLOR_BGR565,
+ .depth = { 16 },
+ .row_depth = { 16 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_RGB24,
+ .mdp_color = MDP_COLOR_RGB888,
+ .depth = { 24 },
+ .row_depth = { 24 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_BGR24,
+ .mdp_color = MDP_COLOR_BGR888,
+ .depth = { 24 },
+ .row_depth = { 24 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_ABGR32,
+ .mdp_color = MDP_COLOR_BGRA8888,
+ .depth = { 32 },
+ .row_depth = { 32 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_ARGB32,
+ .mdp_color = MDP_COLOR_ARGB8888,
+ .depth = { 32 },
+ .row_depth = { 32 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_UYVY,
+ .mdp_color = MDP_COLOR_UYVY,
+ .depth = { 16 },
+ .row_depth = { 16 },
+ .num_planes = 1,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_VYUY,
+ .mdp_color = MDP_COLOR_VYUY,
+ .depth = { 16 },
+ .row_depth = { 16 },
+ .num_planes = 1,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_YUYV,
+ .mdp_color = MDP_COLOR_YUYV,
+ .depth = { 16 },
+ .row_depth = { 16 },
+ .num_planes = 1,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_YVYU,
+ .mdp_color = MDP_COLOR_YVYU,
+ .depth = { 16 },
+ .row_depth = { 16 },
+ .num_planes = 1,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_YUV420,
+ .mdp_color = MDP_COLOR_I420,
+ .depth = { 12 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_YVU420,
+ .mdp_color = MDP_COLOR_YV12,
+ .depth = { 12 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV12,
+ .mdp_color = MDP_COLOR_NV12,
+ .depth = { 12 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV21,
+ .mdp_color = MDP_COLOR_NV21,
+ .depth = { 12 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV16,
+ .mdp_color = MDP_COLOR_NV16,
+ .depth = { 16 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV61,
+ .mdp_color = MDP_COLOR_NV61,
+ .depth = { 16 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV24,
+ .mdp_color = MDP_COLOR_NV24,
+ .depth = { 24 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV42,
+ .mdp_color = MDP_COLOR_NV42,
+ .depth = { 24 },
+ .row_depth = { 8 },
+ .num_planes = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_MT21C,
+ .mdp_color = MDP_COLOR_420_BLKP_UFO,
+ .depth = { 8, 4 },
+ .row_depth = { 8, 8 },
+ .num_planes = 2,
+ .walign = 4,
+ .halign = 5,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_MM21,
+ .mdp_color = MDP_COLOR_420_BLKP,
+ .depth = { 8, 4 },
+ .row_depth = { 8, 8 },
+ .num_planes = 2,
+ .walign = 4,
+ .halign = 5,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV12M,
+ .mdp_color = MDP_COLOR_NV12,
+ .depth = { 8, 4 },
+ .row_depth = { 8, 8 },
+ .num_planes = 2,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV21M,
+ .mdp_color = MDP_COLOR_NV21,
+ .depth = { 8, 4 },
+ .row_depth = { 8, 8 },
+ .num_planes = 2,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV16M,
+ .mdp_color = MDP_COLOR_NV16,
+ .depth = { 8, 8 },
+ .row_depth = { 8, 8 },
+ .num_planes = 2,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_NV61M,
+ .mdp_color = MDP_COLOR_NV61,
+ .depth = { 8, 8 },
+ .row_depth = { 8, 8 },
+ .num_planes = 2,
+ .walign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_YUV420M,
+ .mdp_color = MDP_COLOR_I420,
+ .depth = { 8, 2, 2 },
+ .row_depth = { 8, 4, 4 },
+ .num_planes = 3,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }, {
+ .pixelformat = V4L2_PIX_FMT_YVU420M,
+ .mdp_color = MDP_COLOR_YV12,
+ .depth = { 8, 2, 2 },
+ .row_depth = { 8, 4, 4 },
+ .num_planes = 3,
+ .walign = 1,
+ .halign = 1,
+ .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
+ }
+};
+
static const struct mtk_mdp_driver_data mt8183_mdp_driver_data = {
.mdp_cfg = &mt8183_plat_cfg,
+ .event = mt8183_mdp_event,
+ .event_len = ARRAY_SIZE(mt8183_mdp_event),
+ .comp_list = &mt8183_comp_list,
+ .comp_data = mt8183_mdp_comp_data,
+ .comp_data_len = ARRAY_SIZE(mt8183_mdp_comp_data),
+ .comp_info = mt8183_comp_dt_info,
+ .comp_info_len = ARRAY_SIZE(mt8183_comp_dt_info),
+ .pipe_info = mt8183_pipe_info,
+ .pipe_info_len = ARRAY_SIZE(mt8183_pipe_info),
+ .format = mt8183_formats,
+ .format_len = ARRAY_SIZE(mt8183_formats),
};
static const struct of_device_id mdp_of_ids[] = {
@@ -119,7 +486,7 @@ static int mdp_probe(struct platform_device *pdev)
struct device_node *mdp_node;
struct platform_device *mm_pdev;
u32 i, event_ofst;
- int ret;
+ int ret, i, mutex_id;
mdp = devm_kzalloc(dev, sizeof(*mdp), GFP_KERNEL);
if (!mdp) {
@@ -143,7 +510,7 @@ static int mdp_probe(struct platform_device *pdev)
}
event_ofst = mdp->mdp_data->mdp_cfg->gce_event_offset;
- for (i = RDMA0_SOF; i < MDP_MAX_EVENT_COUNT; i++) {
+ for (i = 0; i < mdp->mdp_data->event_len; i++) {
s32 event_id;
if (!dev)
@@ -167,9 +534,15 @@ static int mdp_probe(struct platform_device *pdev)
goto err_return;
}
- for (i = 0; i < MDP_PIPE_MAX; i++) {
- mdp->mdp_mutex[i] = mtk_mutex_mdp_get(&mm_pdev->dev, i);
- if (!mdp->mdp_mutex[i]) {
+ for (i = 0; i < mdp->mdp_data->pipe_info_len; i++) {
+ mutex_id = mdp->mdp_data->pipe_info[i].mutex_id;
+ if (mdp->mdp_mutex[mutex_id])
+ continue;
+
+ mdp->mdp_mutex[mutex_id] =
+ mtk_mutex_mdp_get(&mm_pdev->dev, mdp->mdp_data->pipe_info[i].pipe_id);
+
+ if (!mdp->mdp_mutex[mutex_id]) {
ret = -ENODEV;
goto err_return;
}
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
index d996d9e71356..f6d70af80b3e 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
@@ -35,6 +35,18 @@ struct mdp_platform_config {
struct mtk_mdp_driver_data {
const struct mdp_platform_config *mdp_cfg;
+ const enum mdp_comp_event *event;
+ unsigned int event_len;
+ const struct mdp_comp_list *comp_list;
+ const struct mdp_comp_data *comp_data;
+ unsigned int comp_data_len;
+ const struct mdp_comp_info *comp_info;
+ unsigned int comp_info_len;
+ const struct mdp_pipe_info *pipe_info;
+ unsigned int pipe_info_len;
+ const struct mdp_format *format;
+ unsigned int format_len;
+ const enum mdp_mmsys_config_id *config_table;
};
struct mdp_dev {
@@ -67,6 +79,13 @@ struct mdp_dev {
atomic_t job_count;
};
+struct mdp_pipe_info {
+ enum mtk_mdp_pipe_id pipe_id;
+ u32 mmsys_id;
+ u32 mutex_id;
+ u32 sof;
+};
+
int mdp_vpu_get_locked(struct mdp_dev *mdp);
void mdp_vpu_put_locked(struct mdp_dev *mdp);
int mdp_vpu_register(struct mdp_dev *mdp);
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c
index 584804ef7bc4..2a8bb05226a0 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c
@@ -629,6 +629,8 @@ static int mdp_m2m_open(struct file *file)
int ret;
struct v4l2_format default_format;
+ mdp_format_init(mdp->mdp_data->format, mdp->mdp_data->format_len);
+
ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
if (!ctx)
return -ENOMEM;
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c
index a6caefb097be..d5bdba00b946 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c
@@ -10,226 +10,8 @@
#include "mtk-mdp3-core.h"
#include "mtk-mdp3-regs.h"
-static const struct mdp_format mdp_formats[] = {
- {
- .pixelformat = V4L2_PIX_FMT_GREY,
- .mdp_color = MDP_COLOR_GREY,
- .depth = { 8 },
- .row_depth = { 8 },
- .num_planes = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_RGB565X,
- .mdp_color = MDP_COLOR_RGB565,
- .depth = { 16 },
- .row_depth = { 16 },
- .num_planes = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_RGB565,
- .mdp_color = MDP_COLOR_BGR565,
- .depth = { 16 },
- .row_depth = { 16 },
- .num_planes = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_RGB24,
- .mdp_color = MDP_COLOR_RGB888,
- .depth = { 24 },
- .row_depth = { 24 },
- .num_planes = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_BGR24,
- .mdp_color = MDP_COLOR_BGR888,
- .depth = { 24 },
- .row_depth = { 24 },
- .num_planes = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_ABGR32,
- .mdp_color = MDP_COLOR_BGRA8888,
- .depth = { 32 },
- .row_depth = { 32 },
- .num_planes = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_ARGB32,
- .mdp_color = MDP_COLOR_ARGB8888,
- .depth = { 32 },
- .row_depth = { 32 },
- .num_planes = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_UYVY,
- .mdp_color = MDP_COLOR_UYVY,
- .depth = { 16 },
- .row_depth = { 16 },
- .num_planes = 1,
- .walign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_VYUY,
- .mdp_color = MDP_COLOR_VYUY,
- .depth = { 16 },
- .row_depth = { 16 },
- .num_planes = 1,
- .walign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_YUYV,
- .mdp_color = MDP_COLOR_YUYV,
- .depth = { 16 },
- .row_depth = { 16 },
- .num_planes = 1,
- .walign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_YVYU,
- .mdp_color = MDP_COLOR_YVYU,
- .depth = { 16 },
- .row_depth = { 16 },
- .num_planes = 1,
- .walign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_YUV420,
- .mdp_color = MDP_COLOR_I420,
- .depth = { 12 },
- .row_depth = { 8 },
- .num_planes = 1,
- .walign = 1,
- .halign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_YVU420,
- .mdp_color = MDP_COLOR_YV12,
- .depth = { 12 },
- .row_depth = { 8 },
- .num_planes = 1,
- .walign = 1,
- .halign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_NV12,
- .mdp_color = MDP_COLOR_NV12,
- .depth = { 12 },
- .row_depth = { 8 },
- .num_planes = 1,
- .walign = 1,
- .halign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_NV21,
- .mdp_color = MDP_COLOR_NV21,
- .depth = { 12 },
- .row_depth = { 8 },
- .num_planes = 1,
- .walign = 1,
- .halign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_NV16,
- .mdp_color = MDP_COLOR_NV16,
- .depth = { 16 },
- .row_depth = { 8 },
- .num_planes = 1,
- .walign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT,
- }, {
- .pixelformat = V4L2_PIX_FMT_NV61,
- .mdp_color = MDP_COLOR_NV61,
- .depth = { 16 },
- .row_depth = { 8 },
- .num_planes = 1,
- .walign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT,
- }, {
- .pixelformat = V4L2_PIX_FMT_NV24,
- .mdp_color = MDP_COLOR_NV24,
- .depth = { 24 },
- .row_depth = { 8 },
- .num_planes = 1,
- .flags = MDP_FMT_FLAG_OUTPUT,
- }, {
- .pixelformat = V4L2_PIX_FMT_NV42,
- .mdp_color = MDP_COLOR_NV42,
- .depth = { 24 },
- .row_depth = { 8 },
- .num_planes = 1,
- .flags = MDP_FMT_FLAG_OUTPUT,
- }, {
- .pixelformat = V4L2_PIX_FMT_MT21C,
- .mdp_color = MDP_COLOR_420_BLK_UFO,
- .depth = { 8, 4 },
- .row_depth = { 8, 8 },
- .num_planes = 2,
- .walign = 4,
- .halign = 5,
- .flags = MDP_FMT_FLAG_OUTPUT,
- }, {
- .pixelformat = V4L2_PIX_FMT_MM21,
- .mdp_color = MDP_COLOR_420_BLK,
- .depth = { 8, 4 },
- .row_depth = { 8, 8 },
- .num_planes = 2,
- .walign = 4,
- .halign = 5,
- .flags = MDP_FMT_FLAG_OUTPUT,
- }, {
- .pixelformat = V4L2_PIX_FMT_NV12M,
- .mdp_color = MDP_COLOR_NV12,
- .depth = { 8, 4 },
- .row_depth = { 8, 8 },
- .num_planes = 2,
- .walign = 1,
- .halign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_NV21M,
- .mdp_color = MDP_COLOR_NV21,
- .depth = { 8, 4 },
- .row_depth = { 8, 8 },
- .num_planes = 2,
- .walign = 1,
- .halign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_NV16M,
- .mdp_color = MDP_COLOR_NV16,
- .depth = { 8, 8 },
- .row_depth = { 8, 8 },
- .num_planes = 2,
- .walign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT,
- }, {
- .pixelformat = V4L2_PIX_FMT_NV61M,
- .mdp_color = MDP_COLOR_NV61,
- .depth = { 8, 8 },
- .row_depth = { 8, 8 },
- .num_planes = 2,
- .walign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT,
- }, {
- .pixelformat = V4L2_PIX_FMT_YUV420M,
- .mdp_color = MDP_COLOR_I420,
- .depth = { 8, 2, 2 },
- .row_depth = { 8, 4, 4 },
- .num_planes = 3,
- .walign = 1,
- .halign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }, {
- .pixelformat = V4L2_PIX_FMT_YVU420M,
- .mdp_color = MDP_COLOR_YV12,
- .depth = { 8, 2, 2 },
- .row_depth = { 8, 4, 4 },
- .num_planes = 3,
- .walign = 1,
- .halign = 1,
- .flags = MDP_FMT_FLAG_OUTPUT | MDP_FMT_FLAG_CAPTURE,
- }
-};
+static const struct mdp_format *mdp_formats;
+static u32 format_len;
static const struct mdp_limit mdp_def_limit = {
.out_limit = {
@@ -256,7 +38,7 @@ static const struct mdp_format *mdp_find_fmt(u32 pixelformat, u32 type)
flag = V4L2_TYPE_IS_OUTPUT(type) ? MDP_FMT_FLAG_OUTPUT :
MDP_FMT_FLAG_CAPTURE;
- for (i = 0; i < ARRAY_SIZE(mdp_formats); ++i) {
+ for (i = 0; i < format_len; ++i) {
if (!(mdp_formats[i].flags & flag))
continue;
if (mdp_formats[i].pixelformat == pixelformat)
@@ -271,7 +53,7 @@ static const struct mdp_format *mdp_find_fmt_by_index(u32 index, u32 type)
flag = V4L2_TYPE_IS_OUTPUT(type) ? MDP_FMT_FLAG_OUTPUT :
MDP_FMT_FLAG_CAPTURE;
- for (i = 0; i < ARRAY_SIZE(mdp_formats); ++i) {
+ for (i = 0; i < format_len; ++i) {
if (!(mdp_formats[i].flags & flag))
continue;
if (index == num)
@@ -744,3 +526,10 @@ int mdp_frameparam_init(struct mdp_frameparam *param)
return 0;
}
+
+void mdp_format_init(const struct mdp_format *format, u32 length)
+{
+ mdp_formats = format;
+ format_len = length;
+}
+
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
index b3aaef8eb7eb..3eb294bd9516 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
@@ -18,14 +18,17 @@
* V-subsample: 0, 1
* Color group: 0-RGB, 1-YUV, 2-raw
*/
-#define MDP_COLOR(PACKED, LOOSE, VIDEO, PLANE, HF, VF, BITS, GROUP, SWAP, ID)\
- (((PACKED) << 27) | ((LOOSE) << 26) | ((VIDEO) << 23) |\
+#define MDP_COLOR(COMPRESS, PACKED, LOOSE, VIDEO, PLANE, HF, VF, BITS, GROUP, SWAP, ID)\
+ (((COMPRESS) << 29) | ((PACKED) << 28) | ((LOOSE) << 27) | ((VIDEO) << 23) |\
((PLANE) << 21) | ((HF) << 19) | ((VF) << 18) | ((BITS) << 8) |\
((GROUP) << 6) | ((SWAP) << 5) | ((ID) << 0))
-#define MDP_COLOR_IS_10BIT_PACKED(c) ((0x08000000 & (c)) >> 27)
-#define MDP_COLOR_IS_10BIT_LOOSE(c) (((0x0c000000 & (c)) >> 26) == 1)
-#define MDP_COLOR_IS_10BIT_TILE(c) (((0x0c000000 & (c)) >> 26) == 3)
+#define MDP_COLOR_IS_HYFBC_COMPRESS(c) ((0x40000000 & (c)) >> 30)
+#define MDP_COLOR_IS_COMPRESS(c) ((0x20000000 & (c)) >> 29)
+#define MDP_COLOR_IS_10BIT_PACKED(c) ((0x10000000 & (c)) >> 28)
+#define MDP_COLOR_IS_10BIT_LOOSE(c) (((0x18000000 & (c)) >> 27) == 1)
+#define MDP_COLOR_IS_10BIT_TILE(c) (((0x18000000 & (c)) >> 27) == 3)
+#define MDP_COLOR_IS_10BIT_JUMP(c) ((0x04000000 & (c)) >> 26)
#define MDP_COLOR_IS_UFP(c) ((0x02000000 & (c)) >> 25)
#define MDP_COLOR_IS_INTERLACED(c) ((0x01000000 & (c)) >> 24)
#define MDP_COLOR_IS_BLOCK_MODE(c) ((0x00800000 & (c)) >> 23)
@@ -42,148 +45,120 @@
#define MDP_COLOR_IS_YUV(c) (MDP_COLOR_GET_GROUP(c) == 1)
#define MDP_COLOR_IS_UV_COPLANE(c) ((MDP_COLOR_GET_PLANE_COUNT(c) == 2) &&\
MDP_COLOR_IS_YUV(c))
+#define MDP_COLOR_IS_10BIT(c) (((0x18000000 & (c)) >> 27) != 0)
+#define MDP_COLOR_GET_AUO_MODE(c) (MDP_COLOR_IS_10BIT_JUMP(c))
enum mdp_color {
MDP_COLOR_UNKNOWN = 0,
- //MDP_COLOR_FULLG8,
- MDP_COLOR_FULLG8_RGGB = MDP_COLOR(0, 0, 0, 1, 0, 0, 8, 2, 0, 21),
- MDP_COLOR_FULLG8_GRBG = MDP_COLOR(0, 0, 0, 1, 0, 1, 8, 2, 0, 21),
- MDP_COLOR_FULLG8_GBRG = MDP_COLOR(0, 0, 0, 1, 1, 0, 8, 2, 0, 21),
- MDP_COLOR_FULLG8_BGGR = MDP_COLOR(0, 0, 0, 1, 1, 1, 8, 2, 0, 21),
- MDP_COLOR_FULLG8 = MDP_COLOR_FULLG8_BGGR,
-
- //MDP_COLOR_FULLG10,
- MDP_COLOR_FULLG10_RGGB = MDP_COLOR(0, 0, 0, 1, 0, 0, 10, 2, 0, 21),
- MDP_COLOR_FULLG10_GRBG = MDP_COLOR(0, 0, 0, 1, 0, 1, 10, 2, 0, 21),
- MDP_COLOR_FULLG10_GBRG = MDP_COLOR(0, 0, 0, 1, 1, 0, 10, 2, 0, 21),
- MDP_COLOR_FULLG10_BGGR = MDP_COLOR(0, 0, 0, 1, 1, 1, 10, 2, 0, 21),
- MDP_COLOR_FULLG10 = MDP_COLOR_FULLG10_BGGR,
-
- //MDP_COLOR_FULLG12,
- MDP_COLOR_FULLG12_RGGB = MDP_COLOR(0, 0, 0, 1, 0, 0, 12, 2, 0, 21),
- MDP_COLOR_FULLG12_GRBG = MDP_COLOR(0, 0, 0, 1, 0, 1, 12, 2, 0, 21),
- MDP_COLOR_FULLG12_GBRG = MDP_COLOR(0, 0, 0, 1, 1, 0, 12, 2, 0, 21),
- MDP_COLOR_FULLG12_BGGR = MDP_COLOR(0, 0, 0, 1, 1, 1, 12, 2, 0, 21),
- MDP_COLOR_FULLG12 = MDP_COLOR_FULLG12_BGGR,
-
- //MDP_COLOR_FULLG14,
- MDP_COLOR_FULLG14_RGGB = MDP_COLOR(0, 0, 0, 1, 0, 0, 14, 2, 0, 21),
- MDP_COLOR_FULLG14_GRBG = MDP_COLOR(0, 0, 0, 1, 0, 1, 14, 2, 0, 21),
- MDP_COLOR_FULLG14_GBRG = MDP_COLOR(0, 0, 0, 1, 1, 0, 14, 2, 0, 21),
- MDP_COLOR_FULLG14_BGGR = MDP_COLOR(0, 0, 0, 1, 1, 1, 14, 2, 0, 21),
- MDP_COLOR_FULLG14 = MDP_COLOR_FULLG14_BGGR,
-
- MDP_COLOR_UFO10 = MDP_COLOR(0, 0, 0, 1, 0, 0, 10, 2, 0, 24),
-
- //MDP_COLOR_BAYER8,
- MDP_COLOR_BAYER8_RGGB = MDP_COLOR(0, 0, 0, 1, 0, 0, 8, 2, 0, 20),
- MDP_COLOR_BAYER8_GRBG = MDP_COLOR(0, 0, 0, 1, 0, 1, 8, 2, 0, 20),
- MDP_COLOR_BAYER8_GBRG = MDP_COLOR(0, 0, 0, 1, 1, 0, 8, 2, 0, 20),
- MDP_COLOR_BAYER8_BGGR = MDP_COLOR(0, 0, 0, 1, 1, 1, 8, 2, 0, 20),
- MDP_COLOR_BAYER8 = MDP_COLOR_BAYER8_BGGR,
-
- //MDP_COLOR_BAYER10,
- MDP_COLOR_BAYER10_RGGB = MDP_COLOR(0, 0, 0, 1, 0, 0, 10, 2, 0, 20),
- MDP_COLOR_BAYER10_GRBG = MDP_COLOR(0, 0, 0, 1, 0, 1, 10, 2, 0, 20),
- MDP_COLOR_BAYER10_GBRG = MDP_COLOR(0, 0, 0, 1, 1, 0, 10, 2, 0, 20),
- MDP_COLOR_BAYER10_BGGR = MDP_COLOR(0, 0, 0, 1, 1, 1, 10, 2, 0, 20),
- MDP_COLOR_BAYER10 = MDP_COLOR_BAYER10_BGGR,
-
- //MDP_COLOR_BAYER12,
- MDP_COLOR_BAYER12_RGGB = MDP_COLOR(0, 0, 0, 1, 0, 0, 12, 2, 0, 20),
- MDP_COLOR_BAYER12_GRBG = MDP_COLOR(0, 0, 0, 1, 0, 1, 12, 2, 0, 20),
- MDP_COLOR_BAYER12_GBRG = MDP_COLOR(0, 0, 0, 1, 1, 0, 12, 2, 0, 20),
- MDP_COLOR_BAYER12_BGGR = MDP_COLOR(0, 0, 0, 1, 1, 1, 12, 2, 0, 20),
- MDP_COLOR_BAYER12 = MDP_COLOR_BAYER12_BGGR,
-
- //MDP_COLOR_BAYER14,
- MDP_COLOR_BAYER14_RGGB = MDP_COLOR(0, 0, 0, 1, 0, 0, 14, 2, 0, 20),
- MDP_COLOR_BAYER14_GRBG = MDP_COLOR(0, 0, 0, 1, 0, 1, 14, 2, 0, 20),
- MDP_COLOR_BAYER14_GBRG = MDP_COLOR(0, 0, 0, 1, 1, 0, 14, 2, 0, 20),
- MDP_COLOR_BAYER14_BGGR = MDP_COLOR(0, 0, 0, 1, 1, 1, 14, 2, 0, 20),
- MDP_COLOR_BAYER14 = MDP_COLOR_BAYER14_BGGR,
-
- MDP_COLOR_RGB48 = MDP_COLOR(0, 0, 0, 1, 0, 0, 48, 0, 0, 23),
- /* For bayer+mono raw-16 */
- MDP_COLOR_RGB565_RAW = MDP_COLOR(0, 0, 0, 1, 0, 0, 16, 2, 0, 0),
-
- MDP_COLOR_BAYER8_UNPAK = MDP_COLOR(0, 0, 0, 1, 0, 0, 8, 2, 0, 22),
- MDP_COLOR_BAYER10_UNPAK = MDP_COLOR(0, 0, 0, 1, 0, 0, 10, 2, 0, 22),
- MDP_COLOR_BAYER12_UNPAK = MDP_COLOR(0, 0, 0, 1, 0, 0, 12, 2, 0, 22),
- MDP_COLOR_BAYER14_UNPAK = MDP_COLOR(0, 0, 0, 1, 0, 0, 14, 2, 0, 22),
-
- /* Unified formats */
- MDP_COLOR_GREY = MDP_COLOR(0, 0, 0, 1, 0, 0, 8, 1, 0, 7),
-
- MDP_COLOR_RGB565 = MDP_COLOR(0, 0, 0, 1, 0, 0, 16, 0, 0, 0),
- MDP_COLOR_BGR565 = MDP_COLOR(0, 0, 0, 1, 0, 0, 16, 0, 1, 0),
- MDP_COLOR_RGB888 = MDP_COLOR(0, 0, 0, 1, 0, 0, 24, 0, 1, 1),
- MDP_COLOR_BGR888 = MDP_COLOR(0, 0, 0, 1, 0, 0, 24, 0, 0, 1),
- MDP_COLOR_RGBA8888 = MDP_COLOR(0, 0, 0, 1, 0, 0, 32, 0, 1, 2),
- MDP_COLOR_BGRA8888 = MDP_COLOR(0, 0, 0, 1, 0, 0, 32, 0, 0, 2),
- MDP_COLOR_ARGB8888 = MDP_COLOR(0, 0, 0, 1, 0, 0, 32, 0, 1, 3),
- MDP_COLOR_ABGR8888 = MDP_COLOR(0, 0, 0, 1, 0, 0, 32, 0, 0, 3),
-
- MDP_COLOR_UYVY = MDP_COLOR(0, 0, 0, 1, 1, 0, 16, 1, 0, 4),
- MDP_COLOR_VYUY = MDP_COLOR(0, 0, 0, 1, 1, 0, 16, 1, 1, 4),
- MDP_COLOR_YUYV = MDP_COLOR(0, 0, 0, 1, 1, 0, 16, 1, 0, 5),
- MDP_COLOR_YVYU = MDP_COLOR(0, 0, 0, 1, 1, 0, 16, 1, 1, 5),
-
- MDP_COLOR_I420 = MDP_COLOR(0, 0, 0, 3, 1, 1, 8, 1, 0, 8),
- MDP_COLOR_YV12 = MDP_COLOR(0, 0, 0, 3, 1, 1, 8, 1, 1, 8),
- MDP_COLOR_I422 = MDP_COLOR(0, 0, 0, 3, 1, 0, 8, 1, 0, 9),
- MDP_COLOR_YV16 = MDP_COLOR(0, 0, 0, 3, 1, 0, 8, 1, 1, 9),
- MDP_COLOR_I444 = MDP_COLOR(0, 0, 0, 3, 0, 0, 8, 1, 0, 10),
- MDP_COLOR_YV24 = MDP_COLOR(0, 0, 0, 3, 0, 0, 8, 1, 1, 10),
-
- MDP_COLOR_NV12 = MDP_COLOR(0, 0, 0, 2, 1, 1, 8, 1, 0, 12),
- MDP_COLOR_NV21 = MDP_COLOR(0, 0, 0, 2, 1, 1, 8, 1, 1, 12),
- MDP_COLOR_NV16 = MDP_COLOR(0, 0, 0, 2, 1, 0, 8, 1, 0, 13),
- MDP_COLOR_NV61 = MDP_COLOR(0, 0, 0, 2, 1, 0, 8, 1, 1, 13),
- MDP_COLOR_NV24 = MDP_COLOR(0, 0, 0, 2, 0, 0, 8, 1, 0, 14),
- MDP_COLOR_NV42 = MDP_COLOR(0, 0, 0, 2, 0, 0, 8, 1, 1, 14),
-
- /* Mediatek proprietary formats */
- /* UFO encoded block mode */
- MDP_COLOR_420_BLK_UFO = MDP_COLOR(0, 0, 5, 2, 1, 1, 256, 1, 0, 12),
- /* Block mode */
- MDP_COLOR_420_BLK = MDP_COLOR(0, 0, 1, 2, 1, 1, 256, 1, 0, 12),
- /* Block mode + field mode */
- MDP_COLOR_420_BLKI = MDP_COLOR(0, 0, 3, 2, 1, 1, 256, 1, 0, 12),
- /* Block mode */
- MDP_COLOR_422_BLK = MDP_COLOR(0, 0, 1, 1, 1, 0, 512, 1, 0, 4),
-
- MDP_COLOR_IYU2 = MDP_COLOR(0, 0, 0, 1, 0, 0, 24, 1, 0, 25),
- MDP_COLOR_YUV444 = MDP_COLOR(0, 0, 0, 1, 0, 0, 24, 1, 0, 30),
-
- /* Packed 10-bit formats */
- MDP_COLOR_RGBA1010102 = MDP_COLOR(1, 0, 0, 1, 0, 0, 32, 0, 1, 2),
- MDP_COLOR_BGRA1010102 = MDP_COLOR(1, 0, 0, 1, 0, 0, 32, 0, 0, 2),
- /* Packed 10-bit UYVY */
- MDP_COLOR_UYVY_10P = MDP_COLOR(1, 0, 0, 1, 1, 0, 20, 1, 0, 4),
- /* Packed 10-bit NV21 */
- MDP_COLOR_NV21_10P = MDP_COLOR(1, 0, 0, 2, 1, 1, 10, 1, 1, 12),
- /* 10-bit block mode */
- MDP_COLOR_420_BLK_10_H = MDP_COLOR(1, 0, 1, 2, 1, 1, 320, 1, 0, 12),
- /* 10-bit HEVC tile mode */
- MDP_COLOR_420_BLK_10_V = MDP_COLOR(1, 1, 1, 2, 1, 1, 320, 1, 0, 12),
- /* UFO encoded 10-bit block mode */
- MDP_COLOR_420_BLK_U10_H = MDP_COLOR(1, 0, 5, 2, 1, 1, 320, 1, 0, 12),
- /* UFO encoded 10-bit HEVC tile mode */
- MDP_COLOR_420_BLK_U10_V = MDP_COLOR(1, 1, 5, 2, 1, 1, 320, 1, 0, 12),
-
- /* Loose 10-bit formats */
- MDP_COLOR_UYVY_10L = MDP_COLOR(0, 1, 0, 1, 1, 0, 20, 1, 0, 4),
- MDP_COLOR_VYUY_10L = MDP_COLOR(0, 1, 0, 1, 1, 0, 20, 1, 1, 4),
- MDP_COLOR_YUYV_10L = MDP_COLOR(0, 1, 0, 1, 1, 0, 20, 1, 0, 5),
- MDP_COLOR_YVYU_10L = MDP_COLOR(0, 1, 0, 1, 1, 0, 20, 1, 1, 5),
- MDP_COLOR_NV12_10L = MDP_COLOR(0, 1, 0, 2, 1, 1, 10, 1, 0, 12),
- MDP_COLOR_NV21_10L = MDP_COLOR(0, 1, 0, 2, 1, 1, 10, 1, 1, 12),
- MDP_COLOR_NV16_10L = MDP_COLOR(0, 1, 0, 2, 1, 0, 10, 1, 0, 13),
- MDP_COLOR_NV61_10L = MDP_COLOR(0, 1, 0, 2, 1, 0, 10, 1, 1, 13),
- MDP_COLOR_YV12_10L = MDP_COLOR(0, 1, 0, 3, 1, 1, 10, 1, 1, 8),
- MDP_COLOR_I420_10L = MDP_COLOR(0, 1, 0, 3, 1, 1, 10, 1, 0, 8),
+ // Unified format
+ MDP_COLOR_GREY = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 8, 1, 0, 7),
+
+ MDP_COLOR_RGB565 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 16, 0, 0, 0),
+ MDP_COLOR_BGR565 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 16, 0, 1, 0),
+ MDP_COLOR_RGB888 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 24, 0, 1, 1),
+ MDP_COLOR_BGR888 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 24, 0, 0, 1),
+ MDP_COLOR_RGBA8888 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 32, 0, 1, 2),
+ MDP_COLOR_BGRA8888 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 32, 0, 0, 2),
+ MDP_COLOR_ARGB8888 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 32, 0, 1, 3),
+ MDP_COLOR_ABGR8888 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 32, 0, 0, 3),
+
+ MDP_COLOR_UYVY = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 16, 1, 0, 4),
+ MDP_COLOR_VYUY = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 16, 1, 1, 4),
+ MDP_COLOR_YUYV = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 16, 1, 0, 5),
+ MDP_COLOR_YVYU = MDP_COLOR(0, 0, 0, 0, 1, 1, 0, 16, 1, 1, 5),
+
+ MDP_COLOR_I420 = MDP_COLOR(0, 0, 0, 0, 3, 1, 1, 8, 1, 0, 8),
+ MDP_COLOR_YV12 = MDP_COLOR(0, 0, 0, 0, 3, 1, 1, 8, 1, 1, 8),
+ MDP_COLOR_I422 = MDP_COLOR(0, 0, 0, 0, 3, 1, 0, 8, 1, 0, 9),
+ MDP_COLOR_YV16 = MDP_COLOR(0, 0, 0, 0, 3, 1, 0, 8, 1, 1, 9),
+ MDP_COLOR_I444 = MDP_COLOR(0, 0, 0, 0, 3, 0, 0, 8, 1, 0, 10),
+ MDP_COLOR_YV24 = MDP_COLOR(0, 0, 0, 0, 3, 0, 0, 8, 1, 1, 10),
+
+ MDP_COLOR_NV12 = MDP_COLOR(0, 0, 0, 0, 2, 1, 1, 8, 1, 0, 12),
+ MDP_COLOR_NV21 = MDP_COLOR(0, 0, 0, 0, 2, 1, 1, 8, 1, 1, 12),
+ MDP_COLOR_NV16 = MDP_COLOR(0, 0, 0, 0, 2, 1, 0, 8, 1, 0, 13),
+ MDP_COLOR_NV61 = MDP_COLOR(0, 0, 0, 0, 2, 1, 0, 8, 1, 1, 13),
+ MDP_COLOR_NV24 = MDP_COLOR(0, 0, 0, 0, 2, 0, 0, 8, 1, 0, 14),
+ MDP_COLOR_NV42 = MDP_COLOR(0, 0, 0, 0, 2, 0, 0, 8, 1, 1, 14),
+
+ // Mediatek proprietary format
+ //Frame mode + Block mode + UFO
+ MDP_COLOR_420_BLKP_UFO = MDP_COLOR(0, 0, 0, 5, 2, 1, 1, 256, 1, 0, 12),
+ //Frame mode + Block mode + UFO AUO
+ MDP_COLOR_420_BLKP_UFO_AUO = MDP_COLOR(0, 0, 0, 13, 2, 1, 1, 256, 1, 0, 12),
+ //Frame mode + Block mode
+ MDP_COLOR_420_BLKP = MDP_COLOR(0, 0, 0, 1, 2, 1, 1, 256, 1, 0, 12),
+ //Field mode + Block mode
+ MDP_COLOR_420_BLKI = MDP_COLOR(0, 0, 0, 3, 2, 1, 1, 256, 1, 0, 12),
+ //Frame mode
+ MDP_COLOR_422_BLKP = MDP_COLOR(0, 0, 0, 1, 1, 1, 0, 512, 1, 0, 4),
+
+ MDP_COLOR_IYU2 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 24, 1, 0, 25),
+ MDP_COLOR_YUV444 = MDP_COLOR(0, 0, 0, 0, 1, 0, 0, 24, 1, 0, 30),
+
+ // Mediatek proprietary 10bit format
+ MDP_COLOR_RGBA1010102 = MDP_COLOR(0, 1, 0, 0, 1, 0, 0, 32, 0, 1, 2),
+ MDP_COLOR_BGRA1010102 = MDP_COLOR(0, 1, 0, 0, 1, 0, 0, 32, 0, 0, 2),
+ MDP_COLOR_ARGB1010102 = MDP_COLOR(0, 1, 0, 0, 1, 0, 0, 32, 0, 1, 3),
+ MDP_COLOR_ABGR1010102 = MDP_COLOR(0, 1, 0, 0, 1, 0, 0, 32, 0, 0, 3),
+ //Packed 10bit UYVY
+ MDP_COLOR_UYVY_10P = MDP_COLOR(0, 1, 0, 0, 1, 1, 0, 20, 1, 0, 4),
+ //Packed 10bit NV21
+ MDP_COLOR_NV12_10P = MDP_COLOR(0, 1, 0, 0, 2, 1, 1, 10, 1, 0, 12),
+ MDP_COLOR_NV21_10P = MDP_COLOR(0, 1, 0, 0, 2, 1, 1, 10, 1, 1, 12),
+ //Frame mode + Block mode
+ MDP_COLOR_420_BLKP_10_H = MDP_COLOR(0, 1, 0, 1, 2, 1, 1, 320, 1, 0, 12),
+ //Frame mode + HEVC tile mode
+ MDP_COLOR_420_BLKP_10_V = MDP_COLOR(0, 1, 1, 1, 2, 1, 1, 320, 1, 0, 12),
+ //Frame mode + Block mode + Jump
+ MDP_COLOR_420_BLKP_10_H_JUMP = MDP_COLOR(0, 1, 0, 9, 2, 1, 1, 320, 1, 0, 12),
+ //Frame mode + HEVC tile mode + Jump
+ MDP_COLOR_420_BLKP_10_V_JUMP = MDP_COLOR(0, 1, 1, 9, 2, 1, 1, 320, 1, 0, 12),
+ //Frame mode + Block mode
+ MDP_COLOR_420_BLKP_UFO_10_H = MDP_COLOR(0, 1, 0, 5, 2, 1, 1, 320, 1, 0, 12),
+ //Frame mode + HEVC tile mode
+ MDP_COLOR_420_BLKP_UFO_10_V = MDP_COLOR(0, 1, 1, 5, 2, 1, 1, 320, 1, 0, 12),
+ //Frame mode + Block mode + Jump
+ MDP_COLOR_420_BLKP_UFO_10_H_JUMP = MDP_COLOR(0, 1, 0, 13, 2, 1, 1, 320, 1, 0, 12),
+ //Frame mode + HEVC tile mode + Jump
+ MDP_COLOR_420_BLKP_UFO_10_V_JUMP = MDP_COLOR(0, 1, 1, 13, 2, 1, 1, 320, 1, 0, 12),
+
+ // Loose 10bit format
+ MDP_COLOR_UYVY_10L = MDP_COLOR(0, 0, 1, 0, 1, 1, 0, 20, 1, 0, 4),
+ MDP_COLOR_VYUY_10L = MDP_COLOR(0, 0, 1, 0, 1, 1, 0, 20, 1, 1, 4),
+ MDP_COLOR_YUYV_10L = MDP_COLOR(0, 0, 1, 0, 1, 1, 0, 20, 1, 0, 5),
+ MDP_COLOR_YVYU_10L = MDP_COLOR(0, 0, 1, 0, 1, 1, 0, 20, 1, 1, 5),
+ MDP_COLOR_NV12_10L = MDP_COLOR(0, 0, 1, 0, 2, 1, 1, 16, 1, 0, 12),
+ MDP_COLOR_NV21_10L = MDP_COLOR(0, 0, 1, 0, 2, 1, 1, 16, 1, 1, 12),
+ MDP_COLOR_NV16_10L = MDP_COLOR(0, 0, 1, 0, 2, 1, 0, 16, 1, 0, 13),
+ MDP_COLOR_NV61_10L = MDP_COLOR(0, 0, 1, 0, 2, 1, 0, 16, 1, 1, 13),
+ MDP_COLOR_YV12_10L = MDP_COLOR(0, 0, 1, 0, 3, 1, 1, 16, 1, 1, 8),
+ MDP_COLOR_I420_10L = MDP_COLOR(0, 0, 1, 0, 3, 1, 1, 16, 1, 0, 8),
+
+ MDP_COLOR_YV12_10P = MDP_COLOR(0, 1, 0, 0, 3, 1, 1, 10, 1, 1, 8),
+ MDP_COLOR_I422_10P = MDP_COLOR(0, 1, 0, 0, 3, 1, 0, 10, 1, 0, 9),
+ MDP_COLOR_NV16_10P = MDP_COLOR(0, 1, 0, 0, 2, 1, 0, 10, 1, 0, 13),
+ MDP_COLOR_NV61_10P = MDP_COLOR(0, 1, 0, 0, 2, 1, 0, 10, 1, 1, 13),
+
+ MDP_COLOR_I422_10L = MDP_COLOR(0, 0, 1, 0, 3, 1, 0, 16, 1, 0, 9),
+
+ MDP_COLOR_RGBA8888_AFBC = MDP_COLOR(1, 0, 0, 0, 1, 0, 0, 32, 0, 1, 2),
+ MDP_COLOR_BGRA8888_AFBC = MDP_COLOR(1, 0, 0, 0, 1, 0, 0, 32, 0, 0, 2),
+ MDP_COLOR_ARGB8888_AFBC = MDP_COLOR(1, 0, 0, 0, 1, 0, 0, 32, 0, 1, 3),
+ MDP_COLOR_ABGR8888_AFBC = MDP_COLOR(1, 0, 0, 0, 1, 0, 0, 32, 0, 0, 3),
+ MDP_COLOR_RGBA1010102_AFBC = MDP_COLOR(1, 1, 0, 0, 1, 0, 0, 32, 0, 1, 2),
+ MDP_COLOR_BGRA1010102_AFBC = MDP_COLOR(1, 1, 0, 0, 1, 0, 0, 32, 0, 0, 2),
+ MDP_COLOR_ARGB1010102_AFBC = MDP_COLOR(1, 1, 0, 0, 1, 0, 0, 32, 0, 1, 3),
+ MDP_COLOR_ABGR1010102_AFBC = MDP_COLOR(1, 1, 0, 0, 1, 0, 0, 32, 0, 0, 3),
+
+ MDP_COLOR_NV12_AFBC = MDP_COLOR(1, 0, 0, 0, 2, 1, 1, 12, 1, 0, 12),
+ MDP_COLOR_P010_AFBC = MDP_COLOR(1, 1, 0, 0, 2, 1, 1, 10, 1, 0, 12),
+
+ MDP_COLOR_NV12_HYFBC = MDP_COLOR(2, 0, 0, 0, 2, 1, 1, 8, 1, 0, 12),
+ MDP_COLOR_NV21_HYFBC = MDP_COLOR(2, 0, 0, 0, 2, 1, 1, 8, 1, 1, 12),
+ MDP_COLOR_NV12_10P_HYFBC = MDP_COLOR(2, 1, 0, 0, 2, 1, 1, 10, 1, 0, 12),
+ MDP_COLOR_NV21_10P_HYFBC = MDP_COLOR(2, 1, 0, 0, 2, 1, 1, 10, 1, 1, 12),
};
/* Minimum Y stride that is accepted by MDP HW */
@@ -368,5 +343,6 @@ void mdp_set_dst_config(struct img_output *out,
struct mdp_frame *frame, struct vb2_buffer *vb);
int mdp_frameparam_init(struct mdp_frameparam *param);
+void mdp_format_init(const struct mdp_format *format, u32 length);
#endif /* __MTK_MDP3_REGS_H__ */
--
2.18.0
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^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v1 4/9] dt-bindings: media: mediatek: mdp3: add additional function block yaml
2021-09-17 2:51 [PATCH v1 1/9] soc: mediatek: mmsys: expand MDP enum for chip independence architecture roy-cw.yeh
2021-09-17 2:51 ` [PATCH v1 2/9] soc: mediatek: mutex: expand parameter for mdp mutex function roy-cw.yeh
2021-09-17 2:51 ` [PATCH v1 3/9] media: platform: mtk-mdp3: add chip independence architecture roy-cw.yeh
@ 2021-09-17 2:51 ` roy-cw.yeh
2021-09-17 2:51 ` [PATCH v1 5/9] arm64: dts: mt8195: add mdp3 node roy-cw.yeh
` (3 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: roy-cw.yeh @ 2021-09-17 2:51 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, Roy-CW . Yeh,
jason-jh . lin, daoyuan huang, Ping-Hsun Wu, Moudy Ho,
Enric Balletbo i Serra, Yongqiang Niu, devicetree, linux-kernel,
linux-media, linux-arm-kernel, linux-mediatek
From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
Add additional function block yaml in mt8195
Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
.../bindings/arm/mediatek/mediatek,mmsys.yaml | 2 +
.../bindings/arm/mediatek/mediatek,mutex.yaml | 4 ++
.../bindings/media/mediatek,mdp3-aal.yaml | 62 +++++++++++++++++
.../bindings/media/mediatek,mdp3-color.yaml | 62 +++++++++++++++++
.../bindings/media/mediatek,mdp3-fg.yaml | 61 +++++++++++++++++
.../bindings/media/mediatek,mdp3-hdr.yaml | 61 +++++++++++++++++
.../bindings/media/mediatek,mdp3-merge.yaml | 62 +++++++++++++++++
.../bindings/media/mediatek,mdp3-ovl.yaml | 61 +++++++++++++++++
.../bindings/media/mediatek,mdp3-pad.yaml | 62 +++++++++++++++++
.../bindings/media/mediatek,mdp3-rdma.yaml | 22 +++++-
.../bindings/media/mediatek,mdp3-rsz.yaml | 2 +
.../bindings/media/mediatek,mdp3-split.yaml | 67 +++++++++++++++++++
.../bindings/media/mediatek,mdp3-stitch.yaml | 62 +++++++++++++++++
.../bindings/media/mediatek,mdp3-tcc.yaml | 62 +++++++++++++++++
.../bindings/media/mediatek,mdp3-tdshp.yaml | 61 +++++++++++++++++
.../bindings/media/mediatek,mdp3-wrot.yaml | 2 +
16 files changed, 713 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-aal.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-color.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-merge.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-ovl.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-pad.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-split.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index 679437ee2590..7b46b8156a12 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -33,6 +33,8 @@ properties:
- mediatek,mt8365-mmsys
- mediatek,mt8195-vdosys0
- mediatek,mt8195-vdosys1
+ - mediatek,mt8195-vppsys0
+ - mediatek,mt8195-vppsys1
- const: syscon
- items:
- const: mediatek,mt7623-mmsys
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mutex.yaml
index 1a1c049aa929..41dc1383131a 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mutex.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mutex.yaml
@@ -37,6 +37,10 @@ properties:
- const: mediatek,mt8192-disp-mutex
- items:
- const: mediatek,mt8195-disp-mutex
+ - items:
+ - const: mediatek,mt8195-vpp0-mutex
+ - items:
+ - const: mediatek,mt8195-vpp1-mutex
reg:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-aal.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-aal.yaml
new file mode 100644
index 000000000000..54535aac8942
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-aal.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-aal.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 AAL Device Tree Bindings
+
+maintainers:
+ - Daoyuan Huang <daoyuan.huang@mediatek.com>
+ - Moudy Ho <moudy.ho@mediatek.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components is responsible for backlight power saving
+ and sunlight visibility improving.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - mediatek,mt8195-mdp3-aal
+
+ mediatek,mdp3-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
+ description: |
+ HW index to distinguish same functionality modules.
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - mediatek,mdp3-id
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ mdp3_aal0: mdp_aal0@14005000 {
+ compatible = "mediatek,mt8195-mdp3-aal";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x14005000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x5000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_AAL>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-color.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-color.yaml
new file mode 100644
index 000000000000..4eba4505ed26
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-color.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-color.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 COLOR Device Tree Bindings
+
+maintainers:
+ - Daoyuan Huang <daoyuan.huang@mediatek.com>
+ - Moudy Ho <moudy.ho@mediatek.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to adjust hue, luma and saturation
+ to get better picture quality.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - mediatek,mt8195-mdp3-color
+
+ mediatek,mdp3-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
+ description: |
+ HW index to distinguish same functionality modules.
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - mediatek,mdp3-id
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ mdp3_color0: mdp_color0@14008000 {
+ compatible = "mediatek,mt8195-mdp3-color";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x14008000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x8000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml
new file mode 100644
index 000000000000..8a4ea694c44b
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-fg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 FG Device Tree Bindings
+
+maintainers:
+ - Daoyuan Huang <daoyuan.huang@mediatek.com>
+ - Moudy Ho <moudy.ho@mediatek.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to add film grain according to AV1 spec.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt8195-mdp3-fg
+
+ mediatek,mdp3-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
+ description: |
+ HW index to distinguish same functionality modules.
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - mediatek,mdp3-id
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ mdp3_fg0: mdp_fg0@14002000 {
+ compatible = "mediatek,mt8195-mdp3-fg";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x14002000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x2000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_FG>;
+ };
\ No newline at end of file
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml
new file mode 100644
index 000000000000..4330f2b79697
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-hdr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 HDR Device Tree Bindings
+
+maintainers:
+ - Daoyuan Huang <daoyuan.huang@mediatek.com>
+ - Moudy Ho <moudy.ho@mediatek.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to perform HDR to SDR
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt8195-mdp3-hdr
+
+ mediatek,mdp3-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
+ description: |
+ HW index to distinguish same functionality modules.
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - mediatek,mdp3-id
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ mdp3_hdr0: mdp_hdr0@14004000
+ compatible = "mediatek,mt8195-mdp3-hdr";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x14004000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x4000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_HDR>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-merge.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-merge.yaml
new file mode 100644
index 000000000000..1e48a4636588
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-merge.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-merge.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 MERGE Device Tree Bindings
+
+maintainers:
+ - Daoyuan Huang <daoyuan.huang@mediatek.com>
+ - Moudy Ho <moudy.ho@mediatek.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to merge
+ two slice-per-line inputs into one side-by-side output.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - mediatek,mt8195-mdp3-merge
+
+ mediatek,mdp3-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
+ description: |
+ HW index to distinguish same functionality modules.
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - mediatek,mdp3-id
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ svpp2_mdp3_merge: svpp2_mdp_merge@14f1a000 {
+ compatible = "mediatek,mt8195-mdp3-merge";
+ mediatek,mdp3-id = <2>;
+ reg = <0 0x14f1a000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_14f1XXXX 0xa000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-ovl.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-ovl.yaml
new file mode 100644
index 000000000000..4e503d79758b
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-ovl.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-ovl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 OVL Device Tree Bindings
+
+maintainers:
+ - Daoyuan Huang <daoyuan.huang@mediatek.com>
+ - Moudy Ho <moudy.ho@mediatek.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to perform alpha blending from the memory.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - mediatek,mt8195-mdp3-ovl
+
+ mediatek,mdp3-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
+ description: |
+ HW index to distinguish same functionality modules.
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - mediatek,mdp3-id
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ mdp3_ovl0: mdp_ovl0@14009000 {
+ compatible = "mediatek,mt8195-mdp3-ovl";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x14009000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x9000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_OVL>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-pad.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-pad.yaml
new file mode 100644
index 000000000000..1f990c5ce6ab
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-pad.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-pad.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 PADDING Device Tree Bindings
+
+maintainers:
+ - Daoyuan Huang <daoyuan.huang@mediatek.com>
+ - Moudy Ho <moudy.ho@mediatek.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to insert
+ pre-defined color or alpha value to arbitrary side of image.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - mediatek,mt8195-mdp3-pad
+
+ mediatek,mdp3-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
+ description: |
+ HW index to distinguish same functionality modules.
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - mediatek,mdp3-id
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ mdp3_pad0: mdp_pad0@1400a000 {
+ compatible = "mediatek,mt8195-mdp3-pad";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x1400a000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0xa000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_PADDING>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
index b355d7fe791e..ce023d9fbef7 100644
--- a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
@@ -20,14 +20,16 @@ properties:
oneOf:
- items:
- enum:
- # controller node
- mediatek,mt8183-mdp3
+ - mediatek,mt8195-mdp3
- enum:
- mediatek,mt8183-mdp3-rdma
- items:
- - enum:
# read DMA
+ - enum:
+ - mediatek,mt8195-mdp3-rdma
+ - enum:
- mediatek,mt8183-mdp3-rdma
mediatek,scp:
@@ -55,12 +57,28 @@ properties:
- mediatek,mt8183-mdp3-dl1
- enum:
- mediatek,mt8183-mdp3-dl2
+ - enum:
+ - mediatek,mt8195-mdp3-dl1
+ - enum:
+ - mediatek,mt8195-mdp3-dl2
+ - enum:
+ - mediatek,mt8195-mdp3-dl3
+ - enum:
+ - mediatek,mt8195-mdp3-dl4
+ - enum:
+ - mediatek,mt8195-mdp3-dl5
+ - enum:
+ - mediatek,mt8195-mdp3-dl6
- enum:
# MDP direct-link output path selection, create a
# component for path connectedness of HW pipe control
- mediatek,mt8183-mdp3-path1
- enum:
- mediatek,mt8183-mdp3-path2
+ - enum:
+ - mediatek,mt8195-mdp3-path1
+ - enum:
+ - mediatek,mt8195-mdp3-path2
- enum:
# Input DMA of ISP PASS2 (DIP) module for raw image input
- mediatek,mt8183-mdp3-imgi
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
index c55a52cd32b7..eaa487ec58cc 100644
--- a/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
@@ -16,6 +16,8 @@ description: |
properties:
compatible:
items:
+ - enum:
+ - mediatek,mt8195-mdp3-rsz
- enum:
- mediatek,mt8183-mdp3-rsz
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-split.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-split.yaml
new file mode 100644
index 000000000000..40827d577f74
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-split.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-solit.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 SPLIT Device Tree Bindings
+
+maintainers:
+ - Daoyuan Huang <daoyuan.huang@mediatek.com>
+ - Moudy Ho <moudy.ho@mediatek.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to split hdmi rx into two stream
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - mediatek,mt8195-mdp3-split
+
+ mediatek,mdp3-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
+ description: |
+ HW index to distinguish same functionality modules.
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - mediatek,mdp3-id
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ vpp_split0: vpp_split0@14f06000 {
+ compatible = "mediatek,mt8195-mdp3-split";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x14f06000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_14f0XXXX 0x6000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_VPP_SPLIT>,
+ <&vppsys1 CLK_VPP1_HDMI_META>,
+ <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>,
+ <&vppsys1 CLK_VPP1_DGI_IN>,
+ <&vppsys1 CLK_VPP1_DGI_OUT>,
+ <&vppsys1 CLK_VPP1_VPP_SPLIT_DGI>,
+ <&vppsys1 CLK_VPP1_VPP_SPLIT_26M>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml
new file mode 100644
index 000000000000..038a9519b2de
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-stitch.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 STITCH Device Tree Bindings
+
+maintainers:
+ - Daoyuan Huang <daoyuan.huang@mediatek.com>
+ - Moudy Ho <moudy.ho@mediatek.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to combine multiple video frame
+ with overlapping fields of view to produce a segmented panorame.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt8195-mdp3-stitch
+
+ mediatek,mdp3-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
+ description: |
+ HW index to distinguish same functionality modules.
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - mediatek,mdp3-id
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ mdp3_stitch0: mdp_stich0@14003000 {
+ compatible = "mediatek,mt8195-mdp3-stitch";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x14003000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x3000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_STITCH>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml
new file mode 100644
index 000000000000..63c147cb8d24
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-tcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 TCC Device Tree Bindings
+
+maintainers:
+ - Daoyuan Huang <daoyuan.huang@mediatek.com>
+ - Moudy Ho <moudy.ho@mediatek.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to support
+ HDR gamma curve conversion HDR displays.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - mediatek,mt8195-mdp3-tcc
+
+ mediatek,mdp3-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
+ description: |
+ HW index to distinguish same functionality modules.
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - mediatek,mdp3-id
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ mdp3_tcc0: mdp_tcc0@1400b000 {
+ compatible = "mediatek,mt8195-mdp3-tcc";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x1400b000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0xb000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_TCC>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml
new file mode 100644
index 000000000000..25b4668d93fc
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-tdshp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 TDSHP Device Tree Bindings
+
+maintainers:
+ - Daoyuan Huang <daoyuan.huang@mediatek.com>
+ - Moudy Ho <moudy.ho@mediatek.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to improve image sharpness and contrast.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt8195-mdp3-tdshp
+
+ mediatek,mdp3-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
+ description: |
+ HW index to distinguish same functionality modules.
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - mediatek,mdp3-id
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ mdp3_tdshp0: mdp_tdshp0@14007000 {
+ compatible = "mediatek,mt8195-mdp3-tdshp";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x14007000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x7000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
index 2993da04c562..885e0f0f9e1f 100644
--- a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
@@ -16,6 +16,8 @@ description: |
properties:
compatible:
items:
+ - enum:
+ - mediatek,mt8195-mdp3-wrot
- enum:
- mediatek,mt8183-mdp3-wrot
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v1 5/9] arm64: dts: mt8195: add mdp3 node
2021-09-17 2:51 [PATCH v1 1/9] soc: mediatek: mmsys: expand MDP enum for chip independence architecture roy-cw.yeh
` (2 preceding siblings ...)
2021-09-17 2:51 ` [PATCH v1 4/9] dt-bindings: media: mediatek: mdp3: add additional function block yaml roy-cw.yeh
@ 2021-09-17 2:51 ` roy-cw.yeh
2021-09-17 2:51 ` [PATCH v1 6/9] soc: mediatek: mmsys: support mt8195 vppsys0/1 roy-cw.yeh
` (2 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: roy-cw.yeh @ 2021-09-17 2:51 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, Roy-CW . Yeh,
jason-jh . lin, daoyuan huang, Ping-Hsun Wu, Moudy Ho,
Enric Balletbo i Serra, Yongqiang Niu, devicetree, linux-kernel,
linux-media, linux-arm-kernel, linux-mediatek
From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
Add mdp3 node.
Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 672 ++++++++++++++++++++++-
1 file changed, 669 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 3a44955350ae..727b78535605 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1002,9 +1002,245 @@
vppsys0: syscon@14000000 {
compatible = "mediatek,mt8195-vppsys0", "syscon";
reg = <0 0x14000000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0 0x1000>;
#clock-cells = <1>;
};
+ mdp3_rdma0: mdp_rdma0@14001000 {
+ compatible = "mediatek,mt8195-mdp3",
+ "mediatek,mt8183-mdp3-rdma";
+ mediatek,scp = <&scp>;
+ mediatek,mdp3-id = <0>;
+ mdp3-comps = "mediatek,mt8195-mdp3-path1", "mediatek,mt8195-mdp3-path2",
+ "mediatek,mt8195-mdp3-dl1", "mediatek,mt8195-mdp3-dl2",
+ "mediatek,mt8195-mdp3-dl3", "mediatek,mt8195-mdp3-dl4",
+ "mediatek,mt8195-mdp3-dl5", "mediatek,mt8195-mdp3-dl6";
+ mdp3-comp-ids = <0 1 0 1 0 0 0 0>;
+ reg = <0 0x14001000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x1000 0x1000>;
+ interrupts = <GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>,
+ <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L4_MDP_RDMA>,
+ <&iommu_vpp M4U_PORT_L4_MDP_WROT>,
+ <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_RDMA>,
+ <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_WROT>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>,
+ <&topckgen CLK_TOP_CFG_VPP0>,
+ <&topckgen CLK_TOP_CFG_26M_VPP0>,
+ <&vppsys0 CLK_VPP0_WARP0_ASYNC_TX>,
+ <&vppsys0 CLK_VPP0_WARP0_RELAY>,
+ <&vppsys0 CLK_VPP0_WARP0_MDP_DL_ASYNC>,
+ <&vppsys0 CLK_VPP0_WARP1_ASYNC_TX>,
+ <&vppsys0 CLK_VPP0_WARP1_RELAY>,
+ <&vppsys0 CLK_VPP0_WARP1_MDP_DL_ASYNC>,
+ <&vppsys0 CLK_VPP0_VPP02VPP1_RELAY>,
+ <&vppsys1 CLK_VPP1_DL_ASYNC>,
+ <&vppsys1 CLK_VPP1_VPP0_DL_ASYNC>,
+ <&vppsys1 CLK_VPP1_VPP0_DL_RELAY>,
+ <&vppsys0 CLK_VPP0_VPP12VPP0_ASYNC>,
+ <&vppsys1 CLK_VPP1_VPP0_DL1_RELAY>,
+ <&vppsys1 CLK_VPP1_SVPP2_VDO0_DL_RELAY>,
+ <&vppsys1 CLK_VPP1_SVPP3_VDO1_DL_RELAY>,
+ <&vppsys1 CLK_VPP1_SVPP2_VDO1_DL_RELAY>,
+ <&vppsys1 CLK_VPP1_SVPP3_VDO0_DL_RELAY>;
+ clock-names = "MDP_RDMA0",
+ "TOP_CFG_VPP0",
+ "TOP_CFG_26M_VPP0",
+ "WARP0_ASYNC_TX",
+ "WARP0_RELAY",
+ "WARP0_MDP_DL_ASYNC",
+ "WARP1_ASYNC_TX",
+ "WARP1_RELAY",
+ "WARP1_MDP_DL_ASYNC",
+ "VPP02VPP1_RELAY",
+ "VPP0_DL_ASYNC_VPP1",
+ "VPP0_DL_ASYNC_VPP0",
+ "VPP0_DL_RELAY",
+ "VPP12VPP0_ASYNC",
+ "VPP0_DL1_RELAY",
+ "SVPP2_VDO0_DL_RELAY",
+ "SVPP3_VDO1_DL_RELAY",
+ "SVPP2_VDO1_DL_RELAY",
+ "SVPP3_VDO0_DL_RELAY";
+ mediatek,mmsys2 = <&vppsys1>;
+ mediatek,mm-mutex2 = <&vpp1_mutex>;
+ mediatek,mmsys = <&vppsys0>;
+ mediatek,mm-mutex = <&vpp0_mutex>;
+ mboxes =
+ <&gce0 12 CMDQ_THR_PRIO_1>,
+ <&gce0 13 CMDQ_THR_PRIO_1>,
+ <&gce0 14 CMDQ_THR_PRIO_1>,
+ <&gce0 21 CMDQ_THR_PRIO_1>,
+ <&gce0 22 CMDQ_THR_PRIO_1>;
+ mdp3-rdma0 = <&mdp3_rdma0>;
+ mdp3-rdma1 = <&svpp1_mdp3_rdma>;
+ mdp3-rdma2 = <&svpp2_mdp3_rdma>;
+ mdp3-rdma3 = <&svpp3_mdp3_rdma>;
+ mdp3-stitch = <&mdp3_stitch0>;
+ mdp3-rsz0 = <&mdp3_rsz0>;
+ mdp3-rsz1 = <&svpp1_mdp3_rsz>;
+ mdp3-rsz2 = <&svpp2_mdp3_rsz>;
+ mdp3-rsz3 = <&svpp3_mdp3_rsz>;
+ mdp3-wrot0 = <&mdp3_wrot0>;
+ mdp3-wrot1 = <&svpp1_mdp3_wrot>;
+ mdp3-wrot2 = <&svpp2_mdp3_wrot>;
+ mdp3-wrot3 = <&svpp3_mdp3_wrot>;
+ mdp3-tdshp0 = <&mdp3_tdshp0>;
+ mdp3-tdshp1 = <&svpp1_mdp3_tdshp>;
+ mdp3-tdshp2 = <&svpp2_mdp3_tdshp>;
+ mdp3-tdshp3 = <&svpp3_mdp3_tdshp>;
+ mdp3-aal0 = <&mdp3_aal0>;
+ mdp3-aal1 = <&svpp1_mdp3_aal>;
+ mdp3-aal2 = <&svpp2_mdp3_aal>;
+ mdp3-aal3 = <&svpp3_mdp3_aal>;
+ mdp3-color0 = <&mdp3_color0>;
+ mdp3-color1 = <&svpp1_mdp3_color>;
+ mdp3-color2 = <&svpp2_mdp3_color>;
+ mdp3-color3 = <&svpp3_mdp3_color>;
+ mdp3-hdr0 = <&mdp3_hdr0>;
+ mdp3-hdr1 = <&svpp1_mdp3_hdr>;
+ mdp3-hdr2 = <&svpp2_mdp3_hdr>;
+ mdp3-hdr3 = <&svpp3_mdp3_hdr>;
+ mdp3-fg0 = <&mdp3_fg0>;
+ mdp3-fg1 = <&svpp1_mdp3_fg>;
+ mdp3-fg2 = <&svpp2_mdp3_fg>;
+ mdp3-fg3 = <&svpp3_mdp3_fg>;
+ mdp3-tcc0 = <&mdp3_tcc0>;
+ mdp3-tcc1 = <&svpp1_mdp3_tcc>;
+ mdp3-ovl0 = <&mdp3_ovl0>;
+ mdp3-ovl1 = <&svpp1_mdp3_ovl>;
+ mdp3-pad0 = <&mdp3_pad0>;
+ mdp3-pad1 = <&svpp1_mdp3_pad>;
+ mdp3-pad2 = <&svpp2_mdp3_pad>;
+ mdp3-pad3 = <&svpp3_mdp3_pad>;
+ mdp3-split = <&vpp_split0>;
+ mdp3-merge2 = <&svpp2_mdp3_merge>;
+ mdp3-merge3 = <&svpp3_mdp3_merge>;
+ };
+
+ mdp3_fg0: mdp_fg0@14002000 {
+ compatible = "mediatek,mt8195-mdp3-fg";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x14002000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x2000 0x1000>;
+ interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_FG>;
+ clock-names = "MDP_FG0";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ mdp3_stitch0: mdp_stich0@14003000 {
+ compatible = "mediatek,mt8195-mdp3-stitch";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x14003000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x3000 0x1000>;
+ interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys0 CLK_VPP0_STITCH>;
+ clock-names = "MDP_STITCH";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ mdp3_hdr0: mdp_hdr0@14004000 {
+ compatible = "mediatek,mt8195-mdp3-hdr";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x14004000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x4000 0x1000>;
+ interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_HDR>;
+ clock-names = "MDP_HDR0";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ mdp3_aal0: mdp_aal0@14005000 {
+ compatible = "mediatek,mt8195-mdp3-aal";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x14005000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x5000 0x1000>;
+ interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_AAL>;
+ clock-names = "MDP_AAL0";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ mdp3_rsz0: mdp_rsz0@14006000 {
+ compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x14006000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x6000 0x1000>;
+ interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_RSZ>;
+ clock-names = "MDP_RSZ0";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ mdp3_tdshp0: mdp_tdshp0@14007000 {
+ compatible = "mediatek,mt8195-mdp3-tdshp";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x14007000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x7000 0x1000>;
+ interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>;
+ clock-names = "MDP_TDSHP0";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ mdp3_color0: mdp_color0@14008000 {
+ compatible = "mediatek,mt8195-mdp3-color";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x14008000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x8000 0x1000>;
+ interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>;
+ clock-names = "MDP_COLOR0";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ mdp3_ovl0: mdp_ovl0@14009000 {
+ compatible = "mediatek,mt8195-mdp3-ovl";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x14009000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x9000 0x1000>;
+ interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_OVL>;
+ clock-names = "MDP_OVL0";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ mdp3_pad0: mdp_pad0@1400a000 {
+ compatible = "mediatek,mt8195-mdp3-pad";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x1400a000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0xa000 0x1000>;
+ interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys0 CLK_VPP0_PADDING>;
+ clock-names = "MDP_PAD0";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ mdp3_tcc0: mdp_tcc0@1400b000 {
+ compatible = "mediatek,mt8195-mdp3-tcc";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x1400b000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0xb000 0x1000>;
+ interrupts = <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_TCC>;
+ clock-names = "MDP_TCC0";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ mdp3_wrot0: mdp_wrot0@1400c000 {
+ compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x1400c000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0xc000 0x1000>;
+ interrupts = <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_WROT>;
+ clock-names = "MDP_WROT0";
+ iommus = <&iommu_vpp M4U_PORT_L4_MDP_WROT>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
smi_common2: smi@1400e000 {
compatible = "mediatek,mt8195-smi-common";
mediatek,common-id = <2>;
@@ -1017,6 +1253,34 @@
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
};
+ vpp0_mutex: vpp0_mutex@1400f000 {
+ compatible = "mediatek,mt8195-vpp0-mutex";
+ reg = <0 0x1400f000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0xf000 0x1000>;
+ interrupts = <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>;
+ #clocks = <&vppsys0 CLK_VPP0_MUTEX>;
+ #clock-names = "MDP_MUTEX0";
+ clocks = <&vppsys0 CLK_VPP0_MUTEX>;
+ clock-names = "MDP_MUTEX0";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>,
+ <CMDQ_EVENT_VPP0_MDP_WROT_SOF>,
+ <CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE>,
+ <CMDQ_EVENT_VPP0_MDP_WROT_VIDO_WDONE>,
+ <CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF>,
+ <CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_FRAME_DONE>,
+ <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_FRAME_DONE>,
+ <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_FRAME_DONE>,
+ <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_FRAME_DONE>,
+ <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_FRAME_DONE>,
+ <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_FRAME_DONE>;
+ };
+
smi_common1: smi@14012000 {
compatible = "mediatek,mt8195-smi-common";
mediatek,common-id = <1>;
@@ -1098,9 +1362,22 @@
vppsys1: syscon@14f00000 {
compatible = "mediatek,mt8195-vppsys1", "syscon";
reg = <0 0x14f00000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_14f0XXXX 0 0x1000>;
#clock-cells = <1>;
};
+ vpp1_mutex: vpp1_mutex@14f01000 {
+ compatible = "mediatek,mt8195-vpp1-mutex";
+ reg = <0 0x14f01000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_14f0XXXX 0x1000 0x1000>;
+ interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>;
+ #clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>;
+ #clock-names = "DISP_MUTEX";
+ clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>;
+ clock-names = "DISP_MUTEX";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
larb5: larb@14f02000 {
compatible = "mediatek,mt8195-smi-larb";
reg = <0 0x14f02000 0 0x1000>;
@@ -1125,7 +1402,396 @@
clock-names = "apb", "smi", "gals", "gals1";
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
};
-
+
+ vpp_split0: vpp_split0@14f06000 {
+ compatible = "mediatek,mt8195-mdp3-split";
+ mediatek,mdp3-id = <1>;
+ reg = <0 0x14f06000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_14f0XXXX 0x6000 0x1000>;
+ interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_VPP_SPLIT>,
+ <&vppsys1 CLK_VPP1_HDMI_META>,
+ <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>,
+ <&vppsys1 CLK_VPP1_DGI_IN>,
+ <&vppsys1 CLK_VPP1_DGI_OUT>,
+ <&vppsys1 CLK_VPP1_VPP_SPLIT_DGI>,
+ <&vppsys1 CLK_VPP1_VPP_SPLIT_26M>;
+ clock-names = "MDP_SPLIT",
+ "HDMI_META",
+ "SPLIT_HDMI",
+ "DGI_IN",
+ "DGI_OUT",
+ "SPLIT_DGI",
+ "VPP_SPLIT_26M";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp1_mdp3_tcc: svpp1_mdp_tcc@14f07000 {
+ compatible = "mediatek,mt8195-mdp3-tcc";
+ mediatek,mdp3-id = <1>;
+ reg = <0 0x14f07000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_14f0XXXX 0x7000 0x1000>;
+ interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TCC>;
+ clock-names = "MDP_TCC1";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp1_mdp3_rdma: svpp1_mdp_rdma@14f08000 {
+ compatible = "mediatek,mt8195-mdp3",
+ "mediatek,mt8183-mdp3-rdma";
+ mediatek,mdp3-id = <1>;
+ reg = <0 0x14f08000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_14f0XXXX 0x8000 0x1000>;
+ interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RDMA>,
+ <&topckgen CLK_TOP_CFG_VPP1>,
+ <&topckgen CLK_TOP_CFG_26M_VPP1>;
+ clock-names = "MDP_RDMA1",
+ "TOP_CFG_VPP1",
+ "TOP_CFG_26M_VPP1";
+ iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_RDMA>,
+ <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_RDMA>,
+ <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_WROT>,
+ <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_WROT>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp2_mdp3_rdma: svpp2_mdp_rdma@14f09000 {
+ compatible = "mediatek,mt8195-mdp3-rdma", "mediatek,mt8183-mdp3-rdma";
+ mediatek,mdp3-id = <2>;
+ reg = <0 0x14f09000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_14f0XXXX 0x9000 0x1000>;
+ interrupts = <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RDMA>,
+ <&topckgen CLK_TOP_CFG_VPP1>,
+ <&topckgen CLK_TOP_CFG_26M_VPP1>;
+ clock-names = "MDP_RDMA2",
+ "TOP_CFG_VPP1",
+ "TOP_CFG_26M_VPP1";
+ iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_RDMA>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp3_mdp3_rdma: svpp3_mdp_rdma@14f0a000 {
+ compatible = "mediatek,mt8195-mdp3-rdma", "mediatek,mt8183-mdp3-rdma";
+ mediatek,mdp3-id = <3>;
+ reg = <0 0x14f0a000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_14f0XXXX 0xa000 0x1000>;
+ interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RDMA>,
+ <&topckgen CLK_TOP_CFG_VPP1>,
+ <&topckgen CLK_TOP_CFG_26M_VPP1>;
+ clock-names = "MDP_RDMA3",
+ "TOP_CFG_VPP1",
+ "TOP_CFG_26M_VPP1";
+ iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_RDMA>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp1_mdp3_fg: svpp1_mdp_fg@14f0b000 {
+ compatible = "mediatek,mt8195-mdp3-fg";
+ mediatek,mdp3-id = <1>;
+ reg = <0 0x14f0b000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_14f0XXXX 0xb000 0x1000>;
+ interrupts = <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_FG>;
+ clock-names = "MDP_FG1";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp2_mdp3_fg: svpp2_mdp_fg@14f0c000 {
+ compatible = "mediatek,mt8195-mdp3-fg";
+ mediatek,mdp3-id = <2>;
+ reg = <0 0x14f0c000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_14f0XXXX 0xc000 0x1000>;
+ interrupts = <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_FG>;
+ clock-names = "MDP_FG2";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp3_mdp3_fg: svpp3_mdp_fg@14f0d000 {
+ compatible = "mediatek,mt8195-mdp3-fg";
+ mediatek,mdp3-id = <3>;
+ reg = <0 0x14f0d000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_14f0XXXX 0xd000 0x1000>;
+ interrupts = <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_FG>;
+ clock-names = "MDP_FG3";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp1_mdp3_hdr: svpp1_mdp_hdr@14f0e000 {
+ compatible = "mediatek,mt8195-mdp3-hdr";
+ mediatek,mdp3-id = <1>;
+ reg = <0 0x14f0e000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_14f0XXXX 0xe000 0x1000>;
+ interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_HDR>;
+ clock-names = "MDP_HDR1";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp2_mdp3_hdr: svpp2_mdp_hdr@14f0f000 {
+ compatible = "mediatek,mt8195-mdp3-hdr";
+ mediatek,mdp3-id = <2>;
+ reg = <0 0x14f0f000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_14f0XXXX 0xf000 0x1000>;
+ interrupts = <GIC_SPI 615 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_HDR>;
+ clock-names = "MDP_HDR2";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp3_mdp3_hdr: svpp3_mdp_hdr@14f10000 {
+ compatible = "mediatek,mt8195-mdp3-hdr";
+ mediatek,mdp3-id = <3>;
+ reg = <0 0x14f10000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_14f1XXXX 0 0x1000>;
+ interrupts = <GIC_SPI 616 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_HDR>;
+ clock-names = "MDP_HDR3";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp1_mdp3_aal: svpp1_mdp_aal@14f11000 {
+ compatible = "mediatek,mt8195-mdp3-aal";
+ mediatek,mdp3-id = <1>;
+ reg = <0 0x14f11000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_14f1XXXX 0x1000 0x1000>;
+ interrupts = <GIC_SPI 617 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_AAL>;
+ clock-names = "MDP_AAL1";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp2_mdp3_aal: svpp2_mdp_aal@14f12000 {
+ compatible = "mediatek,mt8195-mdp3-aal";
+ mediatek,mdp3-id = <2>;
+ reg = <0 0x14f12000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_14f1XXXX 0x2000 0x1000>;
+ interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_AAL>;
+ clock-names = "MDP_AAL2";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp3_mdp3_aal: svpp3_mdp_aal@14f13000 {
+ compatible = "mediatek,mt8195-mdp3-aal";
+ mediatek,mdp3-id = <3>;
+ reg = <0 0x14f13000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_14f1XXXX 0x3000 0x1000>;
+ interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_AAL>;
+ clock-names = "MDP_AAL3";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp1_mdp3_rsz: svpp1_mdp_rsz@14f14000 {
+ compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
+ mediatek,mdp3-id = <1>;
+ reg = <0 0x14f14000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_14f1XXXX 0x4000 0x1000>;
+ interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RSZ>;
+ clock-names = "MDP_RSZ1";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp2_mdp3_rsz: svpp2_mdp_rsz@14f15000 {
+ compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
+ mediatek,mdp3-id = <2>;
+ reg = <0 0x14f15000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_14f1XXXX 0x5000 0x1000>;
+ interrupts = <GIC_SPI 621 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>,
+ <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>;
+ clock-names = "MDP_RSZ2";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp3_mdp3_rsz: svpp3_mdp_rsz@14f16000 {
+ compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz";
+ mediatek,mdp3-id = <3>;
+ reg = <0 0x14f16000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_14f1XXXX 0x6000 0x1000>;
+ interrupts = <GIC_SPI 622 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>,
+ <&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>;
+ clock-names = "MDP_RSZ3";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp1_mdp3_tdshp: svpp1_mdp_tdshp@14f17000 {
+ compatible = "mediatek,mt8195-mdp3-tdshp";
+ mediatek,mdp3-id = <1>;
+ reg = <0 0x14f17000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_14f1XXXX 0x7000 0x1000>;
+ interrupts = <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TDSHP>;
+ clock-names = "MDP_TDSHP1";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp2_mdp3_tdshp: svpp2_mdp_tdshp@14f18000 {
+ compatible = "mediatek,mt8195-mdp3-tdshp";
+ mediatek,mdp3-id = <2>;
+ reg = <0 0x14f18000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_14f1XXXX 0x8000 0x1000>;
+ interrupts = <GIC_SPI 624 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_TDSHP>;
+ clock-names = "MDP_TDSHP2";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp3_mdp3_tdshp: svpp3_mdp_tdshp@14f19000 {
+ compatible = "mediatek,mt8195-mdp3-tdshp";
+ mediatek,mdp3-id = <3>;
+ reg = <0 0x14f19000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_14f1XXXX 0x9000 0x1000>;
+ interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_TDSHP>;
+ clock-names = "MDP_TDSHP3";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp2_mdp3_merge: svpp2_mdp_merge@14f1a000 {
+ compatible = "mediatek,mt8195-mdp3-merge";
+ mediatek,mdp3-id = <2>;
+ reg = <0 0x14f1a000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_14f1XXXX 0xa000 0x1000>;
+ interrupts = <GIC_SPI 626 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>;
+ clock-names = "MDP_MERGE2";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp3_mdp3_merge: svpp3_mdp_merge@14f1b000 {
+ compatible = "mediatek,mt8195-mdp3-merge";
+ mediatek,mdp3-id = <3>;
+ reg = <0 0x14f1b000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_14f1XXXX 0xb000 0x1000>;
+ interrupts = <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>;
+ clock-names = "MDP_MERGE3";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp1_mdp3_color: svpp1_mdp_color@14f1c000 {
+ compatible = "mediatek,mt8195-mdp3-color";
+ mediatek,mdp3-id = <1>;
+ reg = <0 0x14f1c000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_14f1XXXX 0xc000 0x1000>;
+ interrupts = <GIC_SPI 628 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_COLOR>;
+ clock-names = "MDP_COLOR1";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp2_mdp3_color: svpp2_mdp_color@14f1d000 {
+ compatible = "mediatek,mt8195-mdp3-color";
+ mediatek,mdp3-id = <2>;
+ reg = <0 0x14f1d000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_14f1XXXX 0xd000 0x1000>;
+ interrupts = <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_COLOR>;
+ clock-names = "MDP_COLOR2";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp3_mdp3_color: svpp3_mdp_color@14f1e000 {
+ compatible = "mediatek,mt8195-mdp3-color";
+ mediatek,mdp3-id = <3>;
+ reg = <0 0x14f1e000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_14f1XXXX 0xe000 0x1000>;
+ interrupts = <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_COLOR>;
+ clock-names = "MDP_COLOR3";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp1_mdp3_ovl: svpp1_mdp_ovl@14f1f000 {
+ compatible = "mediatek,mt8195-mdp3-ovl";
+ mediatek,mdp3-id = <1>;
+ reg = <0 0x14f1f000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_14f1XXXX 0xf000 0x1000>;
+ interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_OVL>;
+ clock-names = "MDP_OVL1";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp1_mdp3_pad: svpp1_mdp_pad@14f20000 {
+ compatible = "mediatek,mt8195-mdp3-pad";
+ mediatek,mdp3-id = <1>;
+ reg = <0 0x14f20000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_14f2XXXX 0 0x1000>;
+ interrupts = <GIC_SPI 632 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_VPP_PAD>;
+ clock-names = "MDP_PAD1";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp2_mdp3_pad: svpp2_mdp_pad@14f21000 {
+ compatible = "mediatek,mt8195-mdp3-pad";
+ mediatek,mdp3-id = <2>;
+ reg = <0 0x14f21000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_14f2XXXX 0x1000 0x1000>;
+ interrupts = <GIC_SPI 633 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_PAD>;
+ clock-names = "MDP_PAD2";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp3_mdp3_pad: svpp3_mdp_pad@14f22000 {
+ compatible = "mediatek,mt8195-mdp3-pad";
+ mediatek,mdp3-id = <3>;
+ reg = <0 0x14f22000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_14f2XXXX 0x2000 0x1000>;
+ interrupts = <GIC_SPI 634 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_PAD>;
+ clock-names = "MDP_PAD3";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp1_mdp3_wrot: svpp1_mdp_wrot@14f23000 {
+ compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
+ mediatek,mdp3-id = <1>;
+ reg = <0 0x14f23000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_14f2XXXX 0x3000 0x1000>;
+ interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_WROT>;
+ clock-names = "MDP_WROT1";
+ iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_WROT>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp2_mdp3_wrot: svpp2_mdp_wrot@14f24000 {
+ compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
+ mediatek,mdp3-id = <2>;
+ reg = <0 0x14f24000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_14f2XXXX 0x4000 0x1000>;
+ interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_WROT>;
+ clock-names = "MDP_WROT2";
+ iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_WROT>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ svpp3_mdp3_wrot: svpp3_mdp_wrot@14f25000 {
+ compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot";
+ mediatek,mdp3-id = <3>;
+ reg = <0 0x14f25000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_14f2XXXX 0x5000 0x1000>;
+ interrupts = <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_WROT>;
+ clock-names = "MDP_WROT3";
+ iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_WROT>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
imgsys: syscon@15000000 {
compatible = "mediatek,mt8195-imgsys", "syscon";
reg = <0 0x15000000 0 0x1000>;
@@ -1557,7 +2223,7 @@
reg = <0 0x1c100000 0 0x1000>;
#clock-cells = <1>;
};
-
+
larb2: larb@1c102000 {
compatible = "mediatek,mt8195-smi-larb";
reg = <0 0x1c102000 0 0x1000>;
@@ -1580,7 +2246,7 @@
<&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
clock-names = "apb", "smi", "gals";
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
- };
+ };
};
bring-up {
--
2.18.0
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v1 6/9] soc: mediatek: mmsys: support mt8195 vppsys0/1
2021-09-17 2:51 [PATCH v1 1/9] soc: mediatek: mmsys: expand MDP enum for chip independence architecture roy-cw.yeh
` (3 preceding siblings ...)
2021-09-17 2:51 ` [PATCH v1 5/9] arm64: dts: mt8195: add mdp3 node roy-cw.yeh
@ 2021-09-17 2:51 ` roy-cw.yeh
2021-09-17 2:51 ` [PATCH v1 7/9] soc: mediatek: mutex: " roy-cw.yeh
2021-09-17 2:51 ` [PATCH v1 9/9] media: platform: mtk-mdp3: Add dual pipe feature support roy-cw.yeh
6 siblings, 0 replies; 9+ messages in thread
From: roy-cw.yeh @ 2021-09-17 2:51 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, Roy-CW . Yeh,
jason-jh . lin, daoyuan huang, Ping-Hsun Wu, Moudy Ho,
Enric Balletbo i Serra, Yongqiang Niu, devicetree, linux-kernel,
linux-media, linux-arm-kernel, linux-mediatek
From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
Add mt8195 vppsys clock driver name and routing table to
the driver data of mtk-mmsys.
Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
drivers/soc/mediatek/mt8195-mmsys.h | 716 +++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 42 ++
drivers/soc/mediatek/mtk-mmsys.h | 3 +
include/linux/soc/mediatek/mtk-mmsys.h | 4 +
4 files changed, 765 insertions(+)
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index 0c97a5f016c1..8f843275ba34 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -111,4 +111,720 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
}
};
+/* VPPSYS0 MOUT */
+#define MT8195_VPPSYS0_STITCH_MOUT_EN 0xF38
+ #define MT8195_VPPSYS0_STITCH_MOUT_TO_PQ_SEL_IN BIT(0)
+ #define MT8195_VPPSYS0_STITCH_MOUT_TO_VPP1_SEL_IN BIT(1)
+#define MT8195_VPPSYS0_WARP0_MOUT_EN 0xF3C
+ #define MT8195_VPPSYS0_WARP0_MOUT_TO_PQ_SEL_IN BIT(0)
+ #define MT8195_VPPSYS0_WARP0_MOUT_TO_VPP1_SEL_IN BIT(1)
+#define MT8195_VPPSYS0_WARP1_MOUT_EN 0xF40
+ #define MT8195_VPPSYS0_WARP1_MOUT_TO_PQ_SEL_IN BIT(0)
+ #define MT8195_VPPSYS0_WARP1_MOUT_TO_VPP1_SEL_IN BIT(1)
+#define MT8195_VPPSYS0_FG_MOUT_EN 0xF44
+ #define MT8195_VPPSYS0_FG_MOUT_TO_PQ_SEL_IN BIT(0)
+ #define MT8195_VPPSYS0_FG_MOUT_TO_VPP1_SEL_IN BIT(1)
+
+/* VPPSYS1 MOUT */
+#define MT8195_SVPP2_SRC_SEL_MOUT_EN 0xF50
+ #define MT8195_SVPP2_MDP_HDR BIT(0)
+ #define MT8195_SVPP1_HDR_SRC_SEL BIT(1)
+#define MT8195_SVPP3_SRC_SEL_MOUT_EN 0xF7C
+ #define MT8195_SVPP3_MDP_HDR BIT(0)
+ #define MT8195_VPP0_DL1_SRC_SEL BIT(1)
+#define MT8195_SVPP2_MDP_HDR_MOUT_EN 0xF4C
+ #define MT8195_SVPP2_MDP_AAL BIT(0)
+ #define MT8195_SVPP1_MDP_AAL_SEL BIT(1)
+#define MT8195_SVPP3_MDP_HDR_MOUT_EN 0xF78
+ #define MT8195_SVPP3_MDP_AAL BIT(0)
+
+/* VPPSYS0 SEL_IN */
+#define MT8195_VPPSYS0_PQ_SEL_IN 0xF04
+ #define MT8195_VPPSYS0_PQ_SEL_IN_FROM_STITCH 0
+ #define MT8195_VPPSYS0_PQ_SEL_IN_FROM_WARP0 1
+ #define MT8195_VPPSYS0_PQ_SEL_IN_FROM_WARP1 2
+ #define MT8195_VPPSYS0_PQ_SEL_IN_FROM_MDP_FG 3
+#define MT8195_VPPSYS0_VPP1_SEL_IN 0xF08
+ #define MT8195_VPPSYS0_VPP1_SEL_IN_FROM_PADDING_SOUT 0
+ #define MT8195_VPPSYS0_VPP1_SEL_IN_FROM_STITCH 1
+ #define MT8195_VPPSYS0_VPP1_SEL_IN_FROM_WARP0 2
+ #define MT8195_VPPSYS0_VPP1_SEL_IN_FROM_WARP1 3
+ #define MT8195_VPPSYS0_VPP1_SEL_IN_FROM_MDP_FG 4
+#define MT8195_VPPSYS0_HDR_SEL_IN 0xF0C
+ #define MT8195_VPPSYS0_HDR_SEL_IN_FROM_PQ_SOUT 0
+ #define MT8195_VPPSYS0_HDR_SEL_IN_FROM_TCC_SOUT 1
+ #define MT8195_VPPSYS0_HDR_SEL_IN_FROM_VPP1_IN_SOUT 2
+#define MT8195_VPPSYS0_AAL_SEL_IN 0xF18
+ #define MT8195_VPPSYS0_AAL_SEL_IN_FROM_MDP_HDR 0
+ #define MT8195_VPPSYS0_AAL_SEL_IN_FROM_VPP1_IN_SOUT 1
+#define MT8195_VPPSYS0_TCC_SEL_IN 0xF10
+ #define MT8195_VPPSYS0_TCC_SEL_IN_FROM_PADDING_SOUT 0
+ #define MT8195_VPPSYS0_TCC_SEL_IN_FROM_PQ_SOUT 1
+#define MT8195_VPPSYS0_WROT_SEL_IN 0xF14
+ #define MT8195_VPPSYS0_WROT_SEL_IN_FROM_TCC_SOUT 0
+ #define MT8195_VPPSYS0_WROT_SEL_IN_FROM_PADDING_SOUT 1
+ #define MT8195_VPPSYS0_WROT_SEL_IN_FROM_MDP_RDMA 2
+
+/* VPPSYS1 SEL_IN */
+#define MT8195_SVPP1_SRC_SEL_IN 0xF1C
+ #define MT8195_SVPP1_SRC_SEL_IN_FROM_SVPP1_MDP_FG 0
+ #define MT8195_SVPP1_SRC_SEL_IN_FROM_VPP0_SRC_SOUT 1
+#define MT8195_SVPP2_SRC_SEL_IN 0xF38
+ #define MT8195_SVPP2_SRC_SEL_IN_FROM_SVPP2_MDP_FG 0
+ #define MT8195_SVPP2_SRC_SEL_IN_FROM_VPP_SPLIT_OUT0_SOUT 1
+#define MT8195_SVPP3_SRC_SEL_IN 0xF64
+ #define MT8195_SVPP3_SRC_SEL_IN_FROM_SVPP3_MDP_FG 0
+ #define MT8195_SVPP3_SRC_SEL_IN_FROM_VPP_SPLIT_OUT1_SOUT 1
+#define MT8195_SVPP1_HDR_SRC_SEL_IN 0xF24
+ #define MT8195_SVPP1_HDR_SRC_SEL_IN_FROM_SVPP1_SRC_SEL_SOUT 0
+ #define MT8195_SVPP1_HDR_SRC_SEL_IN_FROM_SVPP1_TCC_SOUT 1
+ #define MT8195_SVPP1_HDR_SRC_SEL_IN_FROM_SVPP2_SRC_SEL_MOUT 2
+#define MT8195_SVPP1_MDP_AAL_SEL_IN 0xF54
+ #define MT8195_SVPP1_MDP_AAL_SEL_IN_FROM_SVPP1_MDP_HDR 0
+ #define MT8195_SVPP1_MDP_AAL_SEL_IN_FROM_SVPP2_MDP_HDR_MOUT 1
+#define MT8195_SVPP1_TCC_SEL_IN 0xF30
+ #define MT8195_SVPP1_TCC_SEL_IN_FROM_SVPP1_PATH_SOUT 0
+ #define MT8195_SVPP1_TCC_SEL_IN_FROM_SVPP1_SRC_SEL_SOUT 1
+#define MT8195_VPP0_DL1_SRC_SEL_IN 0xF80
+ #define MT8195_VPP0_DL1_SRC_SEL_IN_FROM_SVPP3_SRC_SEL_MOUT 0
+ #define MT8195_VPP0_DL1_SRC_SEL_IN_FROM_SVPP3_MDP_HDR_MOUT 1
+ #define MT8195_VPP0_DL1_SRC_SEL_IN_FROM_SVPP1_SRC_SEL_SOUT 2
+#define MT8195_SVPP2_RSZ_MERGE_IN_SEL_IN 0xF44
+ #define MT8195_SVPP2_RSZ_MERGE_IN_SEL_IN_FROM_SVPP2_MDP_AAL 0
+ #define MT8195_SVPP2_RSZ_MERGE_IN_SEL_IN_FROM_VPP_SPLIT_OUT0_SOUT 1
+#define MT8195_SVPP3_RSZ_MERGE_IN_SEL_IN 0xF70
+ #define MT8195_SVPP3_RSZ_MERGE_IN_SEL_IN_FROM_SVPP3_MDP_AAL 0
+ #define MT8195_SVPP3_RSZ_MERGE_IN_SEL_IN_FROM_VPP_SPLIT_OUT1_SOUT 1
+#define MT8195_SVPP1_WROT_SRC_SEL_IN 0xF2c
+ #define MT8195_SVPP1_WROT_SRC_SEL_IN_FROM_SVPP1_TCC_SOUT 0
+ #define MT8195_SVPP1_WROT_SRC_SEL_IN_FROM_SVPP1_PATH_SOUT 1
+ #define MT8195_SVPP1_WROT_SRC_SEL_IN_FROM_SVPP1_MDP_RDMA_SOUT 2
+#define MT8195_SVPP2_WROT_SRC_SEL_IN 0xF40
+ #define MT8195_SVPP2_WROT_SRC_SEL_IN_FROM_SVPP1_PATH_SOUT 0
+ #define MT8195_SVPP2_WROT_SRC_SEL_IN_FROM_SVPP2_VPP_PAD 1
+ #define MT8195_SVPP2_WROT_SRC_SEL_IN_FROM_SVPP2_MDP_RDMA_SOUT 2
+#define MT8195_SVPP3_WROT_SRC_SEL_IN 0xF6c
+ #define MT8195_SVPP3_WROT_SRC_SEL_IN_FROM_VPP0_SRC_SOUT 0
+ #define MT8195_SVPP3_WROT_SRC_SEL_IN_FROM_SVPP3_VPP_PAD 1
+ #define MT8195_SVPP3_WROT_SRC_SEL_IN_FROM_SVPP3_MDP_RDMA_SOUT 2
+
+/* VPPSYS0 SEL_OUT */
+#define MT8195_VPPSYS0_WARP0_SOUT_SEL_IN 0xF20
+ #define MT8195_VPPSYS0_WARP0_SOUT_SEL_IN_TO_STITCH 0
+ #define MT8195_VPPSYS0_WARP0_SOUT_SEL_IN_TO_WARP0_MOUT 1
+#define MT8195_VPPSYS0_WARP1_SOUT_SEL_IN 0xF24
+ #define MT8195_VPPSYS0_WARP0_SOUT_SEL_IN_TO_STITCH 0
+ #define MT8195_VPPSYS0_WARP0_SOUT_SEL_IN_TO_WARP1_MOUT 1
+#define MT8195_VPPSYS0_MDP_RDMA_SOUT_SEL_IN 0xF1C
+ #define MT8195_VPPSYS0_MDP_RDMA_SOUT_SEL_IN_TO_MDP_FG 0
+ #define MT8195_VPPSYS0_MDP_RDMA_SOUT_SEL_IN_TO_MDP_WROT_SEL_IN 1
+#define MT8195_VPPSYS0_PQ_SOUT_SEL_IN 0xF28
+ #define MT8195_VPPSYS0_PQ_SOUT_SOUT_SEL_IN_TO_PQ_SEL_IN 0
+ #define MT8195_VPPSYS0_PQ_SOUT_SOUT_SEL_IN_TO_TCC_SEL_IN 1
+#define MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN 0xF34
+ #define MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN_TO_HDR_SEL_IN 0
+ #define MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN_TO_AAL_SEL_IN 1
+ #define MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN_TO_MDP_RSZ 2
+#define MT8195_VPPSYS0_PADDING_SOUT_SEL_IN 0xF2C
+ #define MT8195_VPPSYS0_PADDING_SOUT_SEL_IN_TO_TCC_SEL_IN 0
+ #define MT8195_VPPSYS0_PADDING_SOUT_SEL_IN_TO_WROT_SEL_IN 1
+ #define MT8195_VPPSYS0_PADDING_SOUT_SEL_IN_TO_VPP1_SEL_IN 2
+#define MT8195_VPPSYS0_TCC_SOUT_SEL_IN 0xF30
+ #define MT8195_VPPSYS0_TCC_SOUT_SEL_IN_TO_WROT_SEL_IN 0
+ #define MT8195_VPPSYS0_TCC_SOUT_SEL_IN_TO_HDR_SEL_IN 1
+
+/* VPPSYS1 SEL_OUT */
+#define MT8195_SVPP1_MDP_RDMA_SOUT_SEL 0xF18
+ #define MT8195_SVPP1_MDP_RDMA_SOUT_SEL_TO_SVPP1_MDP_FG 0
+ #define MT8195_SVPP1_MDP_RDMA_SOUT_SEL_TO_SVPP2_MDP_RSZ 1
+ #define MT8195_SVPP1_MDP_RDMA_SOUT_SEL_TO_SVPP1_WROT_SRC_SEL 2
+#define MT8195_SVPP2_MDP_RDMA_SOUT_SEL 0xF90
+ #define MT8195_SVPP2_MDP_RDMA_SOUT_SEL_TO_SVPP2_MDP_FG 0
+ #define MT8195_SVPP2_MDP_RDMA_SOUT_SEL_TO_SVPP2_WROT_SRC_SEL 1
+#define MT8195_SVPP3_MDP_RDMA_SOUT_SEL 0xF60
+ #define MT8195_SVPP3_MDP_RDMA_SOUT_SEL_TO_SVPP3_MDP_FG 0
+ #define MT8195_SVPP3_MDP_RDMA_SOUT_SEL_TO_SVPP3_WROT_SRC_SEL 1
+#define MT8195_VPP0_SRC_SOUT_SEL 0xF8C
+ #define MT8195_VPP0_SRC_SOUT_SEL_TO_SVPP1_SRC_SEL 0
+ #define MT8195_VPP0_SRC_SOUT_SEL_TO_SVPP3_MDP_RSZ 1
+ #define MT8195_VPP0_SRC_SOUT_SEL_TO_SVPP3_WROT_SRC_SEL 2
+#define MT8195_SVPP1_SRC_SEL_SOUT_SEL 0xF20
+ #define MT8195_SVPP1_SRC_SEL_SOUT_SEL_TO_SVPP1_HDR_SRC_SEL 0
+ #define MT8195_SVPP1_SRC_SEL_SOUT_SEL_TO_SVPP1_TCC_SEL 1
+ #define MT8195_SVPP1_SRC_SEL_SOUT_SEL_TO_VPP0_DL1_SRC_SEL 2
+#define MT8195_SVPP2_COLOR_SOUT_SEL 0xF3c
+ #define MT8195_SVPP2_COLOR_SOUT_SEL_TO_SVPP2_VPP_PAD 0
+ #define MT8195_SVPP2_COLOR_SOUT_SEL_TO_VDO0_DL0_RELAY 1
+ #define MT8195_SVPP2_COLOR_SOUT_SEL_TO_VDO1_DL0_RELAY 2
+#define MT8195_SVPP3_COLOR_SOUT_SEL 0xF68
+ #define MT8195_SVPP3_COLOR_SOUT_SEL_TO_SVPP3_VPP_PAD 0
+ #define MT8195_SVPP3_COLOR_SOUT_SEL_TO_VDO0_DL1_RELAY 1
+ #define MT8195_SVPP3_COLOR_SOUT_SEL_TO_VDO1_DL1_RELAY 2
+#define MT8195_SVPP1_TCC_SOUT_SEL 0xF34
+ #define MT8195_SVPP1_TCC_SOUT_SEL_TO_SVPP1_WROT_SRC_SEL 0
+ #define MT8195_SVPP1_TCC_SOUT_SEL_TO_SVPP1_HDR_SRC_SEL 1
+#define MT8195_SVPP1_PATH_SOUT_SEL 0xF28
+ #define MT8195_SVPP1_PATH_SOUT_SEL_TO_SVPP1_TCC_SEL 0
+ #define MT8195_SVPP1_PATH_SOUT_SEL_TO_SVPP1_WROT_SRC_SEL 1
+ #define MT8195_SVPP1_PATH_SOUT_SEL_TO_SVPP2_WROT_SRC_SEL 2
+
+/* VPPSYS0 */
+#define VPPSYS0_HW_DCM_1ST_DIS0 0x050
+
+/* VPPSYS1 */
+#define VPPSYS1_HW_DCM_1ST_DIS0 0x150
+#define VPPSYS1_HW_DCM_1ST_DIS1 0x160
+#define VPPSYS1_HW_DCM_2ND_DIS0 0x1a0
+#define VPPSYS1_HW_DCM_2ND_DIS1 0x1b0
+#define VPP0_DL_IRELAY_WR 0x920
+#define SVPP2_BUF_BF_RSZ_SWITCH 0xf48
+#define SVPP3_BUF_BF_RSZ_SWITCH 0xf74
+
+static const u32 mmsys_mt8195_mdp_vppsys_config_table[] = {
+ VPPSYS0_HW_DCM_1ST_DIS0,
+ VPP0_DL_IRELAY_WR,
+ VPPSYS1_HW_DCM_1ST_DIS0,
+ VPPSYS1_HW_DCM_1ST_DIS1,
+ VPPSYS1_HW_DCM_2ND_DIS0,
+ VPPSYS1_HW_DCM_2ND_DIS1,
+ SVPP2_BUF_BF_RSZ_SWITCH,
+ SVPP3_BUF_BF_RSZ_SWITCH,
+};
+
+static const struct mtk_mmsys_routes mmsys_mt8195_mdp_routing_table[] = {
+ /* VPPSYS0 MOUT */
+ {
+ MDP_COMP_STITCH, MDP_COMP_PQ0_SOUT,
+ MT8195_VPPSYS0_STITCH_MOUT_EN,
+ MT8195_VPPSYS0_STITCH_MOUT_TO_PQ_SEL_IN,
+ MT8195_VPPSYS0_STITCH_MOUT_TO_PQ_SEL_IN
+ }, {
+ MDP_COMP_STITCH, MDP_COMP_VPP0_SOUT,
+ MT8195_VPPSYS0_STITCH_MOUT_EN,
+ MT8195_VPPSYS0_STITCH_MOUT_TO_VPP1_SEL_IN,
+ MT8195_VPPSYS0_STITCH_MOUT_TO_VPP1_SEL_IN
+ }, {
+ MDP_COMP_CAMIN, MDP_COMP_PQ0_SOUT,
+ MT8195_VPPSYS0_WARP0_MOUT_EN,
+ MT8195_VPPSYS0_WARP0_MOUT_TO_PQ_SEL_IN,
+ MT8195_VPPSYS0_WARP0_MOUT_TO_PQ_SEL_IN
+ }, {
+ MDP_COMP_CAMIN, MDP_COMP_VPP0_SOUT,
+ MT8195_VPPSYS0_WARP0_MOUT_EN,
+ MT8195_VPPSYS0_WARP0_MOUT_TO_VPP1_SEL_IN,
+ MT8195_VPPSYS0_WARP0_MOUT_TO_VPP1_SEL_IN
+ },
+ {
+ MDP_COMP_CAMIN2, MDP_COMP_PQ0_SOUT,
+ MT8195_VPPSYS0_WARP1_MOUT_EN,
+ MT8195_VPPSYS0_WARP1_MOUT_TO_PQ_SEL_IN,
+ MT8195_VPPSYS0_WARP1_MOUT_TO_PQ_SEL_IN
+ }, {
+ MDP_COMP_CAMIN2, MDP_COMP_VPP0_SOUT,
+ MT8195_VPPSYS0_WARP1_MOUT_EN,
+ MT8195_VPPSYS0_WARP1_MOUT_TO_VPP1_SEL_IN,
+ MT8195_VPPSYS0_WARP1_MOUT_TO_VPP1_SEL_IN
+ }, {
+ MDP_COMP_FG0, MDP_COMP_PQ0_SOUT,
+ MT8195_VPPSYS0_FG_MOUT_EN,
+ MT8195_VPPSYS0_FG_MOUT_TO_PQ_SEL_IN,
+ MT8195_VPPSYS0_FG_MOUT_TO_PQ_SEL_IN
+ }, {
+ MDP_COMP_FG0, MDP_COMP_VPP0_SOUT,
+ MT8195_VPPSYS0_FG_MOUT_EN,
+ MT8195_VPPSYS0_FG_MOUT_TO_VPP1_SEL_IN,
+ MT8195_VPPSYS0_FG_MOUT_TO_VPP1_SEL_IN
+ },
+ /* VPPSYS1 MOUT */
+ {
+ MDP_COMP_TO_SVPP2MOUT, MDP_COMP_HDR2,
+ MT8195_SVPP2_SRC_SEL_MOUT_EN,
+ MT8195_SVPP2_MDP_HDR,
+ MT8195_SVPP2_MDP_HDR
+ }, {
+ MDP_COMP_TO_SVPP2MOUT, MDP_COMP_HDR1,
+ MT8195_SVPP2_SRC_SEL_MOUT_EN,
+ MT8195_SVPP1_HDR_SRC_SEL,
+ MT8195_SVPP1_HDR_SRC_SEL
+ }, {
+ MDP_COMP_TO_SVPP3MOUT, MDP_COMP_HDR3,
+ MT8195_SVPP3_SRC_SEL_MOUT_EN,
+ MT8195_SVPP3_MDP_HDR,
+ MT8195_SVPP3_MDP_HDR
+ }, {
+ MDP_COMP_TO_SVPP3MOUT, MDP_COMP_VPP1_SOUT,
+ MT8195_SVPP3_SRC_SEL_MOUT_EN,
+ MT8195_VPP0_DL1_SRC_SEL,
+ MT8195_VPP0_DL1_SRC_SEL
+ }, {
+ MDP_COMP_HDR2, MDP_COMP_AAL2,
+ MT8195_SVPP2_MDP_HDR_MOUT_EN,
+ MT8195_SVPP2_MDP_AAL,
+ MT8195_SVPP2_MDP_AAL
+ }, {
+ MDP_COMP_HDR2, MDP_COMP_AAL1,
+ MT8195_SVPP2_MDP_HDR_MOUT_EN,
+ MT8195_SVPP1_MDP_AAL_SEL,
+ MT8195_SVPP1_MDP_AAL_SEL
+ }, {
+ MDP_COMP_HDR3, MDP_COMP_AAL3,
+ MT8195_SVPP3_MDP_HDR_MOUT_EN,
+ MT8195_SVPP3_MDP_AAL,
+ MT8195_SVPP3_MDP_AAL
+ }, {
+ MDP_COMP_HDR3, MDP_COMP_VPP1_SOUT,
+ MT8195_SVPP3_MDP_HDR_MOUT_EN,
+ MT8195_VPP0_DL1_SRC_SEL,
+ MT8195_VPP0_DL1_SRC_SEL
+ },
+ /* VPPSYS0 SEL_IN */
+ {
+ MDP_COMP_STITCH, MDP_COMP_PQ0_SOUT,
+ MT8195_VPPSYS0_PQ_SEL_IN,
+ MT8195_VPPSYS0_PQ_SEL_IN_FROM_STITCH,
+ MT8195_VPPSYS0_PQ_SEL_IN_FROM_STITCH
+ }, {
+ MDP_COMP_CAMIN, MDP_COMP_PQ0_SOUT,
+ MT8195_VPPSYS0_PQ_SEL_IN,
+ MT8195_VPPSYS0_PQ_SEL_IN_FROM_WARP0,
+ MT8195_VPPSYS0_PQ_SEL_IN_FROM_WARP0
+ }, {
+ MDP_COMP_CAMIN2, MDP_COMP_PQ0_SOUT,
+ MT8195_VPPSYS0_PQ_SEL_IN,
+ MT8195_VPPSYS0_PQ_SEL_IN_FROM_WARP1,
+ MT8195_VPPSYS0_PQ_SEL_IN_FROM_WARP1
+ }, {
+ MDP_COMP_FG0, MDP_COMP_PQ0_SOUT,
+ MT8195_VPPSYS0_PQ_SEL_IN,
+ MT8195_VPPSYS0_PQ_SEL_IN_FROM_MDP_FG,
+ MT8195_VPPSYS0_PQ_SEL_IN_FROM_MDP_FG
+ }, {
+ MDP_COMP_PAD0, MDP_COMP_VPP0_SOUT,
+ MT8195_VPPSYS0_VPP1_SEL_IN,
+ MT8195_VPPSYS0_VPP1_SEL_IN_FROM_PADDING_SOUT,
+ MT8195_VPPSYS0_VPP1_SEL_IN_FROM_PADDING_SOUT
+ }, {
+ MDP_COMP_STITCH, MDP_COMP_VPP0_SOUT,
+ MT8195_VPPSYS0_VPP1_SEL_IN,
+ MT8195_VPPSYS0_VPP1_SEL_IN_FROM_STITCH,
+ MT8195_VPPSYS0_VPP1_SEL_IN_FROM_STITCH
+ }, {
+ MDP_COMP_CAMIN, MDP_COMP_VPP0_SOUT,
+ MT8195_VPPSYS0_VPP1_SEL_IN,
+ MT8195_VPPSYS0_VPP1_SEL_IN_FROM_WARP0,
+ MT8195_VPPSYS0_VPP1_SEL_IN_FROM_WARP0
+ }, {
+ MDP_COMP_CAMIN2, MDP_COMP_VPP0_SOUT,
+ MT8195_VPPSYS0_VPP1_SEL_IN,
+ MT8195_VPPSYS0_VPP1_SEL_IN_FROM_WARP1,
+ MT8195_VPPSYS0_VPP1_SEL_IN_FROM_WARP1
+ }, {
+ MDP_COMP_FG0, MDP_COMP_VPP0_SOUT,
+ MT8195_VPPSYS0_VPP1_SEL_IN,
+ MT8195_VPPSYS0_VPP1_SEL_IN_FROM_MDP_FG,
+ MT8195_VPPSYS0_VPP1_SEL_IN_FROM_MDP_FG
+ }, {
+ MDP_COMP_PQ0_SOUT, MDP_COMP_HDR0,
+ MT8195_VPPSYS0_HDR_SEL_IN,
+ MT8195_VPPSYS0_HDR_SEL_IN_FROM_PQ_SOUT,
+ MT8195_VPPSYS0_HDR_SEL_IN_FROM_PQ_SOUT
+ }, {
+ MDP_COMP_TCC0, MDP_COMP_HDR0,
+ MT8195_VPPSYS0_HDR_SEL_IN,
+ MT8195_VPPSYS0_HDR_SEL_IN_FROM_TCC_SOUT,
+ MT8195_VPPSYS0_HDR_SEL_IN_FROM_TCC_SOUT
+ }, {
+ MDP_COMP_VPP1_SOUT, MDP_COMP_HDR0,
+ MT8195_VPPSYS0_HDR_SEL_IN,
+ MT8195_VPPSYS0_HDR_SEL_IN_FROM_VPP1_IN_SOUT,
+ MT8195_VPPSYS0_HDR_SEL_IN_FROM_VPP1_IN_SOUT
+ }, {
+ MDP_COMP_HDR0, MDP_COMP_AAL0,
+ MT8195_VPPSYS0_AAL_SEL_IN,
+ MT8195_VPPSYS0_AAL_SEL_IN_FROM_MDP_HDR,
+ MT8195_VPPSYS0_AAL_SEL_IN_FROM_MDP_HDR
+ }, {
+ MDP_COMP_VPP1_SOUT, MDP_COMP_AAL0,
+ MT8195_VPPSYS0_AAL_SEL_IN,
+ MT8195_VPPSYS0_AAL_SEL_IN_FROM_VPP1_IN_SOUT,
+ MT8195_VPPSYS0_AAL_SEL_IN_FROM_VPP1_IN_SOUT
+ }, {
+ MDP_COMP_PAD0, MDP_COMP_TCC0,
+ MT8195_VPPSYS0_TCC_SEL_IN,
+ MT8195_VPPSYS0_TCC_SEL_IN_FROM_PADDING_SOUT,
+ MT8195_VPPSYS0_TCC_SEL_IN_FROM_PADDING_SOUT
+ }, {
+ MDP_COMP_PQ0_SOUT, MDP_COMP_TCC0,
+ MT8195_VPPSYS0_TCC_SEL_IN,
+ MT8195_VPPSYS0_TCC_SEL_IN_FROM_PQ_SOUT,
+ MT8195_VPPSYS0_TCC_SEL_IN_FROM_PQ_SOUT
+ }, {
+ MDP_COMP_TCC0, MDP_COMP_WROT0,
+ MT8195_VPPSYS0_WROT_SEL_IN,
+ MT8195_VPPSYS0_WROT_SEL_IN_FROM_TCC_SOUT,
+ MT8195_VPPSYS0_WROT_SEL_IN_FROM_TCC_SOUT
+ }, {
+ MDP_COMP_PAD0, MDP_COMP_WROT0,
+ MT8195_VPPSYS0_WROT_SEL_IN,
+ MT8195_VPPSYS0_WROT_SEL_IN_FROM_PADDING_SOUT,
+ MT8195_VPPSYS0_WROT_SEL_IN_FROM_PADDING_SOUT
+ }, {
+ MDP_COMP_RDMA0, MDP_COMP_WROT0,
+ MT8195_VPPSYS0_WROT_SEL_IN,
+ MT8195_VPPSYS0_WROT_SEL_IN_FROM_MDP_RDMA,
+ MT8195_VPPSYS0_WROT_SEL_IN_FROM_MDP_RDMA
+ },
+ /* VPPSYS1 SEL_IN */
+ {
+ MDP_COMP_FG1, MDP_COMP_PQ1_SOUT,
+ MT8195_SVPP1_SRC_SEL_IN,
+ MT8195_SVPP1_SRC_SEL_IN_FROM_SVPP1_MDP_FG,
+ MT8195_SVPP1_SRC_SEL_IN_FROM_SVPP1_MDP_FG
+ }, {
+ MDP_COMP_VPP0_SOUT, MDP_COMP_PQ1_SOUT,
+ MT8195_SVPP1_SRC_SEL_IN,
+ MT8195_SVPP1_SRC_SEL_IN_FROM_VPP0_SRC_SOUT,
+ MT8195_SVPP1_SRC_SEL_IN_FROM_VPP0_SRC_SOUT
+ }, {
+ MDP_COMP_FG2, MDP_COMP_TO_SVPP2MOUT,
+ MT8195_SVPP2_SRC_SEL_IN,
+ MT8195_SVPP2_SRC_SEL_IN_FROM_SVPP2_MDP_FG,
+ MT8195_SVPP2_SRC_SEL_IN_FROM_SVPP2_MDP_FG
+ }, {
+ MDP_COMP_SPLIT, MDP_COMP_TO_SVPP2MOUT,
+ MT8195_SVPP2_SRC_SEL_IN,
+ MT8195_SVPP2_SRC_SEL_IN_FROM_VPP_SPLIT_OUT0_SOUT,
+ MT8195_SVPP2_SRC_SEL_IN_FROM_VPP_SPLIT_OUT0_SOUT
+ }, {
+ MDP_COMP_FG3, MDP_COMP_TO_SVPP3MOUT,
+ MT8195_SVPP3_SRC_SEL_IN,
+ MT8195_SVPP3_SRC_SEL_IN_FROM_SVPP3_MDP_FG,
+ MT8195_SVPP3_SRC_SEL_IN_FROM_SVPP3_MDP_FG
+ }, {
+ MDP_COMP_SPLIT2, MDP_COMP_TO_SVPP3MOUT,
+ MT8195_SVPP3_SRC_SEL_IN,
+ MT8195_SVPP3_SRC_SEL_IN_FROM_VPP_SPLIT_OUT1_SOUT,
+ MT8195_SVPP3_SRC_SEL_IN_FROM_VPP_SPLIT_OUT1_SOUT
+ }, {
+ MDP_COMP_PQ1_SOUT, MDP_COMP_HDR1,
+ MT8195_SVPP1_HDR_SRC_SEL_IN,
+ MT8195_SVPP1_HDR_SRC_SEL_IN_FROM_SVPP1_SRC_SEL_SOUT,
+ MT8195_SVPP1_HDR_SRC_SEL_IN_FROM_SVPP1_SRC_SEL_SOUT
+ }, {
+ MDP_COMP_TCC1, MDP_COMP_HDR1,
+ MT8195_SVPP1_HDR_SRC_SEL_IN,
+ MT8195_SVPP1_HDR_SRC_SEL_IN_FROM_SVPP1_TCC_SOUT,
+ MT8195_SVPP1_HDR_SRC_SEL_IN_FROM_SVPP1_TCC_SOUT
+ }, {
+ MDP_COMP_TO_SVPP2MOUT, MDP_COMP_HDR1,
+ MT8195_SVPP1_HDR_SRC_SEL_IN,
+ MT8195_SVPP1_HDR_SRC_SEL_IN_FROM_SVPP2_SRC_SEL_MOUT,
+ MT8195_SVPP1_HDR_SRC_SEL_IN_FROM_SVPP2_SRC_SEL_MOUT
+ }, {
+ MDP_COMP_HDR1, MDP_COMP_AAL1,
+ MT8195_SVPP1_MDP_AAL_SEL_IN,
+ MT8195_SVPP1_MDP_AAL_SEL_IN_FROM_SVPP1_MDP_HDR,
+ MT8195_SVPP1_MDP_AAL_SEL_IN_FROM_SVPP1_MDP_HDR
+ }, {
+ MDP_COMP_HDR2, MDP_COMP_AAL1,
+ MT8195_SVPP1_MDP_AAL_SEL_IN,
+ MT8195_SVPP1_MDP_AAL_SEL_IN_FROM_SVPP2_MDP_HDR_MOUT,
+ MT8195_SVPP1_MDP_AAL_SEL_IN_FROM_SVPP2_MDP_HDR_MOUT
+ }, {
+ MDP_COMP_PAD1, MDP_COMP_TCC1,
+ MT8195_SVPP1_TCC_SEL_IN,
+ MT8195_SVPP1_TCC_SEL_IN_FROM_SVPP1_PATH_SOUT,
+ MT8195_SVPP1_TCC_SEL_IN_FROM_SVPP1_PATH_SOUT
+ }, {
+ MDP_COMP_PQ1_SOUT, MDP_COMP_TCC1,
+ MT8195_SVPP1_TCC_SEL_IN,
+ MT8195_SVPP1_TCC_SEL_IN_FROM_SVPP1_SRC_SEL_SOUT,
+ MT8195_SVPP1_TCC_SEL_IN_FROM_SVPP1_SRC_SEL_SOUT
+ }, {
+ MDP_COMP_TO_SVPP3MOUT, MDP_COMP_VPP1_SOUT,
+ MT8195_VPP0_DL1_SRC_SEL_IN,
+ MT8195_VPP0_DL1_SRC_SEL_IN_FROM_SVPP3_SRC_SEL_MOUT,
+ MT8195_VPP0_DL1_SRC_SEL_IN_FROM_SVPP3_SRC_SEL_MOUT
+ }, {
+ MDP_COMP_HDR3, MDP_COMP_VPP1_SOUT,
+ MT8195_VPP0_DL1_SRC_SEL_IN,
+ MT8195_VPP0_DL1_SRC_SEL_IN_FROM_SVPP3_MDP_HDR_MOUT,
+ MT8195_VPP0_DL1_SRC_SEL_IN_FROM_SVPP3_MDP_HDR_MOUT
+ }, {
+ MDP_COMP_PQ1_SOUT, MDP_COMP_VPP1_SOUT,
+ MT8195_VPP0_DL1_SRC_SEL_IN,
+ MT8195_VPP0_DL1_SRC_SEL_IN_FROM_SVPP1_SRC_SEL_SOUT,
+ MT8195_VPP0_DL1_SRC_SEL_IN_FROM_SVPP1_SRC_SEL_SOUT
+ }, {
+ MDP_COMP_AAL2, MDP_COMP_RSZ2,
+ MT8195_SVPP2_RSZ_MERGE_IN_SEL_IN,
+ MT8195_SVPP2_RSZ_MERGE_IN_SEL_IN_FROM_SVPP2_MDP_AAL,
+ MT8195_SVPP2_RSZ_MERGE_IN_SEL_IN_FROM_SVPP2_MDP_AAL
+ }, {
+ MDP_COMP_SPLIT, MDP_COMP_RSZ2,
+ MT8195_SVPP2_RSZ_MERGE_IN_SEL_IN,
+ MT8195_SVPP2_RSZ_MERGE_IN_SEL_IN_FROM_VPP_SPLIT_OUT0_SOUT,
+ MT8195_SVPP2_RSZ_MERGE_IN_SEL_IN_FROM_VPP_SPLIT_OUT0_SOUT
+ }, {
+ MDP_COMP_AAL3, MDP_COMP_RSZ3,
+ MT8195_SVPP3_RSZ_MERGE_IN_SEL_IN,
+ MT8195_SVPP3_RSZ_MERGE_IN_SEL_IN_FROM_SVPP3_MDP_AAL,
+ MT8195_SVPP3_RSZ_MERGE_IN_SEL_IN_FROM_SVPP3_MDP_AAL
+ }, {
+ MDP_COMP_SPLIT2, MDP_COMP_RSZ3,
+ MT8195_SVPP3_RSZ_MERGE_IN_SEL_IN,
+ MT8195_SVPP3_RSZ_MERGE_IN_SEL_IN_FROM_VPP_SPLIT_OUT1_SOUT,
+ MT8195_SVPP3_RSZ_MERGE_IN_SEL_IN_FROM_VPP_SPLIT_OUT1_SOUT
+ }, {
+ MDP_COMP_TCC1, MDP_COMP_WROT1,
+ MT8195_SVPP1_WROT_SRC_SEL_IN,
+ MT8195_SVPP1_WROT_SRC_SEL_IN_FROM_SVPP1_TCC_SOUT,
+ MT8195_SVPP1_WROT_SRC_SEL_IN_FROM_SVPP1_TCC_SOUT
+ }, {
+ MDP_COMP_PAD1, MDP_COMP_WROT1,
+ MT8195_SVPP1_WROT_SRC_SEL_IN,
+ MT8195_SVPP1_WROT_SRC_SEL_IN_FROM_SVPP1_PATH_SOUT,
+ MT8195_SVPP1_WROT_SRC_SEL_IN_FROM_SVPP1_PATH_SOUT
+ }, {
+ MDP_COMP_RDMA1, MDP_COMP_WROT1,
+ MT8195_SVPP1_WROT_SRC_SEL_IN,
+ MT8195_SVPP1_WROT_SRC_SEL_IN_FROM_SVPP1_MDP_RDMA_SOUT,
+ MT8195_SVPP1_WROT_SRC_SEL_IN_FROM_SVPP1_MDP_RDMA_SOUT
+ }, {
+ MDP_COMP_PAD1, MDP_COMP_WROT2,
+ MT8195_SVPP2_WROT_SRC_SEL_IN,
+ MT8195_SVPP2_WROT_SRC_SEL_IN_FROM_SVPP1_PATH_SOUT,
+ MT8195_SVPP2_WROT_SRC_SEL_IN_FROM_SVPP1_PATH_SOUT
+ }, {
+ MDP_COMP_PAD2, MDP_COMP_WROT2,
+ MT8195_SVPP2_WROT_SRC_SEL_IN,
+ MT8195_SVPP2_WROT_SRC_SEL_IN_FROM_SVPP2_VPP_PAD,
+ MT8195_SVPP2_WROT_SRC_SEL_IN_FROM_SVPP2_VPP_PAD
+ }, {
+ MDP_COMP_RDMA2, MDP_COMP_WROT2,
+ MT8195_SVPP2_WROT_SRC_SEL_IN,
+ MT8195_SVPP2_WROT_SRC_SEL_IN_FROM_SVPP2_MDP_RDMA_SOUT,
+ MT8195_SVPP2_WROT_SRC_SEL_IN_FROM_SVPP2_MDP_RDMA_SOUT
+ }, {
+ MDP_COMP_VPP0_SOUT, MDP_COMP_WROT3,
+ MT8195_SVPP3_WROT_SRC_SEL_IN,
+ MT8195_SVPP3_WROT_SRC_SEL_IN_FROM_VPP0_SRC_SOUT,
+ MT8195_SVPP3_WROT_SRC_SEL_IN_FROM_VPP0_SRC_SOUT
+ }, {
+ MDP_COMP_PAD3, MDP_COMP_WROT3,
+ MT8195_SVPP3_WROT_SRC_SEL_IN,
+ MT8195_SVPP3_WROT_SRC_SEL_IN_FROM_SVPP3_VPP_PAD,
+ MT8195_SVPP3_WROT_SRC_SEL_IN_FROM_SVPP3_VPP_PAD
+ }, {
+ MDP_COMP_RDMA3, MDP_COMP_WROT3,
+ MT8195_SVPP3_WROT_SRC_SEL_IN,
+ MT8195_SVPP3_WROT_SRC_SEL_IN_FROM_SVPP3_MDP_RDMA_SOUT,
+ MT8195_SVPP3_WROT_SRC_SEL_IN_FROM_SVPP3_MDP_RDMA_SOUT
+ },
+ /* VPPSYS0 SEL_OUT */
+ {
+ MDP_COMP_WPEI, MDP_COMP_STITCH,
+ MT8195_VPPSYS0_WARP0_SOUT_SEL_IN,
+ MT8195_VPPSYS0_WARP0_SOUT_SEL_IN_TO_STITCH,
+ MT8195_VPPSYS0_WARP0_SOUT_SEL_IN_TO_STITCH
+ }, {
+ MDP_COMP_WPEI, MDP_COMP_CAMIN,
+ MT8195_VPPSYS0_WARP0_SOUT_SEL_IN,
+ MT8195_VPPSYS0_WARP0_SOUT_SEL_IN_TO_WARP0_MOUT,
+ MT8195_VPPSYS0_WARP0_SOUT_SEL_IN_TO_WARP0_MOUT
+ }, {
+ MDP_COMP_WPEI2, MDP_COMP_STITCH,
+ MT8195_VPPSYS0_WARP1_SOUT_SEL_IN,
+ MT8195_VPPSYS0_WARP0_SOUT_SEL_IN_TO_STITCH,
+ MT8195_VPPSYS0_WARP0_SOUT_SEL_IN_TO_STITCH
+ }, {
+ MDP_COMP_WPEI2, MDP_COMP_CAMIN2,
+ MT8195_VPPSYS0_WARP1_SOUT_SEL_IN,
+ MT8195_VPPSYS0_WARP0_SOUT_SEL_IN_TO_WARP1_MOUT,
+ MT8195_VPPSYS0_WARP0_SOUT_SEL_IN_TO_WARP1_MOUT
+ }, {
+ MDP_COMP_RDMA0, MDP_COMP_FG0,
+ MT8195_VPPSYS0_MDP_RDMA_SOUT_SEL_IN,
+ MT8195_VPPSYS0_MDP_RDMA_SOUT_SEL_IN_TO_MDP_FG,
+ MT8195_VPPSYS0_MDP_RDMA_SOUT_SEL_IN_TO_MDP_FG
+ }, {
+ MDP_COMP_RDMA0, MDP_COMP_WROT0,
+ MT8195_VPPSYS0_MDP_RDMA_SOUT_SEL_IN,
+ MT8195_VPPSYS0_MDP_RDMA_SOUT_SEL_IN_TO_MDP_WROT_SEL_IN,
+ MT8195_VPPSYS0_MDP_RDMA_SOUT_SEL_IN_TO_MDP_WROT_SEL_IN
+ }, {
+ MDP_COMP_PQ0_SOUT, MDP_COMP_HDR0,
+ MT8195_VPPSYS0_PQ_SOUT_SEL_IN,
+ MT8195_VPPSYS0_PQ_SOUT_SOUT_SEL_IN_TO_PQ_SEL_IN,
+ MT8195_VPPSYS0_PQ_SOUT_SOUT_SEL_IN_TO_PQ_SEL_IN
+ }, {
+ MDP_COMP_PQ0_SOUT, MDP_COMP_TCC0,
+ MT8195_VPPSYS0_PQ_SOUT_SEL_IN,
+ MT8195_VPPSYS0_PQ_SOUT_SOUT_SEL_IN_TO_TCC_SEL_IN,
+ MT8195_VPPSYS0_PQ_SOUT_SOUT_SEL_IN_TO_TCC_SEL_IN
+ }, {
+ MDP_COMP_VPP1_SOUT, MDP_COMP_HDR0,
+ MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN,
+ MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN_TO_HDR_SEL_IN,
+ MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN_TO_HDR_SEL_IN
+ }, {
+ MDP_COMP_VPP1_SOUT, MDP_COMP_AAL0,
+ MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN,
+ MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN_TO_AAL_SEL_IN,
+ MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN_TO_AAL_SEL_IN
+ }, {
+ MDP_COMP_VPP1_SOUT, MDP_COMP_RSZ2,
+ MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN,
+ MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN_TO_MDP_RSZ,
+ MT8195_VPPSYS0_VPP1_IN_SOUT_SEL_IN_TO_MDP_RSZ
+ }, {
+ MDP_COMP_PAD0, MDP_COMP_TCC0,
+ MT8195_VPPSYS0_PADDING_SOUT_SEL_IN,
+ MT8195_VPPSYS0_PADDING_SOUT_SEL_IN_TO_TCC_SEL_IN,
+ MT8195_VPPSYS0_PADDING_SOUT_SEL_IN_TO_TCC_SEL_IN
+ }, {
+ MDP_COMP_PAD0, MDP_COMP_WROT0,
+ MT8195_VPPSYS0_PADDING_SOUT_SEL_IN,
+ MT8195_VPPSYS0_PADDING_SOUT_SEL_IN_TO_WROT_SEL_IN,
+ MT8195_VPPSYS0_PADDING_SOUT_SEL_IN_TO_WROT_SEL_IN
+ }, {
+ MDP_COMP_PAD0, MDP_COMP_VPP0_SOUT,
+ MT8195_VPPSYS0_PADDING_SOUT_SEL_IN,
+ MT8195_VPPSYS0_PADDING_SOUT_SEL_IN_TO_VPP1_SEL_IN,
+ MT8195_VPPSYS0_PADDING_SOUT_SEL_IN_TO_VPP1_SEL_IN
+ }, {
+ MDP_COMP_TCC0, MDP_COMP_WROT0,
+ MT8195_VPPSYS0_TCC_SOUT_SEL_IN,
+ MT8195_VPPSYS0_TCC_SOUT_SEL_IN_TO_WROT_SEL_IN,
+ MT8195_VPPSYS0_TCC_SOUT_SEL_IN_TO_WROT_SEL_IN
+ }, {
+ MDP_COMP_TCC0, MDP_COMP_HDR0,
+ MT8195_VPPSYS0_TCC_SOUT_SEL_IN,
+ MT8195_VPPSYS0_TCC_SOUT_SEL_IN_TO_HDR_SEL_IN,
+ MT8195_VPPSYS0_TCC_SOUT_SEL_IN_TO_HDR_SEL_IN
+ },
+ /* VPPSYS1 SEL_OUT */
+ {
+ MDP_COMP_RDMA1, MDP_COMP_FG1,
+ MT8195_SVPP1_MDP_RDMA_SOUT_SEL,
+ MT8195_SVPP1_MDP_RDMA_SOUT_SEL_TO_SVPP1_MDP_FG,
+ MT8195_SVPP1_MDP_RDMA_SOUT_SEL_TO_SVPP1_MDP_FG
+ }, {
+ MDP_COMP_RDMA1, MDP_COMP_RSZ2,
+ MT8195_SVPP1_MDP_RDMA_SOUT_SEL,
+ MT8195_SVPP1_MDP_RDMA_SOUT_SEL_TO_SVPP2_MDP_RSZ,
+ MT8195_SVPP1_MDP_RDMA_SOUT_SEL_TO_SVPP2_MDP_RSZ
+ }, {
+ MDP_COMP_RDMA1, MDP_COMP_WROT1,
+ MT8195_SVPP1_MDP_RDMA_SOUT_SEL,
+ MT8195_SVPP1_MDP_RDMA_SOUT_SEL_TO_SVPP1_WROT_SRC_SEL,
+ MT8195_SVPP1_MDP_RDMA_SOUT_SEL_TO_SVPP1_WROT_SRC_SEL
+ }, {
+ MDP_COMP_RDMA2, MDP_COMP_FG2,
+ MT8195_SVPP2_MDP_RDMA_SOUT_SEL,
+ MT8195_SVPP2_MDP_RDMA_SOUT_SEL_TO_SVPP2_MDP_FG,
+ MT8195_SVPP2_MDP_RDMA_SOUT_SEL_TO_SVPP2_MDP_FG
+ }, {
+ MDP_COMP_RDMA2, MDP_COMP_WROT2,
+ MT8195_SVPP2_MDP_RDMA_SOUT_SEL,
+ MT8195_SVPP2_MDP_RDMA_SOUT_SEL_TO_SVPP2_WROT_SRC_SEL,
+ MT8195_SVPP2_MDP_RDMA_SOUT_SEL_TO_SVPP2_WROT_SRC_SEL
+ }, {
+ MDP_COMP_RDMA3, MDP_COMP_FG3,
+ MT8195_SVPP3_MDP_RDMA_SOUT_SEL,
+ MT8195_SVPP3_MDP_RDMA_SOUT_SEL_TO_SVPP3_MDP_FG,
+ MT8195_SVPP3_MDP_RDMA_SOUT_SEL_TO_SVPP3_MDP_FG
+ }, {
+ MDP_COMP_RDMA3, MDP_COMP_WROT3,
+ MT8195_SVPP3_MDP_RDMA_SOUT_SEL,
+ MT8195_SVPP3_MDP_RDMA_SOUT_SEL_TO_SVPP3_WROT_SRC_SEL,
+ MT8195_SVPP3_MDP_RDMA_SOUT_SEL_TO_SVPP3_WROT_SRC_SEL
+ }, {
+ MDP_COMP_VPP0_SOUT, MDP_COMP_PQ1_SOUT,
+ MT8195_VPP0_SRC_SOUT_SEL,
+ MT8195_VPP0_SRC_SOUT_SEL_TO_SVPP1_SRC_SEL,
+ MT8195_VPP0_SRC_SOUT_SEL_TO_SVPP1_SRC_SEL
+ }, {
+ MDP_COMP_VPP0_SOUT, MDP_COMP_RSZ3,
+ MT8195_VPP0_SRC_SOUT_SEL,
+ MT8195_VPP0_SRC_SOUT_SEL_TO_SVPP3_MDP_RSZ,
+ MT8195_VPP0_SRC_SOUT_SEL_TO_SVPP3_MDP_RSZ
+ }, {
+ MDP_COMP_VPP0_SOUT, MDP_COMP_WROT3,
+ MT8195_VPP0_SRC_SOUT_SEL,
+ MT8195_VPP0_SRC_SOUT_SEL_TO_SVPP3_WROT_SRC_SEL,
+ MT8195_VPP0_SRC_SOUT_SEL_TO_SVPP3_WROT_SRC_SEL
+ }, {
+ MDP_COMP_PQ1_SOUT, MDP_COMP_HDR1,
+ MT8195_SVPP1_SRC_SEL_SOUT_SEL,
+ MT8195_SVPP1_SRC_SEL_SOUT_SEL_TO_SVPP1_HDR_SRC_SEL,
+ MT8195_SVPP1_SRC_SEL_SOUT_SEL_TO_SVPP1_HDR_SRC_SEL
+ }, {
+ MDP_COMP_PQ1_SOUT, MDP_COMP_TCC1,
+ MT8195_SVPP1_SRC_SEL_SOUT_SEL,
+ MT8195_SVPP1_SRC_SEL_SOUT_SEL_TO_SVPP1_TCC_SEL,
+ MT8195_SVPP1_SRC_SEL_SOUT_SEL_TO_SVPP1_TCC_SEL
+ }, {
+ MDP_COMP_PQ1_SOUT, MDP_COMP_VPP1_SOUT,
+ MT8195_SVPP1_SRC_SEL_SOUT_SEL,
+ MT8195_SVPP1_SRC_SEL_SOUT_SEL_TO_VPP0_DL1_SRC_SEL,
+ MT8195_SVPP1_SRC_SEL_SOUT_SEL_TO_VPP0_DL1_SRC_SEL
+ }, {
+ MDP_COMP_COLOR2, MDP_COMP_PAD2,
+ MT8195_SVPP2_COLOR_SOUT_SEL,
+ MT8195_SVPP2_COLOR_SOUT_SEL_TO_SVPP2_VPP_PAD,
+ MT8195_SVPP2_COLOR_SOUT_SEL_TO_SVPP2_VPP_PAD
+ }, {
+ MDP_COMP_COLOR2, MDP_COMP_VDO0DL0,
+ MT8195_SVPP2_COLOR_SOUT_SEL,
+ MT8195_SVPP2_COLOR_SOUT_SEL_TO_VDO0_DL0_RELAY,
+ MT8195_SVPP2_COLOR_SOUT_SEL_TO_VDO0_DL0_RELAY
+ }, {
+ MDP_COMP_COLOR2, MDP_COMP_VDO1DL0,
+ MT8195_SVPP2_COLOR_SOUT_SEL,
+ MT8195_SVPP2_COLOR_SOUT_SEL_TO_VDO1_DL0_RELAY,
+ MT8195_SVPP2_COLOR_SOUT_SEL_TO_VDO1_DL0_RELAY
+ }, {
+ MDP_COMP_COLOR3, MDP_COMP_PAD3,
+ MT8195_SVPP3_COLOR_SOUT_SEL,
+ MT8195_SVPP3_COLOR_SOUT_SEL_TO_SVPP3_VPP_PAD,
+ MT8195_SVPP3_COLOR_SOUT_SEL_TO_SVPP3_VPP_PAD
+ }, {
+ MDP_COMP_COLOR3, MDP_COMP_VDO0DL1,
+ MT8195_SVPP3_COLOR_SOUT_SEL,
+ MT8195_SVPP3_COLOR_SOUT_SEL_TO_VDO0_DL1_RELAY,
+ MT8195_SVPP3_COLOR_SOUT_SEL_TO_VDO0_DL1_RELAY
+ }, {
+ MDP_COMP_COLOR3, MDP_COMP_VDO1DL1,
+ MT8195_SVPP3_COLOR_SOUT_SEL,
+ MT8195_SVPP3_COLOR_SOUT_SEL_TO_VDO1_DL1_RELAY,
+ MT8195_SVPP3_COLOR_SOUT_SEL_TO_VDO1_DL1_RELAY
+ }, {
+ MDP_COMP_TCC1, MDP_COMP_WROT1,
+ MT8195_SVPP1_TCC_SOUT_SEL,
+ MT8195_SVPP1_TCC_SOUT_SEL_TO_SVPP1_WROT_SRC_SEL,
+ MT8195_SVPP1_TCC_SOUT_SEL_TO_SVPP1_WROT_SRC_SEL
+ }, {
+ MDP_COMP_TCC1, MDP_COMP_HDR1,
+ MT8195_SVPP1_TCC_SOUT_SEL,
+ MT8195_SVPP1_TCC_SOUT_SEL_TO_SVPP1_HDR_SRC_SEL,
+ MT8195_SVPP1_TCC_SOUT_SEL_TO_SVPP1_HDR_SRC_SEL
+ }, {
+ MDP_COMP_PAD1, MDP_COMP_TCC1,
+ MT8195_SVPP1_PATH_SOUT_SEL,
+ MT8195_SVPP1_PATH_SOUT_SEL_TO_SVPP1_TCC_SEL,
+ MT8195_SVPP1_PATH_SOUT_SEL_TO_SVPP1_TCC_SEL
+ }, {
+ MDP_COMP_PAD1, MDP_COMP_WROT1,
+ MT8195_SVPP1_PATH_SOUT_SEL,
+ MT8195_SVPP1_PATH_SOUT_SEL_TO_SVPP1_WROT_SRC_SEL,
+ MT8195_SVPP1_PATH_SOUT_SEL_TO_SVPP1_WROT_SRC_SEL
+ }, {
+ MDP_COMP_PAD1, MDP_COMP_WROT2,
+ MT8195_SVPP1_PATH_SOUT_SEL,
+ MT8195_SVPP1_PATH_SOUT_SEL_TO_SVPP2_WROT_SRC_SEL,
+ MT8195_SVPP1_PATH_SOUT_SEL_TO_SVPP2_WROT_SRC_SEL
+ },
+};
+
#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index cbae8063a187..35f57388fa90 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -69,6 +69,24 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
.clk_driver = "clk-mt8195-vdo1",
};
+static const struct mtk_mmsys_driver_data mt8195_vppsys0_driver_data = {
+ .clk_driver = "clk-mt8195-vpp0",
+ .mdp_routes = mmsys_mt8195_mdp_routing_table,
+ .mdp_num_routes = ARRAY_SIZE(mmsys_mt8195_mdp_routing_table),
+ .mdp_mmsys_configs = mmsys_mt8195_mdp_vppsys_config_table,
+ .mdp_num_mmsys_configs = ARRAY_SIZE(mmsys_mt8195_mdp_vppsys_config_table),
+ .vppsys = true,
+};
+
+static const struct mtk_mmsys_driver_data mt8195_vppsys1_driver_data = {
+ .clk_driver = "clk-mt8195-vpp1",
+ .mdp_routes = mmsys_mt8195_mdp_routing_table,
+ .mdp_num_routes = ARRAY_SIZE(mmsys_mt8195_mdp_routing_table),
+ .mdp_mmsys_configs = mmsys_mt8195_mdp_vppsys_config_table,
+ .mdp_num_mmsys_configs = ARRAY_SIZE(mmsys_mt8195_mdp_vppsys_config_table),
+ .vppsys = true,
+};
+
static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
.clk_driver = "clk-mt8365-mm",
.routes = mt8365_mmsys_routing_table,
@@ -263,6 +281,18 @@ void mtk_mmsys_mdp_camin_ctrl(struct device *dev, struct mmsys_cmdq_cmd *cmd,
}
EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_camin_ctrl);
+void mtk_mmsys_write_reg(struct device *dev,
+ struct mmsys_cmdq_cmd *cmd,
+ u32 alias_id, u32 value, u32 mask)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const u32 *configs = mmsys->data->mdp_mmsys_configs;
+
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id,
+ mmsys->addr + configs[alias_id], value, mask);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_write_reg);
+
static int mtk_mmsys_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -301,6 +331,9 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
if (IS_ERR(clks))
return PTR_ERR(clks);
+ if (mmsys->data->vppsys)
+ goto EXIT;
+
drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
PLATFORM_DEVID_AUTO, NULL, 0);
if (IS_ERR(drm)) {
@@ -308,6 +341,7 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
return PTR_ERR(drm);
}
+EXIT:
return 0;
}
@@ -348,6 +382,14 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
.compatible = "mediatek,mt8195-vdosys1",
.data = &mt8195_vdosys1_driver_data,
},
+ {
+ .compatible = "mediatek,mt8195-vppsys0",
+ .data = &mt8195_vppsys0_driver_data,
+ },
+ {
+ .compatible = "mediatek,mt8195-vppsys1",
+ .data = &mt8195_vppsys1_driver_data,
+ },
{
.compatible = "mediatek,mt8365-mmsys",
.data = &mt8365_mmsys_driver_data,
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index b24da589ff64..e52a6ff8c843 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -93,6 +93,9 @@ struct mtk_mmsys_driver_data {
const struct mtk_mmsys_routes *mdp_routes;
const unsigned int mdp_num_routes;
const unsigned int *mdp_isp_ctrl;
+ const u32 *mdp_mmsys_configs;
+ const unsigned int mdp_num_mmsys_configs;
+ bool vppsys;
};
/*
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index acf4bd3deac1..ab20aaab6b4b 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -191,4 +191,8 @@ void mtk_mmsys_mdp_camin_ctrl(struct device *dev, struct mmsys_cmdq_cmd *cmd,
enum mtk_mdp_comp_id id,
u32 camin_w, u32 camin_h);
+void mtk_mmsys_write_reg(struct device *dev,
+ struct mmsys_cmdq_cmd *cmd,
+ u32 alias_id, u32 value, u32 mask);
+
#endif /* __MTK_MMSYS_H */
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v1 7/9] soc: mediatek: mutex: support mt8195 vppsys0/1
2021-09-17 2:51 [PATCH v1 1/9] soc: mediatek: mmsys: expand MDP enum for chip independence architecture roy-cw.yeh
` (4 preceding siblings ...)
2021-09-17 2:51 ` [PATCH v1 6/9] soc: mediatek: mmsys: support mt8195 vppsys0/1 roy-cw.yeh
@ 2021-09-17 2:51 ` roy-cw.yeh
2021-09-17 2:51 ` [PATCH v1 9/9] media: platform: mtk-mdp3: Add dual pipe feature support roy-cw.yeh
6 siblings, 0 replies; 9+ messages in thread
From: roy-cw.yeh @ 2021-09-17 2:51 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, Roy-CW . Yeh,
jason-jh . lin, daoyuan huang, Ping-Hsun Wu, Moudy Ho,
Enric Balletbo i Serra, Yongqiang Niu, devicetree, linux-kernel,
linux-media, linux-arm-kernel, linux-mediatek
From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
Add mt8195 mdp mutex info to driver data of mtk-mutex
Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
drivers/soc/mediatek/mtk-mutex.c | 53 ++++++++++++++++++++++++++++++++
1 file changed, 53 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index c100a5249016..0e66b5ff916f 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -122,6 +122,23 @@
#define MT8183_MDP_PIPE_WPEI (MT8183_MUTEX_MDP_START + 2)
#define MT8183_MDP_PIPE_WPEI2 (MT8183_MUTEX_MDP_START + 3)
+#define MT8195_MUTEX_MDP_MOD_MASK 0xFFFFFFFF
+#define MT8195_MUTEX_MDP_MOD1_MASK 0x000000FF
+#define MT8195_MUTEX_MDP_SOF_MASK 0x00000007
+
+#define MT8195_MDP_PIPE_WPEI 0
+#define MT8195_MDP_PIPE_WPEI2 1
+#define MT8195_MDP_PIPE_RDMA0 2
+#define MT8195_MDP_PIPE_VPP1_SOUT 3
+
+#define MT8195_MDP_PIPE_RDMA1 1
+#define MT8195_MDP_PIPE_RDMA2 2
+#define MT8195_MDP_PIPE_RDMA3 3
+
+#define MT8195_MDP_PIPE_SPLIT 2
+#define MT8195_MDP_PIPE_SPLIT2 3
+#define MT8195_MDP_PIPE_VPP0_SOUT 4
+
struct mtk_mutex {
int id;
bool claimed;
@@ -266,6 +283,22 @@ static const unsigned int mt8183_mutex_mdp_offset[MDP_PIPE_MAX] = {
[MDP_PIPE_WPEI2] = MT8183_MDP_PIPE_WPEI2,
};
+static const unsigned int mt8195_mutex_vpp0_offset[MDP_PIPE_MAX] = {
+ [MDP_PIPE_WPEI] = MT8195_MDP_PIPE_WPEI,
+ [MDP_PIPE_WPEI2] = MT8195_MDP_PIPE_WPEI2,
+ [MDP_PIPE_RDMA0] = MT8195_MDP_PIPE_RDMA0,
+ [MDP_PIPE_VPP1_SOUT] = MT8195_MDP_PIPE_VPP1_SOUT,
+};
+
+static const unsigned int mt8195_mutex_vpp1_offset[MDP_PIPE_MAX] = {
+ [MDP_PIPE_SPLIT] = MT8195_MDP_PIPE_SPLIT,
+ [MDP_PIPE_SPLIT2] = MT8195_MDP_PIPE_SPLIT2,
+ [MDP_PIPE_RDMA1] = MT8195_MDP_PIPE_RDMA1,
+ [MDP_PIPE_RDMA2] = MT8195_MDP_PIPE_RDMA2,
+ [MDP_PIPE_RDMA3] = MT8195_MDP_PIPE_RDMA3,
+ [MDP_PIPE_VPP0_SOUT] = MT8195_MDP_PIPE_SPLIT,
+};
+
static const struct mtk_mutex_data mt2701_mutex_driver_data = {
.mutex_mod = mt2701_mutex_mod,
.mutex_sof = mt2712_mutex_sof,
@@ -306,6 +339,22 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = {
.no_clk = true,
};
+static const struct mtk_mutex_data mt8195_vpp0_mutex_driver_data = {
+ .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
+ .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
+ .mutex_mdp_offset = mt8195_mutex_vpp0_offset,
+ .mutex_mdp_mod_mask = MT8195_MUTEX_MDP_MOD_MASK,
+ .mutex_mdp_sof_mask = MT8195_MUTEX_MDP_SOF_MASK,
+};
+
+static const struct mtk_mutex_data mt8195_vpp1_mutex_driver_data = {
+ .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
+ .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
+ .mutex_mdp_offset = mt8195_mutex_vpp1_offset,
+ .mutex_mdp_mod_mask = MT8195_MUTEX_MDP_MOD_MASK,
+ .mutex_mdp_sof_mask = MT8195_MUTEX_MDP_SOF_MASK,
+};
+
struct mtk_mutex *mtk_mutex_get(struct device *dev)
{
struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
@@ -614,6 +663,10 @@ static const struct of_device_id mutex_driver_dt_match[] = {
.data = &mt8173_mutex_driver_data},
{ .compatible = "mediatek,mt8183-disp-mutex",
.data = &mt8183_mutex_driver_data},
+ { .compatible = "mediatek,mt8195-vpp0-mutex",
+ .data = &mt8195_vpp0_mutex_driver_data},
+ { .compatible = "mediatek,mt8195-vpp1-mutex",
+ .data = &mt8195_vpp1_mutex_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v1 9/9] media: platform: mtk-mdp3: Add dual pipe feature support
2021-09-17 2:51 [PATCH v1 1/9] soc: mediatek: mmsys: expand MDP enum for chip independence architecture roy-cw.yeh
` (5 preceding siblings ...)
2021-09-17 2:51 ` [PATCH v1 7/9] soc: mediatek: mutex: " roy-cw.yeh
@ 2021-09-17 2:51 ` roy-cw.yeh
6 siblings, 0 replies; 9+ messages in thread
From: roy-cw.yeh @ 2021-09-17 2:51 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger, Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Fabien Parent, Roy-CW . Yeh,
jason-jh . lin, daoyuan huang, Ping-Hsun Wu, Moudy Ho,
Enric Balletbo i Serra, Yongqiang Niu, devicetree, linux-kernel,
linux-media, linux-arm-kernel, linux-mediatek
From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
Add dual pipe feature which uses two svpp to execute dma
Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
.../media/platform/mtk-mdp3/mtk-mdp3-cmdq.c | 191 ++++++++++++++----
.../media/platform/mtk-mdp3/mtk-mdp3-cmdq.h | 1 +
.../media/platform/mtk-mdp3/mtk-mdp3-core.c | 11 +-
.../media/platform/mtk-mdp3/mtk-mdp3-core.h | 3 +
.../media/platform/mtk-mdp3/mtk-mdp3-m2m.c | 6 +-
.../media/platform/mtk-mdp3/mtk-mdp3-regs.c | 16 ++
.../media/platform/mtk-mdp3/mtk-mdp3-regs.h | 4 +
.../media/platform/mtk-mdp3/mtk-mdp3-vpu.c | 2 +-
.../media/platform/mtk-mdp3/mtk-mdp3-vpu.h | 1 +
9 files changed, 190 insertions(+), 45 deletions(-)
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
index e34c2347707e..5cac728fb773 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
@@ -10,7 +10,10 @@
#include "mtk-mdp3-core.h"
#include "mtk-mdp3-m2m.h"
-#define MDP_PATH_MAX_COMPS IMG_MAX_COMPONENTS
+#define PATH_0 0
+#define PATH_1 1
+#define MDP_DUAL_PIPE 2
+#define MDP_PATH_MAX_COMPS IMG_MAX_COMPONENTS
struct mdp_path {
struct mdp_dev *mdp_dev;
@@ -30,6 +33,9 @@ struct mdp_path {
#define is_dummy_engine(mdp, id) \
((mdp)->mdp_data->comp_data[id].match.type == MDP_COMP_TYPE_DUMMY)
+#define is_dual_pipe(scenario) \
+ ((scenario) == MDP_STREAM_TYPE_DUAL_BITBLT)
+
struct mdp_path_subfrm {
s32 mutex_id;
u32 mutex_mod;
@@ -732,26 +738,31 @@ static void mdp_auto_release_work(struct work_struct *work)
struct mdp_cmdq_cb_param *cb_param;
struct mdp_dev *mdp;
int i;
+ bool finalize;
cb_param = container_of(work, struct mdp_cmdq_cb_param,
auto_release_work);
mdp = cb_param->mdp;
+ finalize = cb_param->finalize;
- i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA0);
- mtk_mutex_unprepare(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].mutex_id]);
-
- i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA1);
- if (i >= 0)
- mtk_mutex_unprepare(mdp->mdp_mutex2[mdp->mdp_data->pipe_info[i].mutex_id]);
+ if (finalize) {
+ i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA0);
+ mtk_mutex_unprepare(mdp->mdp_mutex[mdp->mdp_data->pipe_info[i].mutex_id]);
+ i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA1);
+ if (i >= 0)
+ mtk_mutex_unprepare(mdp->mdp_mutex2[mdp->mdp_data->pipe_info[i].mutex_id]);
+ }
mdp_comp_clocks_off(&mdp->pdev->dev, cb_param->comps,
cb_param->num_comps);
kfree(cb_param->comps);
kfree(cb_param);
- atomic_dec(&mdp->job_count);
- wake_up(&mdp->callback_wq);
+ if (finalize) {
+ atomic_dec(&mdp->job_count);
+ wake_up(&mdp->callback_wq);
+ }
}
static void mdp_handle_cmdq_callback(struct cmdq_cb_data data)
@@ -770,7 +781,9 @@ static void mdp_handle_cmdq_callback(struct cmdq_cb_data data)
mdp = cb_param->mdp;
dev = &mdp->pdev->dev;
- if (cb_param->mdp_ctx)
+ cb_param->finalize = (atomic_dec_and_test(&mdp->cmdq_count));
+
+ if (cb_param->finalize && cb_param->mdp_ctx)
mdp_m2m_job_finish(cb_param->mdp_ctx);
if (cb_param->user_cmdq_cb) {
@@ -805,12 +818,15 @@ static void mdp_handle_cmdq_callback(struct cmdq_cb_data data)
int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param)
{
- struct mmsys_cmdq_cmd cmd;
- struct mdp_path path;
+ struct mmsys_cmdq_cmd cmd, cmd_d;
+ static struct mdp_path path[MDP_DUAL_PIPE];
struct mdp_cmdq_cb_param *cb_param = NULL;
+ struct mdp_cmdq_cb_param *cb_param_d = NULL;
struct mdp_comp *comps = NULL;
+ struct mdp_comp *comps_d = NULL;
struct device *dev = &mdp->pdev->dev;
- int i, ret;
+ enum mdp_stream_type scenario = param->param->type;
+ int i, ret, path_id;
if (atomic_read(&mdp->suspended))
return -ECANCELED;
@@ -825,24 +841,39 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param)
}
cmd.event = &mdp->event[0];
- path.mdp_dev = mdp;
- path.config = param->config;
- path.param = param->param;
- for (i = 0; i < param->param->num_outputs; i++) {
- path.bounds[i].left = 0;
- path.bounds[i].top = 0;
- path.bounds[i].width =
- param->param->outputs[i].buffer.format.width;
- path.bounds[i].height =
- param->param->outputs[i].buffer.format.height;
- path.composes[i] = param->composes[i] ?
- param->composes[i] : &path.bounds[i];
- }
-
- ret = mdp_path_ctx_init(mdp, &path);
- if (ret) {
- pr_info("%s mdp_path_ctx_init error\n", __func__);
- goto err_destroy_pkt;
+ if (is_dual_pipe(scenario)) {
+ cmd_d.pkt = cmdq_pkt_create(mdp->cmdq_d_clt, SZ_16K);
+ if (IS_ERR(cmd_d.pkt)) {
+ atomic_dec(&mdp->job_count);
+ wake_up(&mdp->callback_wq);
+ return PTR_ERR(cmd_d.pkt);
+ }
+ cmd_d.event = &mdp->event[0];
+ }
+
+ for (path_id = 0; path_id < MDP_DUAL_PIPE; path_id++) {
+ if (path_id != 0 && (!is_dual_pipe(scenario)))
+ break;
+
+ path[path_id].mdp_dev = mdp;
+ path[path_id].config = ¶m->config[path_id];
+ path[path_id].param = param->param;
+ for (i = 0; i < param->param->num_outputs; i++) {
+ path[path_id].bounds[i].left = 0;
+ path[path_id].bounds[i].top = 0;
+ path[path_id].bounds[i].width =
+ param->param->outputs[i].buffer.format.width;
+ path[path_id].bounds[i].height =
+ param->param->outputs[i].buffer.format.height;
+ path[path_id].composes[i] = param->composes[i] ?
+ param->composes[i] : &path[path_id].bounds[i];
+ }
+
+ ret = mdp_path_ctx_init(mdp, &path[path_id]);
+ if (ret) {
+ pr_info("%s mdp_path_ctx_init error at path %d\n", __func__, path_id);
+ goto err_destroy_pkt;
+ }
}
i = mdp_get_mutex_idx(mdp->mdp_data, MDP_PIPE_RDMA0);
@@ -852,44 +883,61 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param)
if (i >= 0)
mtk_mutex_prepare(mdp->mdp_mutex2[mdp->mdp_data->pipe_info[i].mutex_id]);
- for (i = 0; i < param->config->num_components; i++) {
- if (is_dummy_engine(mdp, path.config->components[i].type))
+ for (i = 0; i < param->config[PATH_0].num_components; i++) {
+ if (is_dummy_engine(mdp, path[PATH_0].config->components[i].type))
continue;
- mdp_comp_clock_on(&mdp->pdev->dev, path.comps[i].comp);
+ mdp_comp_clock_on(&mdp->pdev->dev, path[PATH_0].comps[i].comp);
+ }
+
+ if (is_dual_pipe(scenario)) {
+ for (i = 0; i < param->config[PATH_1].num_components; i++) {
+ if (is_dummy_engine(mdp, path[PATH_1].config->components[i].type))
+ continue;
+
+ mdp_comp_clock_on(&mdp->pdev->dev, path[PATH_1].comps[i].comp);
+ }
}
if (mdp->mdp_data->mdp_cfg->mdp_version_8195) {
/* HYFBC Patch */
- ret = mdp_hyfbc_config(mdp, &cmd, &path, param);
+ ret = mdp_hyfbc_config(mdp, &cmd, &path[PATH_0], param);
if (ret)
pr_info("%s:mdp_hyfbc_config fail!\n", __func__);
}
- ret = mdp_path_config(mdp, &cmd, &path);
+ ret = mdp_path_config(mdp, &cmd, &path[PATH_0]);
if (ret) {
- pr_info("%s mdp_path_config error\n", __func__);
+ pr_info("%s path 0 mdp_path_config error\n", __func__);
goto err_destroy_pkt;
}
+ if (is_dual_pipe(scenario)) {
+ ret = mdp_path_config(mdp, &cmd_d, &path[PATH_1]);
+ if (ret) {
+ pr_info("%s path 1 mdp_path_config error\n", __func__);
+ goto err_destroy_pkt;
+ }
+ }
+
cb_param = kzalloc(sizeof(*cb_param), GFP_KERNEL);
if (!cb_param) {
ret = -ENOMEM;
goto err_destroy_pkt;
}
- comps = kcalloc(param->config->num_components, sizeof(*comps),
+ comps = kcalloc(param->config[PATH_0].num_components, sizeof(*comps),
GFP_KERNEL);
if (!comps) {
ret = -ENOMEM;
goto err_destroy_pkt;
}
- for (i = 0; i < param->config->num_components; i++) {
- if (is_dummy_engine(mdp, path.config->components[i].type))
+ for (i = 0; i < param->config[PATH_0].num_components; i++) {
+ if (is_dummy_engine(mdp, path[PATH_0].config->components[i].type))
continue;
- memcpy(&comps[i], path.comps[i].comp,
+ memcpy(&comps[i], path[PATH_0].comps[i].comp,
sizeof(struct mdp_comp));
}
cb_param->mdp = mdp;
@@ -897,10 +945,49 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param)
cb_param->user_cb_data = param->cb_data;
cb_param->pkt = cmd.pkt;
cb_param->comps = comps;
- cb_param->num_comps = param->config->num_components;
+ cb_param->num_comps = param->config[PATH_0].num_components;
cb_param->mdp_ctx = param->mdp_ctx;
+ if (is_dual_pipe(scenario)) {
+ cb_param_d = kzalloc(sizeof(*cb_param_d), GFP_KERNEL);
+ if (!cb_param_d) {
+ ret = -ENOMEM;
+ goto err_destroy_pkt;
+ }
+ comps_d = kcalloc(param->config[PATH_1].num_components, sizeof(*comps_d),
+ GFP_KERNEL);
+ if (!comps_d) {
+ ret = -ENOMEM;
+ goto err_destroy_pkt;
+ }
+
+ for (i = 0; i < param->config[PATH_1].num_components; i++) {
+ if (is_dummy_engine(mdp, path[PATH_1].config->components[i].type))
+ continue;
+
+ memcpy(&comps_d[i], path[PATH_1].comps[i].comp,
+ sizeof(struct mdp_comp));
+ }
+ cb_param_d->mdp = mdp;
+ cb_param_d->user_cmdq_cb = param->cmdq_cb;
+ cb_param_d->user_cb_data = param->cb_data;
+ cb_param_d->pkt = cmd_d.pkt;
+ cb_param_d->comps = comps_d;
+ cb_param_d->num_comps = param->config[PATH_1].num_components;
+ cb_param_d->mdp_ctx = param->mdp_ctx;
+ }
+
+ if (atomic_read(&mdp->cmdq_count))
+ pr_info("%s: Warning: cmdq_count:%d !\n", __func__, atomic_read(&mdp->cmdq_count));
+
cmdq_pkt_finalize(cmd.pkt);
+ atomic_inc(&mdp->cmdq_count);
+
+ if (is_dual_pipe(scenario)) {
+ cmdq_pkt_finalize(cmd_d.pkt);
+ atomic_inc(&mdp->cmdq_count);
+ }
+
ret = cmdq_pkt_flush_async(cmd.pkt,
mdp_handle_cmdq_callback,
(void *)cb_param);
@@ -908,6 +995,16 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param)
dev_err(dev, "cmdq_pkt_flush_async fail!\n");
goto err_clock_off;
}
+
+ if (is_dual_pipe(scenario)) {
+ ret = cmdq_pkt_flush_async(cmd_d.pkt,
+ mdp_handle_cmdq_callback,
+ (void *)cb_param_d);
+ if (ret) {
+ dev_err(dev, "cmdq_dual_pkt_flush_async fail!\n");
+ goto err_clock_off;
+ }
+ }
return 0;
err_clock_off:
@@ -920,12 +1017,22 @@ int mdp_cmdq_send(struct mdp_dev *mdp, struct mdp_cmdq_param *param)
mdp_comp_clocks_off(&mdp->pdev->dev, cb_param->comps,
cb_param->num_comps);
+ if (cb_param_d)
+ mdp_comp_clocks_off(&mdp->pdev->dev, cb_param_d->comps,
+ cb_param_d->num_comps);
err_destroy_pkt:
cmdq_pkt_destroy(cmd.pkt);
+ if (is_dual_pipe(scenario)) {
+ cmdq_pkt_destroy(cmd_d.pkt);
+ atomic_inc(&mdp->cmdq_count);
+ }
atomic_dec(&mdp->job_count);
+ atomic_dec(&mdp->cmdq_count);
wake_up(&mdp->callback_wq);
kfree(comps);
+ kfree(comps_d);
kfree(cb_param);
+ kfree(cb_param_d);
return ret;
}
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.h
index 16933507333b..0a0e88cef6b5 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.h
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.h
@@ -37,6 +37,7 @@ struct mdp_cmdq_cb_param {
struct mdp_comp *comps;
u8 num_comps;
void *mdp_ctx;
+ bool finalize;
};
struct mdp_dev;
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c
index b167cec05815..090f4c1e03f7 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c
@@ -41,6 +41,7 @@ static const struct mdp_platform_config mt8195_plat_cfg = {
.tdshp_dyn_contrast_version = 2,
.mdp_version_8195 = true,
.mdp_version_6885 = true,
+ .support_dual_pipe = true,
.gce_event_offset = 0,
};
@@ -1263,6 +1264,12 @@ static int mdp_probe(struct platform_device *pdev)
goto err_put_scp;
}
+ mdp->cmdq_d_clt = cmdq_mbox_create(dev, 1);
+ if (IS_ERR(mdp->cmdq_d_clt)) {
+ ret = PTR_ERR(mdp->cmdq_d_clt);
+ goto err_mbox_destroy;
+ }
+
init_waitqueue_head(&mdp->callback_wq);
ida_init(&mdp->mdp_ida);
platform_set_drvdata(pdev, mdp);
@@ -1273,7 +1280,7 @@ static int mdp_probe(struct platform_device *pdev)
if (ret) {
dev_err(dev, "Failed to register v4l2 device\n");
ret = -EINVAL;
- goto err_mbox_destroy;
+ goto err_dual_mbox_destroy;
}
ret = mdp_m2m_device_register(mdp);
@@ -1287,6 +1294,8 @@ static int mdp_probe(struct platform_device *pdev)
err_unregister_device:
v4l2_device_unregister(&mdp->v4l2_dev);
+err_dual_mbox_destroy:
+ cmdq_mbox_destroy(mdp->cmdq_d_clt);
err_mbox_destroy:
cmdq_mbox_destroy(mdp->cmdq_clt);
err_put_scp:
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
index 0b072c33e4e8..4efab0fbfc6b 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
@@ -40,6 +40,7 @@ struct mdp_platform_config {
bool wrot_support_10bit;
bool mdp_version_6885;
bool mdp_version_8195;
+ bool support_dual_pipe;
u8 tdshp_dyn_contrast_version;
u32 gce_event_offset;
};
@@ -81,6 +82,7 @@ struct mdp_dev {
u32 id_count;
struct ida mdp_ida;
struct cmdq_client *cmdq_clt;
+ struct cmdq_client *cmdq_d_clt;
wait_queue_head_t callback_wq;
struct v4l2_device v4l2_dev;
@@ -90,6 +92,7 @@ struct mdp_dev {
struct mutex m2m_lock;
atomic_t suspended;
atomic_t job_count;
+ atomic_t cmdq_count;
};
struct mdp_pipe_info {
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c
index cbea2ef67625..a19b28548b62 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c
@@ -116,6 +116,10 @@ static void mdp_m2m_worker(struct work_struct *work)
frame = ctx_get_frame(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
src_vb = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
mdp_set_src_config(¶m.inputs[0], frame, &src_vb->vb2_buf);
+ mdp_set_scenario(ctx->mdp_dev, ¶m, frame);
+ if (param.frame_change)
+ dev_info(&ctx->mdp_dev->pdev->dev,
+ "MDP Scenario: %d\n", param.type);
frame = ctx_get_frame(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
dst_vb = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
@@ -420,7 +424,7 @@ static int mdp_m2m_streamon(struct file *file, void *fh,
return ret;
ret = mdp_vpu_ctx_init(&ctx->vpu, &ctx->mdp_dev->vpu,
- MDP_DEV_M2M);
+ MDP_DEV_M2M_2ND);
if (ret) {
dev_err(&ctx->mdp_dev->pdev->dev,
"VPU init failed %d\n", ret);
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c
index 91a35f8974f3..10d94672bc8d 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c
@@ -448,6 +448,22 @@ static u32 mdp_fmt_get_plane_size(const struct mdp_format *fmt,
return 0;
}
+void mdp_set_scenario(struct mdp_dev *mdp,
+ struct img_ipi_frameparam *param,
+ struct mdp_frame *frame)
+{
+ u32 width = frame->format.fmt.pix_mp.width;
+ u32 height = frame->format.fmt.pix_mp.height;
+
+ if (!mdp)
+ return;
+
+ if (mdp->mdp_data->mdp_cfg->support_dual_pipe) {
+ if ((width * height) >= (2560 * 1440))
+ param->type = MDP_STREAM_TYPE_DUAL_BITBLT;
+ }
+}
+
static void mdp_prepare_buffer(struct img_image_buffer *b,
struct mdp_frame *frame, struct vb2_buffer *vb)
{
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
index a82516152a60..2ce1afababe9 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
@@ -10,6 +10,7 @@
#include <linux/videodev2.h>
#include <media/videobuf2-core.h>
#include "mtk-img-ipi.h"
+#include "mtk-mdp3-cmdq.h"
/*
* MDP native color code
@@ -339,6 +340,9 @@ int mdp_try_crop(struct v4l2_rect *r, const struct v4l2_selection *s,
int mdp_check_scaling_ratio(const struct v4l2_rect *crop,
const struct v4l2_rect *compose, s32 rotation,
const struct mdp_limit *limit);
+void mdp_set_scenario(struct mdp_dev *mdp,
+ struct img_ipi_frameparam *param,
+ struct mdp_frame *frame);
void mdp_set_src_config(struct img_input *in,
struct mdp_frame *frame, struct vb2_buffer *vb);
void mdp_set_dst_config(struct img_output *out,
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.c b/drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.c
index f91d817ea379..db67a50afef5 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.c
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.c
@@ -10,7 +10,7 @@
#include "mtk-mdp3-core.h"
#define MDP_VPU_MESSAGE_TIMEOUT 500U
-#define vpu_alloc_size 0x600000
+#define vpu_alloc_size 0x7F8000
static inline struct mdp_dev *vpu_to_mdp(struct mdp_vpu_dev *vpu)
{
diff --git a/drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.h b/drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.h
index e831070b44d0..3140d2925a1a 100644
--- a/drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.h
+++ b/drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.h
@@ -39,6 +39,7 @@ struct mdp_ipi_deinit_msg {
enum mdp_config_id {
MDP_DEV_M2M = 0,
+ MDP_DEV_M2M_2ND = 1,
MDP_CONFIG_POOL_SIZE /* ALWAYS keep at the end */
};
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v1 4/9] dt-bindings: media: mediatek: mdp3: add additional function block yaml
2021-09-17 3:27 [PATCH v1 0/9] Add mdp support for mt8195 roy-cw.yeh
@ 2021-09-17 3:27 ` roy-cw.yeh
0 siblings, 0 replies; 9+ messages in thread
From: roy-cw.yeh @ 2021-09-17 3:27 UTC (permalink / raw)
To: river . cheng; +Cc: linux-mediatek, Roy-CW.Yeh
From: "Roy-CW.Yeh" <roy-cw.yeh@mediatek.com>
Add additional function block yaml in mt8195
Signed-off-by: Roy-CW.Yeh <roy-cw.yeh@mediatek.com>
---
.../bindings/arm/mediatek/mediatek,mmsys.yaml | 2 +
.../bindings/arm/mediatek/mediatek,mutex.yaml | 4 ++
.../bindings/media/mediatek,mdp3-aal.yaml | 62 +++++++++++++++++
.../bindings/media/mediatek,mdp3-color.yaml | 62 +++++++++++++++++
.../bindings/media/mediatek,mdp3-fg.yaml | 61 +++++++++++++++++
.../bindings/media/mediatek,mdp3-hdr.yaml | 61 +++++++++++++++++
.../bindings/media/mediatek,mdp3-merge.yaml | 62 +++++++++++++++++
.../bindings/media/mediatek,mdp3-ovl.yaml | 61 +++++++++++++++++
.../bindings/media/mediatek,mdp3-pad.yaml | 62 +++++++++++++++++
.../bindings/media/mediatek,mdp3-rdma.yaml | 22 +++++-
.../bindings/media/mediatek,mdp3-rsz.yaml | 2 +
.../bindings/media/mediatek,mdp3-split.yaml | 67 +++++++++++++++++++
.../bindings/media/mediatek,mdp3-stitch.yaml | 62 +++++++++++++++++
.../bindings/media/mediatek,mdp3-tcc.yaml | 62 +++++++++++++++++
.../bindings/media/mediatek,mdp3-tdshp.yaml | 61 +++++++++++++++++
.../bindings/media/mediatek,mdp3-wrot.yaml | 2 +
16 files changed, 713 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-aal.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-color.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-merge.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-ovl.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-pad.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-split.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index 679437ee2590..7b46b8156a12 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -33,6 +33,8 @@ properties:
- mediatek,mt8365-mmsys
- mediatek,mt8195-vdosys0
- mediatek,mt8195-vdosys1
+ - mediatek,mt8195-vppsys0
+ - mediatek,mt8195-vppsys1
- const: syscon
- items:
- const: mediatek,mt7623-mmsys
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mutex.yaml
index 1a1c049aa929..41dc1383131a 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mutex.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mutex.yaml
@@ -37,6 +37,10 @@ properties:
- const: mediatek,mt8192-disp-mutex
- items:
- const: mediatek,mt8195-disp-mutex
+ - items:
+ - const: mediatek,mt8195-vpp0-mutex
+ - items:
+ - const: mediatek,mt8195-vpp1-mutex
reg:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-aal.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-aal.yaml
new file mode 100644
index 000000000000..54535aac8942
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-aal.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-aal.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 AAL Device Tree Bindings
+
+maintainers:
+ - Daoyuan Huang <daoyuan.huang@mediatek.com>
+ - Moudy Ho <moudy.ho@mediatek.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components is responsible for backlight power saving
+ and sunlight visibility improving.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - mediatek,mt8195-mdp3-aal
+
+ mediatek,mdp3-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
+ description: |
+ HW index to distinguish same functionality modules.
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - mediatek,mdp3-id
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ mdp3_aal0: mdp_aal0@14005000 {
+ compatible = "mediatek,mt8195-mdp3-aal";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x14005000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x5000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_AAL>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-color.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-color.yaml
new file mode 100644
index 000000000000..4eba4505ed26
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-color.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-color.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 COLOR Device Tree Bindings
+
+maintainers:
+ - Daoyuan Huang <daoyuan.huang@mediatek.com>
+ - Moudy Ho <moudy.ho@mediatek.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to adjust hue, luma and saturation
+ to get better picture quality.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - mediatek,mt8195-mdp3-color
+
+ mediatek,mdp3-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
+ description: |
+ HW index to distinguish same functionality modules.
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - mediatek,mdp3-id
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ mdp3_color0: mdp_color0@14008000 {
+ compatible = "mediatek,mt8195-mdp3-color";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x14008000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x8000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml
new file mode 100644
index 000000000000..8a4ea694c44b
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-fg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 FG Device Tree Bindings
+
+maintainers:
+ - Daoyuan Huang <daoyuan.huang@mediatek.com>
+ - Moudy Ho <moudy.ho@mediatek.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to add film grain according to AV1 spec.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt8195-mdp3-fg
+
+ mediatek,mdp3-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
+ description: |
+ HW index to distinguish same functionality modules.
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - mediatek,mdp3-id
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ mdp3_fg0: mdp_fg0@14002000 {
+ compatible = "mediatek,mt8195-mdp3-fg";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x14002000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x2000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_FG>;
+ };
\ No newline at end of file
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml
new file mode 100644
index 000000000000..4330f2b79697
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-hdr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 HDR Device Tree Bindings
+
+maintainers:
+ - Daoyuan Huang <daoyuan.huang@mediatek.com>
+ - Moudy Ho <moudy.ho@mediatek.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to perform HDR to SDR
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt8195-mdp3-hdr
+
+ mediatek,mdp3-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
+ description: |
+ HW index to distinguish same functionality modules.
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - mediatek,mdp3-id
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ mdp3_hdr0: mdp_hdr0@14004000
+ compatible = "mediatek,mt8195-mdp3-hdr";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x14004000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x4000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_HDR>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-merge.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-merge.yaml
new file mode 100644
index 000000000000..1e48a4636588
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-merge.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-merge.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 MERGE Device Tree Bindings
+
+maintainers:
+ - Daoyuan Huang <daoyuan.huang@mediatek.com>
+ - Moudy Ho <moudy.ho@mediatek.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to merge
+ two slice-per-line inputs into one side-by-side output.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - mediatek,mt8195-mdp3-merge
+
+ mediatek,mdp3-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
+ description: |
+ HW index to distinguish same functionality modules.
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - mediatek,mdp3-id
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ svpp2_mdp3_merge: svpp2_mdp_merge@14f1a000 {
+ compatible = "mediatek,mt8195-mdp3-merge";
+ mediatek,mdp3-id = <2>;
+ reg = <0 0x14f1a000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_14f1XXXX 0xa000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-ovl.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-ovl.yaml
new file mode 100644
index 000000000000..4e503d79758b
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-ovl.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-ovl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 OVL Device Tree Bindings
+
+maintainers:
+ - Daoyuan Huang <daoyuan.huang@mediatek.com>
+ - Moudy Ho <moudy.ho@mediatek.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to perform alpha blending from the memory.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - mediatek,mt8195-mdp3-ovl
+
+ mediatek,mdp3-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
+ description: |
+ HW index to distinguish same functionality modules.
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - mediatek,mdp3-id
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ mdp3_ovl0: mdp_ovl0@14009000 {
+ compatible = "mediatek,mt8195-mdp3-ovl";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x14009000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x9000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_OVL>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-pad.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-pad.yaml
new file mode 100644
index 000000000000..1f990c5ce6ab
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-pad.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-pad.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 PADDING Device Tree Bindings
+
+maintainers:
+ - Daoyuan Huang <daoyuan.huang@mediatek.com>
+ - Moudy Ho <moudy.ho@mediatek.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to insert
+ pre-defined color or alpha value to arbitrary side of image.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - mediatek,mt8195-mdp3-pad
+
+ mediatek,mdp3-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
+ description: |
+ HW index to distinguish same functionality modules.
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - mediatek,mdp3-id
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ mdp3_pad0: mdp_pad0@1400a000 {
+ compatible = "mediatek,mt8195-mdp3-pad";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x1400a000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0xa000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_PADDING>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
index b355d7fe791e..ce023d9fbef7 100644
--- a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
@@ -20,14 +20,16 @@ properties:
oneOf:
- items:
- enum:
- # controller node
- mediatek,mt8183-mdp3
+ - mediatek,mt8195-mdp3
- enum:
- mediatek,mt8183-mdp3-rdma
- items:
- - enum:
# read DMA
+ - enum:
+ - mediatek,mt8195-mdp3-rdma
+ - enum:
- mediatek,mt8183-mdp3-rdma
mediatek,scp:
@@ -55,12 +57,28 @@ properties:
- mediatek,mt8183-mdp3-dl1
- enum:
- mediatek,mt8183-mdp3-dl2
+ - enum:
+ - mediatek,mt8195-mdp3-dl1
+ - enum:
+ - mediatek,mt8195-mdp3-dl2
+ - enum:
+ - mediatek,mt8195-mdp3-dl3
+ - enum:
+ - mediatek,mt8195-mdp3-dl4
+ - enum:
+ - mediatek,mt8195-mdp3-dl5
+ - enum:
+ - mediatek,mt8195-mdp3-dl6
- enum:
# MDP direct-link output path selection, create a
# component for path connectedness of HW pipe control
- mediatek,mt8183-mdp3-path1
- enum:
- mediatek,mt8183-mdp3-path2
+ - enum:
+ - mediatek,mt8195-mdp3-path1
+ - enum:
+ - mediatek,mt8195-mdp3-path2
- enum:
# Input DMA of ISP PASS2 (DIP) module for raw image input
- mediatek,mt8183-mdp3-imgi
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
index c55a52cd32b7..eaa487ec58cc 100644
--- a/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
@@ -16,6 +16,8 @@ description: |
properties:
compatible:
items:
+ - enum:
+ - mediatek,mt8195-mdp3-rsz
- enum:
- mediatek,mt8183-mdp3-rsz
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-split.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-split.yaml
new file mode 100644
index 000000000000..40827d577f74
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-split.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-solit.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 SPLIT Device Tree Bindings
+
+maintainers:
+ - Daoyuan Huang <daoyuan.huang@mediatek.com>
+ - Moudy Ho <moudy.ho@mediatek.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to split hdmi rx into two stream
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - mediatek,mt8195-mdp3-split
+
+ mediatek,mdp3-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
+ description: |
+ HW index to distinguish same functionality modules.
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - mediatek,mdp3-id
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ vpp_split0: vpp_split0@14f06000 {
+ compatible = "mediatek,mt8195-mdp3-split";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x14f06000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_14f0XXXX 0x6000 0x1000>;
+ clocks = <&vppsys1 CLK_VPP1_VPP_SPLIT>,
+ <&vppsys1 CLK_VPP1_HDMI_META>,
+ <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>,
+ <&vppsys1 CLK_VPP1_DGI_IN>,
+ <&vppsys1 CLK_VPP1_DGI_OUT>,
+ <&vppsys1 CLK_VPP1_VPP_SPLIT_DGI>,
+ <&vppsys1 CLK_VPP1_VPP_SPLIT_26M>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml
new file mode 100644
index 000000000000..038a9519b2de
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-stitch.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 STITCH Device Tree Bindings
+
+maintainers:
+ - Daoyuan Huang <daoyuan.huang@mediatek.com>
+ - Moudy Ho <moudy.ho@mediatek.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to combine multiple video frame
+ with overlapping fields of view to produce a segmented panorame.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt8195-mdp3-stitch
+
+ mediatek,mdp3-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
+ description: |
+ HW index to distinguish same functionality modules.
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - mediatek,mdp3-id
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ mdp3_stitch0: mdp_stich0@14003000 {
+ compatible = "mediatek,mt8195-mdp3-stitch";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x14003000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x3000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_STITCH>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml
new file mode 100644
index 000000000000..63c147cb8d24
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-tcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 TCC Device Tree Bindings
+
+maintainers:
+ - Daoyuan Huang <daoyuan.huang@mediatek.com>
+ - Moudy Ho <moudy.ho@mediatek.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to support
+ HDR gamma curve conversion HDR displays.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - mediatek,mt8195-mdp3-tcc
+
+ mediatek,mdp3-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
+ description: |
+ HW index to distinguish same functionality modules.
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - mediatek,mdp3-id
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ mdp3_tcc0: mdp_tcc0@1400b000 {
+ compatible = "mediatek,mt8195-mdp3-tcc";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x1400b000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0xb000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_TCC>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml
new file mode 100644
index 000000000000..25b4668d93fc
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-tdshp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 TDSHP Device Tree Bindings
+
+maintainers:
+ - Daoyuan Huang <daoyuan.huang@mediatek.com>
+ - Moudy Ho <moudy.ho@mediatek.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to improve image sharpness and contrast.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt8195-mdp3-tdshp
+
+ mediatek,mdp3-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
+ description: |
+ HW index to distinguish same functionality modules.
+
+ reg:
+ maxItems: 1
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+required:
+ - compatible
+ - mediatek,mdp3-id
+ - reg
+ - mediatek,gce-client-reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+
+ mdp3_tdshp0: mdp_tdshp0@14007000 {
+ compatible = "mediatek,mt8195-mdp3-tdshp";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x14007000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1400XXXX 0x7000 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
index 2993da04c562..885e0f0f9e1f 100644
--- a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
@@ -16,6 +16,8 @@ description: |
properties:
compatible:
items:
+ - enum:
+ - mediatek,mt8195-mdp3-wrot
- enum:
- mediatek,mt8183-mdp3-wrot
--
2.18.0
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end of thread, other threads:[~2021-09-17 3:28 UTC | newest]
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-- links below jump to the message on this page --
2021-09-17 2:51 [PATCH v1 1/9] soc: mediatek: mmsys: expand MDP enum for chip independence architecture roy-cw.yeh
2021-09-17 2:51 ` [PATCH v1 2/9] soc: mediatek: mutex: expand parameter for mdp mutex function roy-cw.yeh
2021-09-17 2:51 ` [PATCH v1 3/9] media: platform: mtk-mdp3: add chip independence architecture roy-cw.yeh
2021-09-17 2:51 ` [PATCH v1 4/9] dt-bindings: media: mediatek: mdp3: add additional function block yaml roy-cw.yeh
2021-09-17 2:51 ` [PATCH v1 5/9] arm64: dts: mt8195: add mdp3 node roy-cw.yeh
2021-09-17 2:51 ` [PATCH v1 6/9] soc: mediatek: mmsys: support mt8195 vppsys0/1 roy-cw.yeh
2021-09-17 2:51 ` [PATCH v1 7/9] soc: mediatek: mutex: " roy-cw.yeh
2021-09-17 2:51 ` [PATCH v1 9/9] media: platform: mtk-mdp3: Add dual pipe feature support roy-cw.yeh
2021-09-17 3:27 [PATCH v1 0/9] Add mdp support for mt8195 roy-cw.yeh
2021-09-17 3:27 ` [PATCH v1 4/9] dt-bindings: media: mediatek: mdp3: add additional function block yaml roy-cw.yeh
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