All of lore.kernel.org
 help / color / mirror / Atom feed
* [Intel-gfx] [PATCH 0/2] Check SFC fusing on Xe_HP
@ 2021-09-17 16:12 Matt Roper
  2021-09-17 16:12 ` [Intel-gfx] [PATCH 1/2] drm/i915/xehp: Check new fuse bits for SFC availability Matt Roper
  2021-09-17 16:12 ` [Intel-gfx] [PATCH 2/2] drm/i915: Check SFC fusing before recording/dumping SFC_DONE Matt Roper
  0 siblings, 2 replies; 6+ messages in thread
From: Matt Roper @ 2021-09-17 16:12 UTC (permalink / raw)
  To: intel-gfx; +Cc: matthew.d.roper

Xe_HP adds some new fuse bits to indicate whether an SFC unit is fused
off.  We should utilize these when initializing VD/VE SFC access and
also when capturing/dumping SFC_DONE for the error state.

Matt Roper (2):
  drm/i915/xehp: Check new fuse bits for SFC availability
  drm/i915: Check SFC fusing before recording/dumping SFC_DONE

 drivers/gpu/drm/i915/gt/intel_engine_cs.c | 25 ++++++++++++++++++-----
 drivers/gpu/drm/i915/gt/intel_gt_types.h  |  3 +++
 drivers/gpu/drm/i915/gt/intel_sseu.c      |  5 ++---
 drivers/gpu/drm/i915/i915_gpu_error.c     |  6 ++++--
 drivers/gpu/drm/i915/i915_reg.h           |  4 ++--
 5 files changed, 31 insertions(+), 12 deletions(-)

-- 
2.33.0


^ permalink raw reply	[flat|nested] 6+ messages in thread
* [Intel-gfx] [PATCH 1/2] drm/i915/xehp: Check new fuse bits for SFC availability
  2021-09-17 16:12 [Intel-gfx] [PATCH 0/2] Check SFC fusing on Xe_HP Matt Roper
@ 2021-09-17 16:12 ` Matt Roper
  2021-09-17 17:39   ` Souza, Jose
  2021-09-17 16:12 ` [Intel-gfx] [PATCH 2/2] drm/i915: Check SFC fusing before recording/dumping SFC_DONE Matt Roper
  1 sibling, 1 reply; 6+ messages in thread
From: Matt Roper @ 2021-09-17 16:12 UTC (permalink / raw)
  To: intel-gfx; +Cc: matthew.d.roper, José Roberto de Souza

Xe_HP adds some new bits to the FUSE1 register to let us know whether a
given SFC unit is present.  We should take this into account while
initializing SFC availability to our VCS and VECS engines.

While we're at it, update the FUSE1 register definition to use
REG_GENMASK / REG_FIELD_GET notation.

Note that, the bspec confusingly names the fuse bits "disable" despite
the register reflecting the *enable* status of the SFC units.  The
original architecture documents which the bspec is based on do properly
name this field "SFC_ENABLE."

Bspec: 52543
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c | 25 ++++++++++++++++++-----
 drivers/gpu/drm/i915/gt/intel_gt_types.h  |  3 +++
 drivers/gpu/drm/i915/gt/intel_sseu.c      |  5 ++---
 drivers/gpu/drm/i915/i915_reg.h           |  4 ++--
 4 files changed, 27 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 332efea696a5..06dfe7f38953 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -398,7 +398,8 @@ static void __setup_engine_capabilities(struct intel_engine_cs *engine)
 			engine->uabi_capabilities |=
 				I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
 	} else if (engine->class == VIDEO_ENHANCEMENT_CLASS) {
-		if (GRAPHICS_VER(i915) >= 9)
+		if (GRAPHICS_VER(i915) >= 9 &&
+		    engine->gt->info.sfc_mask & BIT(engine->instance))
 			engine->uabi_capabilities |=
 				I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
 	}
@@ -474,18 +475,25 @@ void intel_engines_free(struct intel_gt *gt)
 }
 
 static
-bool gen11_vdbox_has_sfc(struct drm_i915_private *i915,
+bool gen11_vdbox_has_sfc(struct intel_gt *gt,
 			 unsigned int physical_vdbox,
 			 unsigned int logical_vdbox, u16 vdbox_mask)
 {
+	struct drm_i915_private *i915 = gt->i915;
+
 	/*
 	 * In Gen11, only even numbered logical VDBOXes are hooked
 	 * up to an SFC (Scaler & Format Converter) unit.
 	 * In Gen12, Even numbered physical instance always are connected
 	 * to an SFC. Odd numbered physical instances have SFC only if
 	 * previous even instance is fused off.
+	 *
+	 * Starting with Xe_HP, there's also a dedicated SFC_ENABLE field
+	 * in the fuse register that tells us whether a specific SFC is present.
 	 */
-	if (GRAPHICS_VER(i915) == 12)
+	if ((gt->info.sfc_mask & BIT(physical_vdbox / 2)) == 0)
+		return false;
+	else if (GRAPHICS_VER(i915) == 12)
 		return (physical_vdbox % 2 == 0) ||
 			!(BIT(physical_vdbox - 1) & vdbox_mask);
 	else if (GRAPHICS_VER(i915) == 11)
@@ -512,7 +520,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
 	struct intel_uncore *uncore = gt->uncore;
 	unsigned int logical_vdbox = 0;
 	unsigned int i;
-	u32 media_fuse;
+	u32 media_fuse, fuse1;
 	u16 vdbox_mask;
 	u16 vebox_mask;
 
@@ -534,6 +542,13 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
 	vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
 		      GEN11_GT_VEBOX_DISABLE_SHIFT;
 
+	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
+		fuse1 = intel_uncore_read(uncore, HSW_PAVP_FUSE1);
+		gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
+	} else {
+		gt->info.sfc_mask = ~0;
+	}
+
 	for (i = 0; i < I915_MAX_VCS; i++) {
 		if (!HAS_ENGINE(gt, _VCS(i))) {
 			vdbox_mask &= ~BIT(i);
@@ -546,7 +561,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
 			continue;
 		}
 
-		if (gen11_vdbox_has_sfc(i915, i, logical_vdbox, vdbox_mask))
+		if (gen11_vdbox_has_sfc(gt, i, logical_vdbox, vdbox_mask))
 			gt->info.vdbox_sfc_access |= BIT(i);
 		logical_vdbox++;
 	}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 6fdcde64c180..4492de7f79fd 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -184,6 +184,9 @@ struct intel_gt {
 
 		u8 num_engines;
 
+		/* General presence of SFC units */
+		u8 sfc_mask;
+
 		/* Media engine access to SFC per instance */
 		u8 vdbox_sfc_access;
 
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index b0e09b58005e..bdf09051b8a0 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -514,10 +514,9 @@ static void hsw_sseu_info_init(struct intel_gt *gt)
 	}
 
 	fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1);
-	switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) {
+	switch (REG_FIELD_GET(HSW_F1_EU_DIS_MASK, fuse1)) {
 	default:
-		MISSING_CASE((fuse1 & HSW_F1_EU_DIS_MASK) >>
-			     HSW_F1_EU_DIS_SHIFT);
+		MISSING_CASE(REG_FIELD_GET(HSW_F1_EU_DIS_MASK, fuse1));
 		fallthrough;
 	case HSW_F1_EU_DIS_10EUS:
 		sseu->eu_per_subslice = 10;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c2853cc005ee..280902bfa2ce 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3112,8 +3112,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 
 /* Fuse readout registers for GT */
 #define HSW_PAVP_FUSE1			_MMIO(0x911C)
-#define   HSW_F1_EU_DIS_SHIFT		16
-#define   HSW_F1_EU_DIS_MASK		(0x3 << HSW_F1_EU_DIS_SHIFT)
+#define   XEHP_SFC_ENABLE_MASK		REG_GENMASK(27, 24)
+#define   HSW_F1_EU_DIS_MASK		REG_GENMASK(17, 16)
 #define   HSW_F1_EU_DIS_10EUS		0
 #define   HSW_F1_EU_DIS_8EUS		1
 #define   HSW_F1_EU_DIS_6EUS		2
-- 
2.33.0


^ permalink raw reply related	[flat|nested] 6+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915: Check SFC fusing before recording/dumping SFC_DONE
  2021-09-17 16:12 [Intel-gfx] [PATCH 0/2] Check SFC fusing on Xe_HP Matt Roper
  2021-09-17 16:12 ` [Intel-gfx] [PATCH 1/2] drm/i915/xehp: Check new fuse bits for SFC availability Matt Roper
@ 2021-09-17 16:12 ` Matt Roper
  2021-09-17 17:40   ` Souza, Jose
  1 sibling, 1 reply; 6+ messages in thread
From: Matt Roper @ 2021-09-17 16:12 UTC (permalink / raw)
  To: intel-gfx; +Cc: matthew.d.roper, José Roberto de Souza

On Xe_HP and beyond the SFC unit may be fused off, even if the
corresponding media engines are present.  Check the SFC-specific fusing
before trying to dump the SFC_DONE instances.

Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/i915_gpu_error.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index b9f66dbd46bb..2a2d7643b551 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -753,7 +753,8 @@ static void err_print_gt(struct drm_i915_error_state_buf *m,
 			 * only exists if the corresponding VCS engine is
 			 * present.
 			 */
-			if (!HAS_ENGINE(gt->_gt, _VCS(i * 2)))
+			if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 ||
+			    !HAS_ENGINE(gt->_gt, _VCS(i * 2)))
 				continue;
 
 			err_printf(m, "  SFC_DONE[%d]: 0x%08x\n", i,
@@ -1632,7 +1633,8 @@ static void gt_record_regs(struct intel_gt_coredump *gt)
 			 * only exists if the corresponding VCS engine is
 			 * present.
 			 */
-			if (!HAS_ENGINE(gt->_gt, _VCS(i * 2)))
+			if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 ||
+			    !HAS_ENGINE(gt->_gt, _VCS(i * 2)))
 				continue;
 
 			gt->sfc_done[i] =
-- 
2.33.0


^ permalink raw reply related	[flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/xehp: Check new fuse bits for SFC availability
  2021-09-17 16:12 ` [Intel-gfx] [PATCH 1/2] drm/i915/xehp: Check new fuse bits for SFC availability Matt Roper
@ 2021-09-17 17:39   ` Souza, Jose
  0 siblings, 0 replies; 6+ messages in thread
From: Souza, Jose @ 2021-09-17 17:39 UTC (permalink / raw)
  To: Roper, Matthew D, intel-gfx

On Fri, 2021-09-17 at 09:12 -0700, Matt Roper wrote:
> Xe_HP adds some new bits to the FUSE1 register to let us know whether a
> given SFC unit is present.  We should take this into account while
> initializing SFC availability to our VCS and VECS engines.
> 
> While we're at it, update the FUSE1 register definition to use
> REG_GENMASK / REG_FIELD_GET notation.
> 
> Note that, the bspec confusingly names the fuse bits "disable" despite
> the register reflecting the *enable* status of the SFC units.  The
> original architecture documents which the bspec is based on do properly
> name this field "SFC_ENABLE."

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> Bspec: 52543
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_engine_cs.c | 25 ++++++++++++++++++-----
>  drivers/gpu/drm/i915/gt/intel_gt_types.h  |  3 +++
>  drivers/gpu/drm/i915/gt/intel_sseu.c      |  5 ++---
>  drivers/gpu/drm/i915/i915_reg.h           |  4 ++--
>  4 files changed, 27 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 332efea696a5..06dfe7f38953 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -398,7 +398,8 @@ static void __setup_engine_capabilities(struct intel_engine_cs *engine)
>  			engine->uabi_capabilities |=
>  				I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
>  	} else if (engine->class == VIDEO_ENHANCEMENT_CLASS) {
> -		if (GRAPHICS_VER(i915) >= 9)
> +		if (GRAPHICS_VER(i915) >= 9 &&
> +		    engine->gt->info.sfc_mask & BIT(engine->instance))
>  			engine->uabi_capabilities |=
>  				I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
>  	}
> @@ -474,18 +475,25 @@ void intel_engines_free(struct intel_gt *gt)
>  }
>  
>  static
> -bool gen11_vdbox_has_sfc(struct drm_i915_private *i915,
> +bool gen11_vdbox_has_sfc(struct intel_gt *gt,
>  			 unsigned int physical_vdbox,
>  			 unsigned int logical_vdbox, u16 vdbox_mask)
>  {
> +	struct drm_i915_private *i915 = gt->i915;
> +
>  	/*
>  	 * In Gen11, only even numbered logical VDBOXes are hooked
>  	 * up to an SFC (Scaler & Format Converter) unit.
>  	 * In Gen12, Even numbered physical instance always are connected
>  	 * to an SFC. Odd numbered physical instances have SFC only if
>  	 * previous even instance is fused off.
> +	 *
> +	 * Starting with Xe_HP, there's also a dedicated SFC_ENABLE field
> +	 * in the fuse register that tells us whether a specific SFC is present.
>  	 */
> -	if (GRAPHICS_VER(i915) == 12)
> +	if ((gt->info.sfc_mask & BIT(physical_vdbox / 2)) == 0)
> +		return false;
> +	else if (GRAPHICS_VER(i915) == 12)
>  		return (physical_vdbox % 2 == 0) ||
>  			!(BIT(physical_vdbox - 1) & vdbox_mask);
>  	else if (GRAPHICS_VER(i915) == 11)
> @@ -512,7 +520,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
>  	struct intel_uncore *uncore = gt->uncore;
>  	unsigned int logical_vdbox = 0;
>  	unsigned int i;
> -	u32 media_fuse;
> +	u32 media_fuse, fuse1;
>  	u16 vdbox_mask;
>  	u16 vebox_mask;
>  
> @@ -534,6 +542,13 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
>  	vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
>  		      GEN11_GT_VEBOX_DISABLE_SHIFT;
>  
> +	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
> +		fuse1 = intel_uncore_read(uncore, HSW_PAVP_FUSE1);
> +		gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
> +	} else {
> +		gt->info.sfc_mask = ~0;
> +	}
> +
>  	for (i = 0; i < I915_MAX_VCS; i++) {
>  		if (!HAS_ENGINE(gt, _VCS(i))) {
>  			vdbox_mask &= ~BIT(i);
> @@ -546,7 +561,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
>  			continue;
>  		}
>  
> -		if (gen11_vdbox_has_sfc(i915, i, logical_vdbox, vdbox_mask))
> +		if (gen11_vdbox_has_sfc(gt, i, logical_vdbox, vdbox_mask))
>  			gt->info.vdbox_sfc_access |= BIT(i);
>  		logical_vdbox++;
>  	}
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> index 6fdcde64c180..4492de7f79fd 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
> @@ -184,6 +184,9 @@ struct intel_gt {
>  
>  		u8 num_engines;
>  
> +		/* General presence of SFC units */
> +		u8 sfc_mask;
> +
>  		/* Media engine access to SFC per instance */
>  		u8 vdbox_sfc_access;
>  
> diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
> index b0e09b58005e..bdf09051b8a0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_sseu.c
> +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
> @@ -514,10 +514,9 @@ static void hsw_sseu_info_init(struct intel_gt *gt)
>  	}
>  
>  	fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1);
> -	switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) {
> +	switch (REG_FIELD_GET(HSW_F1_EU_DIS_MASK, fuse1)) {
>  	default:
> -		MISSING_CASE((fuse1 & HSW_F1_EU_DIS_MASK) >>
> -			     HSW_F1_EU_DIS_SHIFT);
> +		MISSING_CASE(REG_FIELD_GET(HSW_F1_EU_DIS_MASK, fuse1));
>  		fallthrough;
>  	case HSW_F1_EU_DIS_10EUS:
>  		sseu->eu_per_subslice = 10;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c2853cc005ee..280902bfa2ce 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3112,8 +3112,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>  
>  /* Fuse readout registers for GT */
>  #define HSW_PAVP_FUSE1			_MMIO(0x911C)
> -#define   HSW_F1_EU_DIS_SHIFT		16
> -#define   HSW_F1_EU_DIS_MASK		(0x3 << HSW_F1_EU_DIS_SHIFT)
> +#define   XEHP_SFC_ENABLE_MASK		REG_GENMASK(27, 24)
> +#define   HSW_F1_EU_DIS_MASK		REG_GENMASK(17, 16)
>  #define   HSW_F1_EU_DIS_10EUS		0
>  #define   HSW_F1_EU_DIS_8EUS		1
>  #define   HSW_F1_EU_DIS_6EUS		2


^ permalink raw reply	[flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915: Check SFC fusing before recording/dumping SFC_DONE
  2021-09-17 16:12 ` [Intel-gfx] [PATCH 2/2] drm/i915: Check SFC fusing before recording/dumping SFC_DONE Matt Roper
@ 2021-09-17 17:40   ` Souza, Jose
  0 siblings, 0 replies; 6+ messages in thread
From: Souza, Jose @ 2021-09-17 17:40 UTC (permalink / raw)
  To: Roper, Matthew D, intel-gfx

On Fri, 2021-09-17 at 09:12 -0700, Matt Roper wrote:
> On Xe_HP and beyond the SFC unit may be fused off, even if the
> corresponding media engines are present.  Check the SFC-specific fusing
> before trying to dump the SFC_DONE instances.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gpu_error.c | 6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
> index b9f66dbd46bb..2a2d7643b551 100644
> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
> @@ -753,7 +753,8 @@ static void err_print_gt(struct drm_i915_error_state_buf *m,
>  			 * only exists if the corresponding VCS engine is
>  			 * present.
>  			 */
> -			if (!HAS_ENGINE(gt->_gt, _VCS(i * 2)))
> +			if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 ||
> +			    !HAS_ENGINE(gt->_gt, _VCS(i * 2)))
>  				continue;
>  
>  			err_printf(m, "  SFC_DONE[%d]: 0x%08x\n", i,
> @@ -1632,7 +1633,8 @@ static void gt_record_regs(struct intel_gt_coredump *gt)
>  			 * only exists if the corresponding VCS engine is
>  			 * present.
>  			 */
> -			if (!HAS_ENGINE(gt->_gt, _VCS(i * 2)))
> +			if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 ||
> +			    !HAS_ENGINE(gt->_gt, _VCS(i * 2)))
>  				continue;
>  
>  			gt->sfc_done[i] =


^ permalink raw reply	[flat|nested] 6+ messages in thread
* [Intel-gfx] [PATCH 1/2] drm/i915/xehp: Check new fuse bits for SFC availability
  2021-09-17 16:14 [PATCH 0/2] Check SFC fusing on Xe_HP Matt Roper
@ 2021-09-17 16:14 ` Matt Roper
  0 siblings, 0 replies; 6+ messages in thread
From: Matt Roper @ 2021-09-17 16:14 UTC (permalink / raw)
  To: intel-gfx; +Cc: dri-devel, matthew.d.roper, José Roberto de Souza

Xe_HP adds some new bits to the FUSE1 register to let us know whether a
given SFC unit is present.  We should take this into account while
initializing SFC availability to our VCS and VECS engines.

While we're at it, update the FUSE1 register definition to use
REG_GENMASK / REG_FIELD_GET notation.

Note that, the bspec confusingly names the fuse bits "disable" despite
the register reflecting the *enable* status of the SFC units.  The
original architecture documents which the bspec is based on do properly
name this field "SFC_ENABLE."

Bspec: 52543
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c | 25 ++++++++++++++++++-----
 drivers/gpu/drm/i915/gt/intel_gt_types.h  |  3 +++
 drivers/gpu/drm/i915/gt/intel_sseu.c      |  5 ++---
 drivers/gpu/drm/i915/i915_reg.h           |  4 ++--
 4 files changed, 27 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 332efea696a5..06dfe7f38953 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -398,7 +398,8 @@ static void __setup_engine_capabilities(struct intel_engine_cs *engine)
 			engine->uabi_capabilities |=
 				I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
 	} else if (engine->class == VIDEO_ENHANCEMENT_CLASS) {
-		if (GRAPHICS_VER(i915) >= 9)
+		if (GRAPHICS_VER(i915) >= 9 &&
+		    engine->gt->info.sfc_mask & BIT(engine->instance))
 			engine->uabi_capabilities |=
 				I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
 	}
@@ -474,18 +475,25 @@ void intel_engines_free(struct intel_gt *gt)
 }
 
 static
-bool gen11_vdbox_has_sfc(struct drm_i915_private *i915,
+bool gen11_vdbox_has_sfc(struct intel_gt *gt,
 			 unsigned int physical_vdbox,
 			 unsigned int logical_vdbox, u16 vdbox_mask)
 {
+	struct drm_i915_private *i915 = gt->i915;
+
 	/*
 	 * In Gen11, only even numbered logical VDBOXes are hooked
 	 * up to an SFC (Scaler & Format Converter) unit.
 	 * In Gen12, Even numbered physical instance always are connected
 	 * to an SFC. Odd numbered physical instances have SFC only if
 	 * previous even instance is fused off.
+	 *
+	 * Starting with Xe_HP, there's also a dedicated SFC_ENABLE field
+	 * in the fuse register that tells us whether a specific SFC is present.
 	 */
-	if (GRAPHICS_VER(i915) == 12)
+	if ((gt->info.sfc_mask & BIT(physical_vdbox / 2)) == 0)
+		return false;
+	else if (GRAPHICS_VER(i915) == 12)
 		return (physical_vdbox % 2 == 0) ||
 			!(BIT(physical_vdbox - 1) & vdbox_mask);
 	else if (GRAPHICS_VER(i915) == 11)
@@ -512,7 +520,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
 	struct intel_uncore *uncore = gt->uncore;
 	unsigned int logical_vdbox = 0;
 	unsigned int i;
-	u32 media_fuse;
+	u32 media_fuse, fuse1;
 	u16 vdbox_mask;
 	u16 vebox_mask;
 
@@ -534,6 +542,13 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
 	vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
 		      GEN11_GT_VEBOX_DISABLE_SHIFT;
 
+	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
+		fuse1 = intel_uncore_read(uncore, HSW_PAVP_FUSE1);
+		gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
+	} else {
+		gt->info.sfc_mask = ~0;
+	}
+
 	for (i = 0; i < I915_MAX_VCS; i++) {
 		if (!HAS_ENGINE(gt, _VCS(i))) {
 			vdbox_mask &= ~BIT(i);
@@ -546,7 +561,7 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
 			continue;
 		}
 
-		if (gen11_vdbox_has_sfc(i915, i, logical_vdbox, vdbox_mask))
+		if (gen11_vdbox_has_sfc(gt, i, logical_vdbox, vdbox_mask))
 			gt->info.vdbox_sfc_access |= BIT(i);
 		logical_vdbox++;
 	}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 6fdcde64c180..4492de7f79fd 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -184,6 +184,9 @@ struct intel_gt {
 
 		u8 num_engines;
 
+		/* General presence of SFC units */
+		u8 sfc_mask;
+
 		/* Media engine access to SFC per instance */
 		u8 vdbox_sfc_access;
 
diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c
index b0e09b58005e..bdf09051b8a0 100644
--- a/drivers/gpu/drm/i915/gt/intel_sseu.c
+++ b/drivers/gpu/drm/i915/gt/intel_sseu.c
@@ -514,10 +514,9 @@ static void hsw_sseu_info_init(struct intel_gt *gt)
 	}
 
 	fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1);
-	switch ((fuse1 & HSW_F1_EU_DIS_MASK) >> HSW_F1_EU_DIS_SHIFT) {
+	switch (REG_FIELD_GET(HSW_F1_EU_DIS_MASK, fuse1)) {
 	default:
-		MISSING_CASE((fuse1 & HSW_F1_EU_DIS_MASK) >>
-			     HSW_F1_EU_DIS_SHIFT);
+		MISSING_CASE(REG_FIELD_GET(HSW_F1_EU_DIS_MASK, fuse1));
 		fallthrough;
 	case HSW_F1_EU_DIS_10EUS:
 		sseu->eu_per_subslice = 10;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c2853cc005ee..280902bfa2ce 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3112,8 +3112,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 
 /* Fuse readout registers for GT */
 #define HSW_PAVP_FUSE1			_MMIO(0x911C)
-#define   HSW_F1_EU_DIS_SHIFT		16
-#define   HSW_F1_EU_DIS_MASK		(0x3 << HSW_F1_EU_DIS_SHIFT)
+#define   XEHP_SFC_ENABLE_MASK		REG_GENMASK(27, 24)
+#define   HSW_F1_EU_DIS_MASK		REG_GENMASK(17, 16)
 #define   HSW_F1_EU_DIS_10EUS		0
 #define   HSW_F1_EU_DIS_8EUS		1
 #define   HSW_F1_EU_DIS_6EUS		2
-- 
2.33.0


^ permalink raw reply related	[flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-09-17 17:41 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-09-17 16:12 [Intel-gfx] [PATCH 0/2] Check SFC fusing on Xe_HP Matt Roper
2021-09-17 16:12 ` [Intel-gfx] [PATCH 1/2] drm/i915/xehp: Check new fuse bits for SFC availability Matt Roper
2021-09-17 17:39   ` Souza, Jose
2021-09-17 16:12 ` [Intel-gfx] [PATCH 2/2] drm/i915: Check SFC fusing before recording/dumping SFC_DONE Matt Roper
2021-09-17 17:40   ` Souza, Jose
2021-09-17 16:14 [PATCH 0/2] Check SFC fusing on Xe_HP Matt Roper
2021-09-17 16:14 ` [Intel-gfx] [PATCH 1/2] drm/i915/xehp: Check new fuse bits for SFC availability Matt Roper

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.