[PATCH i-g-t v11 00/15] Introduce PXP Test

[PATCH i-g-t v11 00/15] Introduce PXP Test

[Alan Previn]

This series adds gem_pxp tests for the new PXP subsystem currently
being reviewed at https://patchwork.freedesktop.org/series/90504/.
This series currently includes 4 groups of tests addressing the
features and restrictions described by Daniele's series :
   1. test i915 interfaces for allocation of protected bo's
      and contexts and enforcement of UAPI rule disallowing the
      modification of parameters after it's been created.
   2. verify PXP subsystem protected sessions generate encrypted
      content on protected output buffers and decrypt protected
      inputs buffers.
   3. verify i915 PXP auto-teardown succeeds on suspend-resume
      cycles and gem-exec of stale protected assets fail. Ensure
      protected-contexts adhere to stricter invalidation
      enforcement upon teardown event.
   4. Ensure that display plane decryption works as expected with
      protected buffers.

NOTE: This series is on the tenth revision. All R-v-b's have been
received except UAPI patch which will be dropped at merge time (after
kernel patches gets merged and igt's drm UAPI gets sync'd).

Changes from prior rev1 to now:
   v11:
      - When detecting hw support, retry pxp context creation
        multiple times a timeout as per HW SLA.
      - initialize bo or ctx handles to zero before calling
        creation ioctl wrapper.
   v10:
      - In patch #2, reuse existing gem_create_ext wrapper.
      - In patch #10, kernel side changed the debugfs file name
        (but no difference in behavior / usage).
      - Removed patch #14 from Rev9 as decision on kernel side
        was to drop the usage of RESET_STATS IOCTL to track
        invalidated pxp contexts.
   v9:
      - Remove patch #2 from rev7 as it was duplicating
        an existing ioctl wrapper helper
      - Fix the false-negative warnings when triggering
        auto-suspend-resume (remove checking if we are
        suspending after the system has already resumed).
   v8:
      - Nothing - mistaken detection from patchwork
   v7:
      - In prior rev, Patches #11->13 was testing expected results
        from calling gem_execbuf with stale pxp-context, pxp-buffer
        or combinations of them (including an opt-out usage). All
        of them used a single suspend-resume power state cycles to
        trigger the PXP teardown event. These patches have been
        combined into patch #14 that continues to carry the prior rev
        Rvb.
      - In its place, the new patches of #11->#13 do the identical
        set of tests as before (results from gem_execbuf with various
        combinations of stale pxp context and buffer), but this time
        using a debugfs file handle that triggers the same code path
        taken when the HW triggers the pxp teardown. That said, the
        code is nearly identical as v6 but I did not keep the Rvb's.
      - In patch #15, RESET_STAT now reports invalidated / banned
        pxp contexts via the existing batch_active's lost count.
   v6:
      - Addressed rev5 review comments for patch #1, #7, #14
        and #17.
      - For #17, I'm using Rodrigo's Rv-b because offline 
        discussions concluded that we couldn't use those
        test sequences with HDCP and so it was removed it.
      - Added Rv-b into all patches that received it.
      - Modified the test requirement from a list of device
        ids to checking if runtime PXP interface succeeds
        due to kernel's build config dependency.
   v5:
      - Addressed all rev4 review comments. No changes to
        overall flow and logic compared to the last rev.
   v4:
      - Addressed all rev3 review comments. NOTE: that all
        test cases and code logic are the same but a decent
        amount of refactoring has occured due to address
        v3 comments to break out subtests into separate
        functions while combining certain checks into the same
        function to reduce test time by minimizing number of
        suspend-resume power cycles.
   v3:
      - Addressed all rev2 review comments.
      - In line with one of the rev2 comments, a thorough fixup
        of all line-breaks in function calls was made for a more
        consistent styling.
      - Rebased on igt upstream repo and updated to latest kernel
        UAPI that added GEM_CREATE_EXT.
   v2: 
      - Addressed all rev1 review comments except these:
           1.Chris Wilson : "...have the caller do 1-3 once for its protected
             context. Call it something like intel_bb_enable_pxp(),
             intel_bb_set_pxp if it should be reversible.".
             -  This couldn't be implemented because [1] HW needs different
             instruction sequences for enabling/disabling PXP depending
             on the engine class and [2] the pair of "pxp-enable" and "pxp-
             disable" instructions need to be contained within the same batch
             that is dispatched to the hardware. That said, implementing
             internal intel_batchbuffer funtionality for this would conflict
             with how rendercopy_gen9 uses batch buffer memory by repositioing
             the pointer and consuming unused portions of the batch buffer as
             3d state offsets that batchbuffer has no visibility.
         
      - Added these additional subtests:
           1. verify that buffer sharing works across testing pxp context.
           2. verify teardown bans contexts via DRM_IOCTL_I915_GET_RESET_STAT.
           3. verify display plane decryption of protected buffers.

Alan Previn (14):
  Add PXP UAPI support in i915_drm.h
  Add basic PXP testing of buffer and context alloc
  Perform a regular 3d copy as a control checkpoint
  Add PXP attribute support in batchbuffer and buffer_ops libs
  Add MI_SET_APPID instruction definition
  Enable protected session cmd in gen12_render_copyfunc
  Add subtest to copy raw source to protected dest
  Add test where both src and dest are protected
  Verify PXP teardown occurred through suspend-resume
  Verify execbuf fails with stale PXP context after teardown
  Verify execbuf fails with stale PXP buffer after teardown
  Verify execbuf ok with stale PXP buf in opt-out use
  Verify execution behavior with stale PXP assets through suspend-resume
  Verify protected surfaces are dma buffer sharable

Karthik B S (1):
  tests/i915_pxp: CRC validation for display tests.

 lib/i915/i915_drm_local.h |  102 +++
 lib/intel_batchbuffer.c   |   23 +-
 lib/intel_batchbuffer.h   |   31 +
 lib/intel_bufops.h        |   15 +
 lib/intel_reg.h           |    8 +
 lib/rendercopy_gen9.c     |   57 ++
 tests/i915/gem_pxp.c      | 1283 +++++++++++++++++++++++++++++++++++++
 tests/meson.build         |    1 +
 8 files changed, 1519 insertions(+), 1 deletion(-)
 create mode 100644 tests/i915/gem_pxp.c

-- 
2.25.1

[igt-dev] [PATCH i-g-t v11 00/15] Introduce PXP Test

[Alan Previn]

This series adds gem_pxp tests for the new PXP subsystem currently
being reviewed at https://patchwork.freedesktop.org/series/90504/.
This series currently includes 4 groups of tests addressing the
features and restrictions described by Daniele's series :
   1. test i915 interfaces for allocation of protected bo's
      and contexts and enforcement of UAPI rule disallowing the
      modification of parameters after it's been created.
   2. verify PXP subsystem protected sessions generate encrypted
      content on protected output buffers and decrypt protected
      inputs buffers.
   3. verify i915 PXP auto-teardown succeeds on suspend-resume
      cycles and gem-exec of stale protected assets fail. Ensure
      protected-contexts adhere to stricter invalidation
      enforcement upon teardown event.
   4. Ensure that display plane decryption works as expected with
      protected buffers.

NOTE: This series is on the tenth revision. All R-v-b's have been
received except UAPI patch which will be dropped at merge time (after
kernel patches gets merged and igt's drm UAPI gets sync'd).

Changes from prior rev1 to now:
   v11:
      - When detecting hw support, retry pxp context creation
        multiple times a timeout as per HW SLA.
      - initialize bo or ctx handles to zero before calling
        creation ioctl wrapper.
   v10:
      - In patch #2, reuse existing gem_create_ext wrapper.
      - In patch #10, kernel side changed the debugfs file name
        (but no difference in behavior / usage).
      - Removed patch #14 from Rev9 as decision on kernel side
        was to drop the usage of RESET_STATS IOCTL to track
        invalidated pxp contexts.
   v9:
      - Remove patch #2 from rev7 as it was duplicating
        an existing ioctl wrapper helper
      - Fix the false-negative warnings when triggering
        auto-suspend-resume (remove checking if we are
        suspending after the system has already resumed).
   v8:
      - Nothing - mistaken detection from patchwork
   v7:
      - In prior rev, Patches #11->13 was testing expected results
        from calling gem_execbuf with stale pxp-context, pxp-buffer
        or combinations of them (including an opt-out usage). All
        of them used a single suspend-resume power state cycles to
        trigger the PXP teardown event. These patches have been
        combined into patch #14 that continues to carry the prior rev
        Rvb.
      - In its place, the new patches of #11->#13 do the identical
        set of tests as before (results from gem_execbuf with various
        combinations of stale pxp context and buffer), but this time
        using a debugfs file handle that triggers the same code path
        taken when the HW triggers the pxp teardown. That said, the
        code is nearly identical as v6 but I did not keep the Rvb's.
      - In patch #15, RESET_STAT now reports invalidated / banned
        pxp contexts via the existing batch_active's lost count.
   v6:
      - Addressed rev5 review comments for patch #1, #7, #14
        and #17.
      - For #17, I'm using Rodrigo's Rv-b because offline 
        discussions concluded that we couldn't use those
        test sequences with HDCP and so it was removed it.
      - Added Rv-b into all patches that received it.
      - Modified the test requirement from a list of device
        ids to checking if runtime PXP interface succeeds
        due to kernel's build config dependency.
   v5:
      - Addressed all rev4 review comments. No changes to
        overall flow and logic compared to the last rev.
   v4:
      - Addressed all rev3 review comments. NOTE: that all
        test cases and code logic are the same but a decent
        amount of refactoring has occured due to address
        v3 comments to break out subtests into separate
        functions while combining certain checks into the same
        function to reduce test time by minimizing number of
        suspend-resume power cycles.
   v3:
      - Addressed all rev2 review comments.
      - In line with one of the rev2 comments, a thorough fixup
        of all line-breaks in function calls was made for a more
        consistent styling.
      - Rebased on igt upstream repo and updated to latest kernel
        UAPI that added GEM_CREATE_EXT.
   v2: 
      - Addressed all rev1 review comments except these:
           1.Chris Wilson : "...have the caller do 1-3 once for its protected
             context. Call it something like intel_bb_enable_pxp(),
             intel_bb_set_pxp if it should be reversible.".
             -  This couldn't be implemented because [1] HW needs different
             instruction sequences for enabling/disabling PXP depending
             on the engine class and [2] the pair of "pxp-enable" and "pxp-
             disable" instructions need to be contained within the same batch
             that is dispatched to the hardware. That said, implementing
             internal intel_batchbuffer funtionality for this would conflict
             with how rendercopy_gen9 uses batch buffer memory by repositioing
             the pointer and consuming unused portions of the batch buffer as
             3d state offsets that batchbuffer has no visibility.
         
      - Added these additional subtests:
           1. verify that buffer sharing works across testing pxp context.
           2. verify teardown bans contexts via DRM_IOCTL_I915_GET_RESET_STAT.
           3. verify display plane decryption of protected buffers.

Alan Previn (14):
  Add PXP UAPI support in i915_drm.h
  Add basic PXP testing of buffer and context alloc
  Perform a regular 3d copy as a control checkpoint
  Add PXP attribute support in batchbuffer and buffer_ops libs
  Add MI_SET_APPID instruction definition
  Enable protected session cmd in gen12_render_copyfunc
  Add subtest to copy raw source to protected dest
  Add test where both src and dest are protected
  Verify PXP teardown occurred through suspend-resume
  Verify execbuf fails with stale PXP context after teardown
  Verify execbuf fails with stale PXP buffer after teardown
  Verify execbuf ok with stale PXP buf in opt-out use
  Verify execution behavior with stale PXP assets through suspend-resume
  Verify protected surfaces are dma buffer sharable

Karthik B S (1):
  tests/i915_pxp: CRC validation for display tests.

 lib/i915/i915_drm_local.h |  102 +++
 lib/intel_batchbuffer.c   |   23 +-
 lib/intel_batchbuffer.h   |   31 +
 lib/intel_bufops.h        |   15 +
 lib/intel_reg.h           |    8 +
 lib/rendercopy_gen9.c     |   57 ++
 tests/i915/gem_pxp.c      | 1283 +++++++++++++++++++++++++++++++++++++
 tests/meson.build         |    1 +
 8 files changed, 1519 insertions(+), 1 deletion(-)
 create mode 100644 tests/i915/gem_pxp.c

-- 
2.25.1

[igt-dev] [PATCH i-g-t v11 01/15] Add PXP UAPI support in i915_drm.h

[Alan Previn]

PXP hasn't been merged into upstream kernel, so taking the
UAPI changes from the kernel patches and adding into
i915_drm_local.h for now.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
---
 lib/i915/i915_drm_local.h | 102 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 102 insertions(+)

diff --git a/lib/i915/i915_drm_local.h b/lib/i915/i915_drm_local.h
index dd646aed..fbb68d8a 100644
--- a/lib/i915/i915_drm_local.h
+++ b/lib/i915/i915_drm_local.h
@@ -20,6 +20,108 @@ extern "C" {
  * clean these up when kernel uapi headers are sync'd.
  */
 
+/*
+ * New PXP UAPI value for 'struct drm_i915_gem_context_param.param'
+ * I915_CONTEXT_PARAM_PROTECTED_CONTENT:
+ *
+ * Mark that the context makes use of protected content, which will result
+ * in the context being invalidated when the protected content session is.
+ * Given that the protected content session is killed on suspend, the device
+ * is kept awake for the lifetime of a protected context, so the user should
+ * make sure to dispose of them once done.
+ * This flag can only be set at context creation time and, when set to true,
+ * must be preceded by an explicit setting of I915_CONTEXT_PARAM_RECOVERABLE
+ * to false. This flag can't be set to true in conjunction with setting the
+ * I915_CONTEXT_PARAM_BANNABLE flag to false. Creation example:
+ *
+ * .. code-block:: C
+ *
+ *	struct drm_i915_gem_context_create_ext_setparam p_protected = {
+ *		.base = {
+ *			.name = I915_CONTEXT_CREATE_EXT_SETPARAM,
+ *		},
+ *		.param = {
+ *			.param = I915_CONTEXT_PARAM_PROTECTED_CONTENT,
+ *			.value = 1,
+ *		}
+ *	};
+ *	struct drm_i915_gem_context_create_ext_setparam p_norecover = {
+ *		.base = {
+ *			.name = I915_CONTEXT_CREATE_EXT_SETPARAM,
+ *			.next_extension = to_user_pointer(&p_protected),
+ *		},
+ *		.param = {
+ *			.param = I915_CONTEXT_PARAM_RECOVERABLE,
+ *			.value = 0,
+ *		}
+ *	};
+ *	struct drm_i915_gem_context_create_ext create = {
+ *		.flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
+ *		.extensions = to_user_pointer(&p_norecover);
+ *	};
+ *
+ *	ctx_id = gem_context_create_ext(drm_fd, &create);
+ *
+ * In addition to the normal failure cases, setting this flag during context
+ * creation can result in the following errors:
+ *
+ * -ENODEV: feature not available
+ * -EPERM: trying to mark a recoverable or not bannable context as protected
+ */
+#define I915_CONTEXT_PARAM_PROTECTED_CONTENT    0xd
+
+/*
+ * New PXP UAPI flag for 'struct drm_i915_gem_create_ext.flags'
+ *
+ * For I915_GEM_CREATE_EXT_PROTECTED_CONTENT usage see
+ * struct drm_i915_gem_create_ext_protected_content.
+ */
+#define I915_GEM_CREATE_EXT_PROTECTED_CONTENT 1
+
+/**
+ * struct drm_i915_gem_create_ext_protected_content - The
+ * I915_OBJECT_PARAM_PROTECTED_CONTENT extension.
+ *
+ * If this extension is provided, buffer contents are expected to be protected
+ * by PXP encryption and require decryption for scan out and processing. This
+ * is only possible on platforms that have PXP enabled, on all other scenarios
+ * using this extension will cause the ioctl to fail and return -ENODEV. The
+ * flags parameter is reserved for future expansion and must currently be set
+ * to zero.
+ *
+ * The buffer contents are considered invalid after a PXP session teardown.
+ *
+ * The encryption is guaranteed to be processed correctly only if the object
+ * is submitted with a context created using the
+ * I915_CONTEXT_PARAM_PROTECTED_CONTENT flag. This will also enable extra checks
+ * at submission time on the validity of the objects involved.
+ *
+ * Below is an example on how to create a protected object:
+ *
+ * .. code-block:: C
+ *
+ *      struct drm_i915_gem_create_ext_protected_content protected_ext = {
+ *              .base = { .name = I915_GEM_CREATE_EXT_PROTECTED_CONTENT },
+ *              .flags = 0,
+ *      };
+ *      struct drm_i915_gem_create_ext create_ext = {
+ *              .size = PAGE_SIZE,
+ *              .extensions = (uintptr_t)&protected_ext,
+ *      };
+ *
+ *      int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext);
+ *      if (err) ...
+ */
+struct drm_i915_gem_create_ext_protected_content {
+	/** @base: Extension link. See struct i915_user_extension. */
+	struct i915_user_extension base;
+	/** @flags: reserved for future usage, currently MBZ */
+	__u32 flags;
+};
+
+/* ID of the protected content session managed by i915 when PXP is active */
+#define I915_PROTECTED_CONTENT_DEFAULT_SESSION 0xf
+
 #if defined(__cplusplus)
 }
 #endif
-- 
2.25.1

[igt-dev] [PATCH i-g-t v11 02/15] Add basic PXP testing of buffer and context alloc

[Alan Previn]

Test PXP capability support as well as the allocation of protected
buffers and protected contexts.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 tests/i915/gem_pxp.c | 355 +++++++++++++++++++++++++++++++++++++++++++
 tests/meson.build    |   1 +
 2 files changed, 356 insertions(+)
 create mode 100644 tests/i915/gem_pxp.c

diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
new file mode 100644
index 00000000..c6083d0f
--- /dev/null
+++ b/tests/i915/gem_pxp.c
@@ -0,0 +1,355 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include "igt.h"
+#include "i915/gem.h"
+#include "i915/gem_create.h"
+
+IGT_TEST_DESCRIPTION("Test PXP that manages protected content through arbitrated HW-PXP-session");
+/* Note: PXP = "Protected Xe Path" */
+
+static int create_bo_ext(int i915, uint32_t size, bool protected_is_true, uint32_t *bo_out)
+{
+	int ret;
+	uint64_t size64 = size;
+	struct i915_user_extension *ext = NULL;
+
+	struct drm_i915_gem_create_ext_protected_content protected_ext = {
+		.base = { .name = I915_GEM_CREATE_EXT_PROTECTED_CONTENT },
+		.flags = 0,
+	};
+
+	if (protected_is_true)
+		ext = &protected_ext.base;
+
+	*bo_out = 0;
+	ret = __gem_create_ext(i915, &size64, bo_out, ext);
+
+	return ret;
+}
+
+static void test_bo_alloc_pxp_nohw(int i915)
+{
+	int ret;
+	uint32_t bo;
+
+	ret = create_bo_ext(i915, 4096, false, &bo);
+	igt_assert_eq(ret, 0);
+	gem_close(i915, bo);
+
+	ret = create_bo_ext(i915, 4096, true, &bo);
+	igt_assert_eq(ret, -ENODEV);
+	igt_assert_eq(bo, 0);
+}
+
+static void test_bo_alloc_pxp_off(int i915)
+{
+	int ret;
+	uint32_t bo;
+
+	ret = create_bo_ext(i915, 4096, false, &bo);
+	igt_assert_eq(ret, 0);
+	gem_close(i915, bo);
+}
+
+static void test_bo_alloc_pxp_on(int i915)
+{
+	int ret;
+	uint32_t bo;
+
+	ret = create_bo_ext(i915, 4096, true, &bo);
+	igt_assert_eq(ret, 0);
+	gem_close(i915, bo);
+}
+
+static int create_ctx_with_params(int i915, bool with_protected_param, bool protected_is_true,
+				  bool with_recoverable_param, bool recoverable_is_true,
+				  uint32_t *ctx_out)
+{
+	uint32_t flags = 0;
+	uint64_t extensions = 0;
+
+	struct drm_i915_gem_context_create_ext_setparam p_prot = {
+		.base = {
+			.name = I915_CONTEXT_CREATE_EXT_SETPARAM,
+			.next_extension = 0,
+		},
+		.param = {
+			.param = I915_CONTEXT_PARAM_PROTECTED_CONTENT,
+			.value = 0,
+		}
+	};
+	struct drm_i915_gem_context_create_ext_setparam p_norecover = {
+		.base = {
+			.name = I915_CONTEXT_CREATE_EXT_SETPARAM,
+			.next_extension = 0,
+		},
+		.param = {
+			.param = I915_CONTEXT_PARAM_RECOVERABLE,
+			.value = 0,
+		}
+	};
+
+	p_prot.param.value = protected_is_true;
+	p_norecover.param.value = recoverable_is_true;
+
+	if (with_protected_param && with_recoverable_param) {
+		p_norecover.base.next_extension = to_user_pointer(&(p_prot.base));
+		flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS;
+		extensions = to_user_pointer(&(p_norecover.base));
+	} else if (!with_protected_param && with_recoverable_param) {
+		p_norecover.base.next_extension = 0;
+		flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS;
+		extensions = to_user_pointer(&(p_norecover.base));
+	} else if (with_protected_param && !with_recoverable_param) {
+		p_prot.base.next_extension = 0;
+		flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS;
+		extensions = to_user_pointer(&(p_prot.base));
+	}
+
+	*ctx_out = 0;
+	return __gem_context_create_ext(i915, flags, extensions, ctx_out);
+
+}
+
+#define CHANGE_PARAM_PROTECTED 0x0001
+#define CHANGE_PARAM_RECOVERY 0x0002
+
+static int modify_ctx_param(int i915, uint32_t ctx_id, uint32_t param_mask, bool param_value)
+{
+	int ret;
+
+	struct drm_i915_gem_context_param ctx_param = {
+		.ctx_id = ctx_id,
+		.param = 0,
+		.value = 0,
+	};
+
+	if (param_mask == CHANGE_PARAM_PROTECTED) {
+		ctx_param.param = I915_CONTEXT_PARAM_PROTECTED_CONTENT;
+		ctx_param.value = (int)param_value;
+	} else if (param_mask == CHANGE_PARAM_RECOVERY) {
+		ctx_param.param = I915_CONTEXT_PARAM_RECOVERABLE;
+		ctx_param.value = (int)param_value;
+	}
+
+	ret = igt_ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM, &ctx_param);
+
+	return ret;
+}
+
+static int get_ctx_protected_param(int i915, uint32_t ctx_id)
+{
+	int ret;
+
+	struct drm_i915_gem_context_param ctx_param = {
+		.ctx_id = ctx_id,
+		.param = I915_CONTEXT_PARAM_PROTECTED_CONTENT,
+	};
+
+	ret = igt_ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, &ctx_param);
+	igt_assert_eq(ret, 0);
+
+	return ctx_param.value;
+}
+
+static int get_ctx_recovery_param(int i915, uint32_t ctx_id)
+{
+	int ret;
+
+	struct drm_i915_gem_context_param ctx_param = {
+		.ctx_id = ctx_id,
+		.param = I915_CONTEXT_PARAM_RECOVERABLE,
+	};
+
+	ret = igt_ioctl(i915, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, &ctx_param);
+	igt_assert_eq(ret, 0);
+
+	return ctx_param.value;
+}
+
+static bool is_pxp_hw_supported(int i915)
+{
+	uint32_t tmpctx;
+	int i = 0, ret;
+
+	/* when running too soon after boot, its possible the component interface
+	 * between i915 and MEI may have not yet established, give it some time
+	 */
+	while (i++ < 50) {
+		ret = create_ctx_with_params(i915, true, true, true, false, &tmpctx);
+		if (ret == 0) {
+			gem_context_destroy(i915, tmpctx);
+			return true;
+		}
+		usleep(50*1000);
+	}
+	return false;
+}
+
+static void test_ctx_alloc_pxp_nohw(int i915)
+{
+	uint32_t ctx;
+
+	igt_assert_eq(create_ctx_with_params(i915, true, true, true, false, &ctx), -ENODEV);
+	igt_assert_eq(create_ctx_with_params(i915, true, false, true, false, &ctx), 0);
+	igt_assert_eq(get_ctx_protected_param(i915, ctx), 0);
+	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 0);
+	gem_context_destroy(i915, ctx);
+}
+
+static void test_ctx_alloc_recover_off_protect_off(int i915)
+{
+	uint32_t ctx;
+
+	igt_assert_eq(create_ctx_with_params(i915, true, false, true, false, &ctx), 0);
+	igt_assert_eq(get_ctx_protected_param(i915, ctx), 0);
+	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 0);
+	gem_context_destroy(i915, ctx);
+}
+
+static void test_ctx_alloc_recover_off_protect_on(int i915)
+{
+	uint32_t ctx;
+
+	igt_assert_eq(create_ctx_with_params(i915, true, true, true, false, &ctx), 0);
+	igt_assert_eq(get_ctx_protected_param(i915, ctx), 1);
+	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 0);
+	gem_context_destroy(i915, ctx);
+}
+
+static void test_ctx_alloc_recover_on_protect_off(int i915)
+{
+	uint32_t ctx;
+
+	igt_assert_eq(create_ctx_with_params(i915, true, false, true, true, &ctx), 0);
+	igt_assert_eq(get_ctx_protected_param(i915, ctx), 0);
+	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 1);
+	gem_context_destroy(i915, ctx);
+}
+
+static void test_ctx_alloc_recover_on_protect_on(int i915)
+{
+	uint32_t ctx;
+
+	igt_assert_eq(create_ctx_with_params(i915, true, true, true, true, &ctx), -EPERM);
+	igt_assert_eq(create_ctx_with_params(i915, true, true, false, false, &ctx), -EPERM);
+}
+
+static void test_ctx_mod_recover_off_to_on(int i915)
+{
+	uint32_t ctx;
+
+	igt_assert_eq(create_ctx_with_params(i915, true, true, true, false, &ctx), 0);
+	igt_assert_eq(get_ctx_protected_param(i915, ctx), 1);
+	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 0);
+	igt_assert_eq(modify_ctx_param(i915, ctx, CHANGE_PARAM_RECOVERY, true), -EPERM);
+	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 0);
+	gem_context_destroy(i915, ctx);
+}
+
+static void test_ctx_mod_protected_on_to_off(int i915)
+{
+	uint32_t ctx;
+
+	igt_assert_eq(create_ctx_with_params(i915, true, true, true, false, &ctx), 0);
+	igt_assert_eq(get_ctx_protected_param(i915, ctx), 1);
+	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 0);
+	igt_assert_eq(modify_ctx_param(i915, ctx, CHANGE_PARAM_PROTECTED, false), -EPERM);
+	igt_assert_eq(get_ctx_protected_param(i915, ctx), 1);
+	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 0);
+	gem_context_destroy(i915, ctx);
+}
+
+static void test_ctx_mod_protected_to_all_invalid(int i915)
+{
+	uint32_t ctx;
+
+	igt_assert_eq(create_ctx_with_params(i915, true, true, true, false, &ctx), 0);
+	igt_assert_eq(get_ctx_protected_param(i915, ctx), 1);
+	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 0);
+	igt_assert_eq(modify_ctx_param(i915, ctx, CHANGE_PARAM_RECOVERY, true), -EPERM);
+	igt_assert_eq(modify_ctx_param(i915, ctx, CHANGE_PARAM_PROTECTED, false), -EPERM);
+	igt_assert_eq(get_ctx_protected_param(i915, ctx), 1);
+	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 0);
+	gem_context_destroy(i915, ctx);
+}
+
+static void test_ctx_mod_regular_to_all_valid(int i915)
+{
+	uint32_t ctx;
+
+	igt_assert_eq(create_ctx_with_params(i915, false, false, false, false, &ctx), 0);
+	igt_assert_eq(get_ctx_protected_param(i915, ctx), 0);
+	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 1);
+	igt_assert_eq(modify_ctx_param(i915, ctx, CHANGE_PARAM_RECOVERY, false), 0);
+	igt_assert_eq(modify_ctx_param(i915, ctx, CHANGE_PARAM_PROTECTED, true), -EPERM);
+	igt_assert_eq(get_ctx_protected_param(i915, ctx), 0);
+	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 0);
+	gem_context_destroy(i915, ctx);
+}
+
+igt_main
+{
+	int i915 = -1;
+	bool pxp_supported = false;
+
+	igt_fixture
+	{
+		i915 = drm_open_driver(DRIVER_INTEL);
+		igt_require(i915);
+		igt_require_gem(i915);
+		pxp_supported = is_pxp_hw_supported(i915);
+	}
+
+	igt_subtest_group {
+		igt_fixture {
+			igt_require((pxp_supported == 0));
+		}
+
+		igt_describe("Verify protected buffer on unsupported hw:");
+		igt_subtest("hw-rejects-pxp-buffer")
+			test_bo_alloc_pxp_nohw(i915);
+		igt_describe("Verify protected context on unsupported hw:");
+		igt_subtest("hw-rejects-pxp-context")
+			test_ctx_alloc_pxp_nohw(i915);
+	}
+
+	igt_subtest_group {
+		igt_fixture {
+			igt_require(pxp_supported);
+		}
+
+		igt_describe("Verify protected buffer on supported hw:");
+		igt_subtest("create-regular-buffer")
+			test_bo_alloc_pxp_off(i915);
+		igt_subtest("create-protected-buffer")
+			test_bo_alloc_pxp_on(i915);
+
+		igt_describe("Verify protected context on supported hw:");
+		igt_subtest("create-regular-context-1")
+			test_ctx_alloc_recover_off_protect_off(i915);
+		igt_subtest("create-regular-context-2")
+			test_ctx_alloc_recover_on_protect_off(i915);
+		igt_subtest("fail-invalid-protected-context")
+			test_ctx_alloc_recover_on_protect_on(i915);
+		igt_subtest("create-valid-protected-context")
+			test_ctx_alloc_recover_off_protect_on(i915);
+
+		igt_describe("Verify protected context integrity:");
+		igt_subtest("reject-modify-context-protection-on")
+			test_ctx_mod_regular_to_all_valid(i915);
+		igt_subtest("reject-modify-context-protection-off-1")
+			test_ctx_mod_recover_off_to_on(i915);
+		igt_subtest("reject-modify-context-protection-off-2")
+			test_ctx_mod_protected_on_to_off(i915);
+		igt_subtest("reject-modify-context-protection-off-3")
+			test_ctx_mod_protected_to_all_invalid(i915);
+	}
+
+	igt_fixture {
+		close(i915);
+	}
+}
diff --git a/tests/meson.build b/tests/meson.build
index 8ad52596..4697c4b8 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -168,6 +168,7 @@ i915_progs = [
 	'gem_pread_after_blit',
 	'gem_pwrite',
 	'gem_pwrite_snooped',
+	'gem_pxp',
 	'gem_read_read_speed',
 	'gem_readwrite',
 	'gem_reg_read',
-- 
2.25.1

[igt-dev] [PATCH i-g-t v11 03/15] Perform a regular 3d copy as a control checkpoint

[Alan Previn]

As a control checkpoint, allocate buffers to be used
as texture and render target in the 3d engine for a
regular src to dest copy blit and verify buffer pixels.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 tests/i915/gem_pxp.c | 166 ++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 157 insertions(+), 9 deletions(-)

diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
index c6083d0f..272de57b 100644
--- a/tests/i915/gem_pxp.c
+++ b/tests/i915/gem_pxp.c
@@ -238,6 +238,20 @@ static void test_ctx_alloc_recover_on_protect_on(int i915)
 	igt_assert_eq(create_ctx_with_params(i915, true, true, false, false, &ctx), -EPERM);
 }
 
+static void test_ctx_mod_regular_to_all_valid(int i915)
+{
+	uint32_t ctx;
+
+	igt_assert_eq(create_ctx_with_params(i915, false, false, false, false, &ctx), 0);
+	igt_assert_eq(get_ctx_protected_param(i915, ctx), 0);
+	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 1);
+	igt_assert_eq(modify_ctx_param(i915, ctx, CHANGE_PARAM_RECOVERY, false), 0);
+	igt_assert_eq(modify_ctx_param(i915, ctx, CHANGE_PARAM_PROTECTED, true), -EPERM);
+	igt_assert_eq(get_ctx_protected_param(i915, ctx), 0);
+	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 0);
+	gem_context_destroy(i915, ctx);
+}
+
 static void test_ctx_mod_recover_off_to_on(int i915)
 {
 	uint32_t ctx;
@@ -277,24 +291,145 @@ static void test_ctx_mod_protected_to_all_invalid(int i915)
 	gem_context_destroy(i915, ctx);
 }
 
-static void test_ctx_mod_regular_to_all_valid(int i915)
+static void fill_bo_content(int i915, uint32_t bo, uint32_t size, uint32_t initcolor)
 {
-	uint32_t ctx;
+	uint32_t *ptr, *ptrtmp;
+	int loop = 0;
 
-	igt_assert_eq(create_ctx_with_params(i915, false, false, false, false, &ctx), 0);
-	igt_assert_eq(get_ctx_protected_param(i915, ctx), 0);
-	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 1);
-	igt_assert_eq(modify_ctx_param(i915, ctx, CHANGE_PARAM_RECOVERY, false), 0);
-	igt_assert_eq(modify_ctx_param(i915, ctx, CHANGE_PARAM_PROTECTED, true), -EPERM);
-	igt_assert_eq(get_ctx_protected_param(i915, ctx), 0);
-	igt_assert_eq(get_ctx_recovery_param(i915, ctx), 0);
+	ptr = gem_mmap__device_coherent(i915, bo, 0, size, PROT_WRITE);
+	ptrtmp = ptr;
+
+	/* read and count all dword matches till size */
+	while (loop++ < (size/4)) {
+		*ptrtmp = initcolor;
+		++ptrtmp;
+	}
+
+	igt_assert(gem_munmap(ptr, size) == 0);
+}
+
+#define COMPARE_COLOR_READIBLE     1
+#define COMPARE_COLOR_UNREADIBLE   2
+#define COMPARE_N_PIXELS_VERBOSELY 0
+
+static void assert_bo_content_check(int i915, uint32_t bo, int compare_op,
+				    uint32_t size, uint32_t color)
+{
+	uint32_t *ptr, *ptrtmp;
+	int loop = 0, num_matches = 0;
+	uint32_t value;
+	bool op_readible = (compare_op == COMPARE_COLOR_READIBLE);
+
+	ptr = gem_mmap__device_coherent(i915, bo, 0, size, PROT_READ);
+	ptrtmp = ptr;
+
+	if (COMPARE_N_PIXELS_VERBOSELY) {
+		igt_info("--------->>>\n");
+		while (loop < COMPARE_N_PIXELS_VERBOSELY && loop < (size/4)) {
+			value = *ptrtmp;
+			igt_info("Color read = 0x%08x ", value);
+			igt_info("expected %c= 0x%08x)\n", op_readible?'=':'!', color);
+			++ptrtmp;
+			++loop;
+		}
+		igt_info("<<<---------\n");
+		ptrtmp = ptr;
+		loop = 0;
+	}
+
+	/* count all pixels for matches */
+	while (loop++ < (size/4)) {
+		value = *ptrtmp;
+		if (value == color)
+			++num_matches;
+		++ptrtmp;
+	}
+
+	if (op_readible)
+		igt_assert_eq(num_matches, (size/4));
+	else
+		igt_assert_eq(num_matches, 0);
+
+	igt_assert(gem_munmap(ptr, size) == 0);
+}
+
+static uint32_t alloc_and_fill_dest_buff(int i915, bool protected, uint32_t size,
+					 uint32_t init_color)
+{
+	uint32_t bo;
+	int ret;
+
+	ret = create_bo_ext(i915, size, protected, &bo);
+	igt_assert_eq(ret, 0);
+	igt_assert(bo);
+	fill_bo_content(i915, bo, size, init_color);
+	assert_bo_content_check(i915, bo, COMPARE_COLOR_READIBLE, size, init_color);
+
+	return bo;
+}
+
+/*
+ * Rendering tests surface attributes, keep it simple:
+ * page aligned width==stride, thus, and size
+ */
+#define TSTSURF_WIDTH       1024
+#define TSTSURF_HEIGHT      128
+#define TSTSURF_BYTESPP     4
+#define TSTSURF_STRIDE      (TSTSURF_WIDTH*TSTSURF_BYTESPP)
+#define TSTSURF_SIZE        (TSTSURF_STRIDE*TSTSURF_HEIGHT)
+#define TSTSURF_FILLCOLOR1  0xfaceface
+#define TSTSURF_INITCOLOR1  0x12341234
+
+static void test_render_baseline(int i915)
+{
+	uint32_t ctx, srcbo, dstbo;
+	struct intel_buf *srcbuf, *dstbuf;
+	struct buf_ops *bops;
+	struct intel_bb *ibb;
+	uint32_t devid;
+	int ret;
+
+	devid = intel_get_drm_devid(i915);
+	igt_assert(devid);
+
+	bops = buf_ops_create(i915);
+	igt_assert(bops);
+
+	/* Perform a regular 3d copy as a control checkpoint */
+	ret = create_ctx_with_params(i915, false, false, false, false, &ctx);
+	igt_assert_eq(ret, 0);
+	ibb = intel_bb_create_with_context(i915, ctx, 4096);
+	igt_assert(ibb);
+
+	dstbo = alloc_and_fill_dest_buff(i915, false, TSTSURF_SIZE, TSTSURF_INITCOLOR1);
+	dstbuf = intel_buf_create_using_handle(bops, dstbo, TSTSURF_WIDTH, TSTSURF_HEIGHT,
+					       TSTSURF_BYTESPP*8, 0, I915_TILING_NONE, 0);
+
+	srcbo = alloc_and_fill_dest_buff(i915, false, TSTSURF_SIZE, TSTSURF_FILLCOLOR1);
+	srcbuf = intel_buf_create_using_handle(bops, srcbo, TSTSURF_WIDTH, TSTSURF_HEIGHT,
+					       TSTSURF_BYTESPP*8, 0, I915_TILING_NONE, 0);
+
+	gen12_render_copyfunc(ibb, srcbuf, 0, 0, TSTSURF_WIDTH, TSTSURF_HEIGHT, dstbuf, 0, 0);
+	gem_sync(i915, dstbo);
+
+	assert_bo_content_check(i915, dstbo, COMPARE_COLOR_READIBLE,
+				TSTSURF_SIZE, TSTSURF_FILLCOLOR1);
+
+	intel_bb_destroy(ibb);
+	intel_buf_destroy(srcbuf);
+	gem_close(i915, srcbo);
+	intel_buf_destroy(dstbuf);
+	gem_close(i915, dstbo);
 	gem_context_destroy(i915, ctx);
+	buf_ops_destroy(bops);
 }
 
 igt_main
 {
 	int i915 = -1;
 	bool pxp_supported = false;
+	igt_render_copyfunc_t rendercopy = NULL;
+	uint32_t devid = 0;
 
 	igt_fixture
 	{
@@ -348,6 +483,19 @@ igt_main
 		igt_subtest("reject-modify-context-protection-off-3")
 			test_ctx_mod_protected_to_all_invalid(i915);
 	}
+	igt_subtest_group {
+		igt_fixture {
+			igt_require(pxp_supported);
+			devid = intel_get_drm_devid(i915);
+			igt_assert(devid);
+			rendercopy = igt_get_render_copyfunc(devid);
+			igt_require(rendercopy);
+		}
+
+		igt_describe("Verify protected render operations:");
+		igt_subtest("regular-baseline-src-copy-readible")
+			test_render_baseline(i915);
+	}
 
 	igt_fixture {
 		close(i915);
-- 
2.25.1

[igt-dev] [PATCH i-g-t v11 04/15] Add PXP attribute support in batchbuffer and buffer_ops libs

[Alan Previn]

Eventually when we get to testing PXP rendering capability,
we shall reuse lib's rendercopy feature. Rendercopy libraries
shall retrieve information about PXP-session-enablement and
which buffers are protected from these new flags.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 lib/intel_batchbuffer.c | 21 +++++++++++++++++++++
 lib/intel_batchbuffer.h | 28 ++++++++++++++++++++++++++++
 lib/intel_bufops.h      | 15 +++++++++++++++
 3 files changed, 64 insertions(+)

diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 399d0e99..773d0d27 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -2350,6 +2350,27 @@ uint64_t intel_bb_offset_reloc_to_object(struct intel_bb *ibb,
 				  delta, offset, presumed_offset);
 }
 
+/*
+ * @intel_bb_set_pxp:
+ * @ibb: pointer to intel_bb
+ * @new_state: enable or disable pxp session
+ * @apptype: pxp session input identifies what type of session to enable
+ * @appid: pxp session input provides which appid to use
+ *
+ * This function merely stores the pxp state and session information to
+ * be retrieved and programmed later by supporting libraries such as
+ * gen12_render_copy that must program the HW within the same dispatch
+ */
+void intel_bb_set_pxp(struct intel_bb *ibb, bool new_state,
+		      uint32_t apptype, uint32_t appid)
+{
+	igt_assert(ibb);
+
+	ibb->pxp.enabled = new_state;
+	ibb->pxp.apptype = new_state ? apptype : 0;
+	ibb->pxp.appid   = new_state ? appid : 0;
+}
+
 static void intel_bb_dump_execbuf(struct intel_bb *ibb,
 				  struct drm_i915_gem_execbuffer2 *execbuf)
 {
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index 0839d761..10fa66ee 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -446,6 +446,11 @@ typedef void (*igt_media_spinfunc_t)(int i915,
 
 igt_media_spinfunc_t igt_get_media_spinfunc(int devid);
 
+struct igt_pxp {
+	bool     enabled;
+	uint32_t apptype;
+	uint32_t appid;
+};
 
 /*
  * Batchbuffer without libdrm dependency
@@ -472,6 +477,7 @@ struct intel_bb {
 	bool supports_48b_address;
 	bool uses_full_ppgtt;
 
+	struct igt_pxp pxp;
 	uint32_t ctx;
 	uint32_t vm_id;
 
@@ -583,6 +589,27 @@ static inline void intel_bb_out(struct intel_bb *ibb, uint32_t dword)
 	igt_assert(intel_bb_offset(ibb) <= ibb->size);
 }
 
+void intel_bb_set_pxp(struct intel_bb *ibb, bool new_state,
+		      uint32_t apptype, uint32_t appid);
+
+static inline bool intel_bb_pxp_enabled(struct intel_bb *ibb)
+{
+	igt_assert(ibb);
+	return ibb->pxp.enabled;
+}
+
+static inline uint32_t intel_bb_pxp_apptype(struct intel_bb *ibb)
+{
+	igt_assert(ibb);
+	return ibb->pxp.apptype;
+}
+
+static inline uint32_t intel_bb_pxp_appid(struct intel_bb *ibb)
+{
+	igt_assert(ibb);
+	return ibb->pxp.appid;
+}
+
 struct drm_i915_gem_exec_object2 *
 intel_bb_add_object(struct intel_bb *ibb, uint32_t handle, uint64_t size,
 		    uint64_t offset, uint64_t alignment, bool write);
@@ -697,3 +724,4 @@ typedef void (*igt_huc_copyfunc_t)(int fd, uint64_t ahnd,
 
 igt_huc_copyfunc_t	igt_get_huc_copyfunc(int devid);
 #endif
+
diff --git a/lib/intel_bufops.h b/lib/intel_bufops.h
index 54f2ce45..8b718ba7 100644
--- a/lib/intel_bufops.h
+++ b/lib/intel_bufops.h
@@ -50,6 +50,9 @@ struct intel_buf {
 	uint32_t *ptr;
 	bool cpu_write;
 
+	/* Content Protection*/
+	bool is_protected;
+
 	/* For debugging purposes */
 	char name[INTEL_BUF_NAME_MAXSIZE + 1];
 };
@@ -160,6 +163,18 @@ struct intel_buf *intel_buf_create_using_handle_and_size(struct buf_ops *bops,
 							 int stride);
 void intel_buf_destroy(struct intel_buf *buf);
 
+static inline void intel_buf_set_pxp(struct intel_buf *buf, bool new_pxp_state)
+{
+	igt_assert(buf);
+	buf->is_protected = new_pxp_state;
+}
+
+static inline bool intel_buf_pxp(const struct intel_buf *buf)
+{
+	igt_assert(buf);
+	return buf->is_protected;
+}
+
 void *intel_buf_cpu_map(struct intel_buf *buf, bool write);
 void *intel_buf_device_map(struct intel_buf *buf, bool write);
 void intel_buf_unmap(struct intel_buf *buf);
-- 
2.25.1

[igt-dev] [PATCH i-g-t v11 05/15] Add MI_SET_APPID instruction definition

[Alan Previn]

Add MI_SET_APPID instruction and param definitions

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 lib/intel_reg.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index ac1fc6cb..ab01a283 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -2546,6 +2546,14 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define CTXT_PALETTE_SAVE_DISABLE	(1<<3)
 #define CTXT_PALETTE_RESTORE_DISABLE	(1<<2)
 
+#define MI_SET_APPID                    (0x0E << 23)
+#define APPID_CTXREST_INHIBIT           (1 << 9)
+#define APPID_CTXSAVE_INHIBIT           (1 << 8)
+#define APPTYPE(n)                      ((n) << 7)
+#define  DISPLAY_APPTYPE                (0)
+#define  TRANSCODE_APPTYPE              (1)
+#define APPID(n)                        ((n) & 0x7f)
+
 /* Dword 0 */
 #define MI_VERTEX_BUFFER		(0x17<<23)
 #define MI_VERTEX_BUFFER_IDX(x)		(x<<20)
-- 
2.25.1

[igt-dev] [PATCH i-g-t v11 06/15] Enable protected session cmd in gen12_render_copyfunc

[Alan Previn]

1. In _gen9_render_op, check if the incoming batchbuffer
   is marked with pxp enabled. If so, insert MI_SET_APPID
   along with PIPE_CONTROL instructions at the start and
   end of the rendering operation in the command buffer.

2. The two PIPE_CONTROLs will enable protected memory
   at the start of the batch and disabling protected
   memory at the end of it. These PIPE_CONTROLs require a
   Post-Sync operation with a write to memory for hardware
   to accept.

3. In order to satisfy #2, _gen9_render_op uses unused
   regions of the ibb buffer for the PIPE_CONTROL PostSync
   write to memory (no different from how other 3d states
   are being referenced).

4. _gen9_render_op shall check the incoming surface
   buffers for "is_protected" flag and if its set, it
   will mark the SURFACE_STATE's MOCS field accordingly.

NOTE: _gen9_render_op needs to program the HW to enable
the PXP session as part of the rendering batch buffer
because the HW requires that enabling/disabling protected
memory access must be programmed in pairs within the same
"dispatch of rendering commands" to HW.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 lib/rendercopy_gen9.c | 57 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 57 insertions(+)

diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
index 0356964e..f021f4cb 100644
--- a/lib/rendercopy_gen9.c
+++ b/lib/rendercopy_gen9.c
@@ -183,6 +183,8 @@ gen8_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int is_dst) {
 		ss->ss0.tiled_mode = 3;
 
 	ss->ss1.memory_object_control = intel_get_uc_mocs(i915);
+	if (intel_buf_pxp(buf))
+		ss->ss1.memory_object_control |= 1;
 
 	if (buf->tiling == I915_TILING_Yf)
 		ss->ss5.trmode = 1;
@@ -904,6 +906,53 @@ static void gen8_emit_primitive(struct intel_bb *ibb, uint32_t offset)
 	intel_bb_out(ibb, 0);	/* index buffer offset, ignored */
 }
 
+#define GFX_OP_PIPE_CONTROL    ((3 << 29) | (3 << 27) | (2 << 24))
+#define PIPE_CONTROL_CS_STALL	            (1 << 20)
+#define PIPE_CONTROL_RENDER_TARGET_FLUSH    (1 << 12)
+#define PIPE_CONTROL_FLUSH_ENABLE           (1 << 7)
+#define PIPE_CONTROL_DATA_CACHE_INVALIDATE  (1 << 5)
+#define PIPE_CONTROL_PROTECTEDPATH_DISABLE  (1 << 27)
+#define PIPE_CONTROL_PROTECTEDPATH_ENABLE   (1 << 22)
+#define PIPE_CONTROL_POST_SYNC_OP           (1 << 14)
+#define PIPE_CONTROL_POST_SYNC_OP_STORE_DW_IDX (1 << 21)
+#define PS_OP_TAG_START                     0x1234fed0
+#define PS_OP_TAG_END                       0x5678cbaf
+static void gen12_emit_pxp_state(struct intel_bb *ibb, bool enable,
+		 uint32_t pxp_write_op_offset)
+{
+	uint32_t pipe_ctl_flags;
+	uint32_t set_app_id, ps_op_id;
+
+	if (enable) {
+		pipe_ctl_flags = PIPE_CONTROL_FLUSH_ENABLE;
+		intel_bb_out(ibb, GFX_OP_PIPE_CONTROL);
+		intel_bb_out(ibb, pipe_ctl_flags);
+
+		set_app_id =  MI_SET_APPID |
+			      APPTYPE(intel_bb_pxp_apptype(ibb)) |
+			      APPID(intel_bb_pxp_appid(ibb));
+		intel_bb_out(ibb, set_app_id);
+
+		pipe_ctl_flags = PIPE_CONTROL_PROTECTEDPATH_ENABLE;
+		ps_op_id = PS_OP_TAG_START;
+	} else {
+		pipe_ctl_flags = PIPE_CONTROL_PROTECTEDPATH_DISABLE;
+		ps_op_id = PS_OP_TAG_END;
+	}
+
+	pipe_ctl_flags |= (PIPE_CONTROL_CS_STALL |
+			   PIPE_CONTROL_RENDER_TARGET_FLUSH |
+			   PIPE_CONTROL_DATA_CACHE_INVALIDATE |
+			   PIPE_CONTROL_POST_SYNC_OP);
+	intel_bb_out(ibb, GFX_OP_PIPE_CONTROL | 4);
+	intel_bb_out(ibb, pipe_ctl_flags);
+	intel_bb_emit_reloc(ibb, ibb->handle, 0, I915_GEM_DOMAIN_COMMAND,
+			    (enable ? pxp_write_op_offset : (pxp_write_op_offset+8)),
+			    ibb->batch_offset);
+	intel_bb_out(ibb, ps_op_id);
+	intel_bb_out(ibb, ps_op_id);
+}
+
 /* The general rule is if it's named gen6 it is directly copied from
  * gen6_render_copyfunc.
  *
@@ -953,6 +1002,7 @@ void _gen9_render_op(struct intel_bb *ibb,
 	uint32_t vertex_buffer;
 	uint32_t aux_pgtable_state;
 	bool fast_clear = !src;
+	uint32_t pxp_scratch_offset;
 
 	if (!fast_clear)
 		igt_assert(src->bpp == dst->bpp);
@@ -981,8 +1031,12 @@ void _gen9_render_op(struct intel_bb *ibb,
 	aux_pgtable_state = gen12_create_aux_pgtable_state(ibb, aux_pgtable_buf);
 
 	/* TODO: there is other state which isn't setup */
+	pxp_scratch_offset = intel_bb_offset(ibb);
 	intel_bb_ptr_set(ibb, 0);
 
+	if (intel_bb_pxp_enabled(ibb))
+		gen12_emit_pxp_state(ibb, true, pxp_scratch_offset);
+
 	/* Start emitting the commands. The order roughly follows the mesa blorp
 	 * order */
 	intel_bb_out(ibb, G4X_PIPELINE_SELECT | PIPELINE_SELECT_3D |
@@ -1054,6 +1108,9 @@ void _gen9_render_op(struct intel_bb *ibb,
 	gen8_emit_vf_topology(ibb);
 	gen8_emit_primitive(ibb, vertex_buffer);
 
+	if (intel_bb_pxp_enabled(ibb))
+		gen12_emit_pxp_state(ibb, false, pxp_scratch_offset);
+
 	intel_bb_emit_bbe(ibb);
 	intel_bb_exec(ibb, intel_bb_offset(ibb),
 		      I915_EXEC_RENDER | I915_EXEC_NO_RELOC, false);
-- 
2.25.1

[igt-dev] [PATCH i-g-t v11 07/15] Add subtest to copy raw source to protected dest

[Alan Previn]

Add subtest to 3d-copy raw source buffer (with
known readible content) to a destination buffer
marked as protected with a protected session using
default session keys. The destination buffer is
verified to be different from the source (when
read via CPU) because its encrypted.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 tests/i915/gem_pxp.c | 55 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 55 insertions(+)

diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
index 272de57b..9c7de6b0 100644
--- a/tests/i915/gem_pxp.c
+++ b/tests/i915/gem_pxp.c
@@ -378,7 +378,9 @@ static uint32_t alloc_and_fill_dest_buff(int i915, bool protected, uint32_t size
 #define TSTSURF_STRIDE      (TSTSURF_WIDTH*TSTSURF_BYTESPP)
 #define TSTSURF_SIZE        (TSTSURF_STRIDE*TSTSURF_HEIGHT)
 #define TSTSURF_FILLCOLOR1  0xfaceface
+#define TSTSURF_FILLCOLOR2  0xdeaddead
 #define TSTSURF_INITCOLOR1  0x12341234
+#define TSTSURF_INITCOLOR2  0x56785678
 
 static void test_render_baseline(int i915)
 {
@@ -424,6 +426,57 @@ static void test_render_baseline(int i915)
 	buf_ops_destroy(bops);
 }
 
+static void test_render_pxp_src_to_protdest(int i915)
+{
+	uint32_t ctx, srcbo, dstbo;
+	struct intel_buf *srcbuf, *dstbuf;
+	struct buf_ops *bops;
+	struct intel_bb *ibb;
+	uint32_t devid;
+	int ret;
+
+	devid = intel_get_drm_devid(i915);
+	igt_assert(devid);
+
+	bops = buf_ops_create(i915);
+	igt_assert(bops);
+
+	/*
+	 * Perform a protected render operation but only label
+	 * the dest as protected. After rendering, the content
+	 * should be encrypted
+	 */
+	ret = create_ctx_with_params(i915, true, true, true, false, &ctx);
+	igt_assert_eq(ret, 0);
+	igt_assert_eq(get_ctx_protected_param(i915, ctx), 1);
+	ibb = intel_bb_create_with_context(i915, ctx, 4096);
+	igt_assert(ibb);
+	intel_bb_set_pxp(ibb, true, DISPLAY_APPTYPE, I915_PROTECTED_CONTENT_DEFAULT_SESSION);
+
+	dstbo = alloc_and_fill_dest_buff(i915, true, TSTSURF_SIZE, TSTSURF_INITCOLOR2);
+	dstbuf = intel_buf_create_using_handle(bops, dstbo, TSTSURF_WIDTH, TSTSURF_HEIGHT,
+						TSTSURF_BYTESPP*8, 0, I915_TILING_NONE, 0);
+	intel_buf_set_pxp(dstbuf, true);
+
+	srcbo = alloc_and_fill_dest_buff(i915, false, TSTSURF_SIZE, TSTSURF_FILLCOLOR2);
+	srcbuf = intel_buf_create_using_handle(bops, srcbo, TSTSURF_WIDTH, TSTSURF_HEIGHT,
+						TSTSURF_BYTESPP*8, 0, I915_TILING_NONE, 0);
+
+	gen12_render_copyfunc(ibb, srcbuf, 0, 0, TSTSURF_WIDTH, TSTSURF_HEIGHT, dstbuf, 0, 0);
+	gem_sync(i915, dstbo);
+
+	assert_bo_content_check(i915, dstbo, COMPARE_COLOR_UNREADIBLE,
+				TSTSURF_SIZE, TSTSURF_FILLCOLOR2);
+
+	intel_bb_destroy(ibb);
+	intel_buf_destroy(srcbuf);
+	gem_close(i915, srcbo);
+	intel_buf_destroy(dstbuf);
+	gem_close(i915, dstbo);
+	gem_context_destroy(i915, ctx);
+	buf_ops_destroy(bops);
+}
+
 igt_main
 {
 	int i915 = -1;
@@ -495,6 +548,8 @@ igt_main
 		igt_describe("Verify protected render operations:");
 		igt_subtest("regular-baseline-src-copy-readible")
 			test_render_baseline(i915);
+		igt_subtest("protected-raw-src-copy-not-readible")
+			test_render_pxp_src_to_protdest(i915);
 	}
 
 	igt_fixture {
-- 
2.25.1

[igt-dev] [PATCH i-g-t v11 08/15] Add test where both src and dest are protected

[Alan Previn]

When both the source and destination surfaces are
protected, the destination pixel result of the 3d
copy operation would be the same as the source. By
appending this test case to the end of the prior
test (raw-src to protected-dest) and reusing the
previous' test destination as the current source,
we can prove that new-source was decrypted properly
as we would see the difference in results: repeating
the same render operation but with a src buffer
that is protected in this case yields matching
(but still encrypted) output rendered pixels.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 tests/i915/gem_pxp.c | 144 +++++++++++++++++++++++++++++++++++++++----
 1 file changed, 133 insertions(+), 11 deletions(-)

diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
index 9c7de6b0..51908799 100644
--- a/tests/i915/gem_pxp.c
+++ b/tests/i915/gem_pxp.c
@@ -310,29 +310,51 @@ static void fill_bo_content(int i915, uint32_t bo, uint32_t size, uint32_t initc
 
 #define COMPARE_COLOR_READIBLE     1
 #define COMPARE_COLOR_UNREADIBLE   2
+#define COMPARE_BUFFER_READIBLE    3
+#define COMPARE_BUFFER_UNREADIBLE  4
+#define COPY_BUFFER                5
 #define COMPARE_N_PIXELS_VERBOSELY 0
 
-static void assert_bo_content_check(int i915, uint32_t bo, int compare_op,
-				    uint32_t size, uint32_t color)
+static void assert_bo_content_check(int i915, uint32_t bo, int compare_op, uint32_t size,
+				    uint32_t color, uint32_t *auxptr, int auxsize)
 {
-	uint32_t *ptr, *ptrtmp;
+	uint32_t *ptr, *ptrtmp, *auxtmp;
 	int loop = 0, num_matches = 0;
 	uint32_t value;
-	bool op_readible = (compare_op == COMPARE_COLOR_READIBLE);
+	bool op_readible = ((compare_op == COMPARE_COLOR_READIBLE) ||
+		 (compare_op == COMPARE_BUFFER_READIBLE));
+	bool chk_buff = ((compare_op == COMPARE_BUFFER_READIBLE) ||
+		 (compare_op == COMPARE_BUFFER_UNREADIBLE));
+	bool copy_buff = (compare_op == COPY_BUFFER);
 
 	ptr = gem_mmap__device_coherent(i915, bo, 0, size, PROT_READ);
 	ptrtmp = ptr;
 
+	if (chk_buff || copy_buff) {
+		if (auxsize < size)
+			auxptr = NULL;
+		igt_assert(auxptr);
+		auxtmp = auxptr;
+	}
+
 	if (COMPARE_N_PIXELS_VERBOSELY) {
 		igt_info("--------->>>\n");
 		while (loop < COMPARE_N_PIXELS_VERBOSELY && loop < (size/4)) {
 			value = *ptrtmp;
-			igt_info("Color read = 0x%08x ", value);
-			igt_info("expected %c= 0x%08x)\n", op_readible?'=':'!', color);
+			if (chk_buff)
+				color = *auxtmp;
+			if (copy_buff)
+				igt_info("Color copy = 0x%08x\n", value);
+			else {
+				igt_info("Color read = 0x%08x ", value);
+				igt_info("expected %c= 0x%08x)\n", op_readible?'=':'!', color);
+			}
+			++auxtmp;
 			++ptrtmp;
 			++loop;
 		}
 		igt_info("<<<---------\n");
+		auxtmp = auxptr;
 		ptrtmp = ptr;
 		loop = 0;
 	}
@@ -340,8 +362,25 @@ static void assert_bo_content_check(int i915, uint32_t bo, int compare_op,
 	/* count all pixels for matches */
 	while (loop++ < (size/4)) {
 		value = *ptrtmp;
-		if (value == color)
-			++num_matches;
+		switch (compare_op) {
+		case COMPARE_COLOR_READIBLE:
+		case COMPARE_COLOR_UNREADIBLE:
+			if (value == color)
+				++num_matches;
+			break;
+		case COMPARE_BUFFER_READIBLE:
+		case COMPARE_BUFFER_UNREADIBLE:
+			if (value == (*auxtmp))
+				++num_matches;
+			++auxtmp;
+			break;
+		case COPY_BUFFER:
+			*auxtmp = value;
+			++auxtmp;
+			break;
+		default:
+			break;
+		}
 		++ptrtmp;
 	}
 
@@ -363,7 +402,8 @@ static uint32_t alloc_and_fill_dest_buff(int i915, bool protected, uint32_t size
 	igt_assert_eq(ret, 0);
 	igt_assert(bo);
 	fill_bo_content(i915, bo, size, init_color);
-	assert_bo_content_check(i915, bo, COMPARE_COLOR_READIBLE, size, init_color);
+	assert_bo_content_check(i915, bo, COMPARE_COLOR_READIBLE,
+				size, init_color, NULL, 0);
 
 	return bo;
 }
@@ -381,6 +421,7 @@ static uint32_t alloc_and_fill_dest_buff(int i915, bool protected, uint32_t size
 #define TSTSURF_FILLCOLOR2  0xdeaddead
 #define TSTSURF_INITCOLOR1  0x12341234
 #define TSTSURF_INITCOLOR2  0x56785678
+#define TSTSURF_INITCOLOR3  0xabcdabcd
 
 static void test_render_baseline(int i915)
 {
@@ -415,7 +456,7 @@ static void test_render_baseline(int i915)
 	gem_sync(i915, dstbo);
 
 	assert_bo_content_check(i915, dstbo, COMPARE_COLOR_READIBLE,
-				TSTSURF_SIZE, TSTSURF_FILLCOLOR1);
+				TSTSURF_SIZE, TSTSURF_FILLCOLOR1, NULL, 0);
 
 	intel_bb_destroy(ibb);
 	intel_buf_destroy(srcbuf);
@@ -466,13 +507,92 @@ static void test_render_pxp_src_to_protdest(int i915)
 	gem_sync(i915, dstbo);
 
 	assert_bo_content_check(i915, dstbo, COMPARE_COLOR_UNREADIBLE,
-				TSTSURF_SIZE, TSTSURF_FILLCOLOR2);
+				TSTSURF_SIZE, TSTSURF_FILLCOLOR2, NULL, 0);
+
+	intel_bb_destroy(ibb);
+	intel_buf_destroy(srcbuf);
+	gem_close(i915, srcbo);
+	intel_buf_destroy(dstbuf);
+	gem_close(i915, dstbo);
+	gem_context_destroy(i915, ctx);
+	buf_ops_destroy(bops);
+}
+
+static void test_render_pxp_protsrc_to_protdest(int i915)
+{
+	uint32_t ctx, srcbo, dstbo, dstbo2;
+	struct intel_buf *srcbuf, *dstbuf, *dstbuf2;
+	struct buf_ops *bops;
+	struct intel_bb *ibb;
+	uint32_t devid;
+	int ret;
+	uint32_t encrypted[TSTSURF_SIZE/TSTSURF_BYTESPP];
+
+	devid = intel_get_drm_devid(i915);
+	igt_assert(devid);
+
+	bops = buf_ops_create(i915);
+	igt_assert(bops);
+
+	/*
+	 * Perform a protected render operation but only label
+	 * the dest as protected. After rendering, the content
+	 * should be encrypted
+	 */
+	ret = create_ctx_with_params(i915, true, true, true, false, &ctx);
+	igt_assert_eq(ret, 0);
+	igt_assert_eq(get_ctx_protected_param(i915, ctx), 1);
+	ibb = intel_bb_create_with_context(i915, ctx, 4096);
+	igt_assert(ibb);
+	intel_bb_set_pxp(ibb, true, DISPLAY_APPTYPE, I915_PROTECTED_CONTENT_DEFAULT_SESSION);
+
+	dstbo = alloc_and_fill_dest_buff(i915, true, TSTSURF_SIZE, TSTSURF_INITCOLOR2);
+	dstbuf = intel_buf_create_using_handle(bops, dstbo, TSTSURF_WIDTH, TSTSURF_HEIGHT,
+						TSTSURF_BYTESPP*8, 0, I915_TILING_NONE, 0);
+	intel_buf_set_pxp(dstbuf, true);
+
+	srcbo = alloc_and_fill_dest_buff(i915, false, TSTSURF_SIZE, TSTSURF_FILLCOLOR2);
+	srcbuf = intel_buf_create_using_handle(bops, srcbo, TSTSURF_WIDTH, TSTSURF_HEIGHT,
+						TSTSURF_BYTESPP*8, 0, I915_TILING_NONE, 0);
+
+	gen12_render_copyfunc(ibb, srcbuf, 0, 0, TSTSURF_WIDTH, TSTSURF_HEIGHT, dstbuf, 0, 0);
+	gem_sync(i915, dstbo);
+
+	assert_bo_content_check(i915, dstbo, COMPARE_COLOR_UNREADIBLE,
+				TSTSURF_SIZE, TSTSURF_FILLCOLOR2, NULL, 0);
+
+	/*
+	 * Reuse prior dst as the new-src and create dst2 as the new-dest.
+	 * Take a copy of encrypted content from new-src for comparison after render
+	 * operation. After the rendering, we should find no difference in content
+	 * since both new-src and new-dest are labelled as encrypted. HW should read
+	 * and decrypt new-src, perform the render and re-encrypt when going into
+	 * new-dest
+	 */
+	assert_bo_content_check(i915, dstbo, COPY_BUFFER,
+				TSTSURF_SIZE, 0, encrypted, TSTSURF_SIZE);
+
+	dstbo2 = alloc_and_fill_dest_buff(i915, true, TSTSURF_SIZE, TSTSURF_INITCOLOR3);
+	dstbuf2 = intel_buf_create_using_handle(bops, dstbo2, TSTSURF_WIDTH, TSTSURF_HEIGHT,
+						TSTSURF_BYTESPP*8, 0, I915_TILING_NONE, 0);
+	intel_buf_set_pxp(dstbuf2, true);
+	intel_buf_set_pxp(dstbuf, true);/*this time, src is protected*/
+
+	intel_bb_set_pxp(ibb, true, DISPLAY_APPTYPE, I915_PROTECTED_CONTENT_DEFAULT_SESSION);
+
+	gen12_render_copyfunc(ibb, dstbuf, 0, 0, TSTSURF_WIDTH, TSTSURF_HEIGHT, dstbuf2, 0, 0);
+	gem_sync(i915, dstbo2);
+
+	assert_bo_content_check(i915, dstbo2, COMPARE_BUFFER_READIBLE,
+				TSTSURF_SIZE, 0, encrypted, TSTSURF_SIZE);
 
 	intel_bb_destroy(ibb);
 	intel_buf_destroy(srcbuf);
 	gem_close(i915, srcbo);
 	intel_buf_destroy(dstbuf);
 	gem_close(i915, dstbo);
+	intel_buf_destroy(dstbuf2);
+	gem_close(i915, dstbo2);
 	gem_context_destroy(i915, ctx);
 	buf_ops_destroy(bops);
 }
@@ -550,6 +670,8 @@ igt_main
 			test_render_baseline(i915);
 		igt_subtest("protected-raw-src-copy-not-readible")
 			test_render_pxp_src_to_protdest(i915);
+		igt_subtest("protected-encrypted-src-copy-not-readible")
+			test_render_pxp_protsrc_to_protdest(i915);
 	}
 
 	igt_fixture {
-- 
2.25.1

[igt-dev] [PATCH i-g-t v11 09/15] Verify PXP teardown occurred through suspend-resume

[Alan Previn]

During a suspend-resume cycle, the driver shall ensure the
PXP session and keys are torn down and re-established.
Verify that key change did occur by repeating the 3d
rendercopy operation before and after the suspend-resume
cycle and ensuring the encrypted output is different.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 tests/i915/gem_pxp.c | 66 +++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 65 insertions(+), 1 deletion(-)

diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
index 51908799..3233fa7f 100644
--- a/tests/i915/gem_pxp.c
+++ b/tests/i915/gem_pxp.c
@@ -10,6 +10,12 @@
 IGT_TEST_DESCRIPTION("Test PXP that manages protected content through arbitrated HW-PXP-session");
 /* Note: PXP = "Protected Xe Path" */
 
+/* Struct and definitions for power management. */
+struct powermgt_data {
+	int debugfsdir;
+	bool has_runtime_pm;
+};
+
 static int create_bo_ext(int i915, uint32_t size, bool protected_is_true, uint32_t *bo_out)
 {
 	int ret;
@@ -467,7 +473,7 @@ static void test_render_baseline(int i915)
 	buf_ops_destroy(bops);
 }
 
-static void test_render_pxp_src_to_protdest(int i915)
+static void __test_render_pxp_src_to_protdest(int i915, uint32_t *outpixels, int outsize)
 {
 	uint32_t ctx, srcbo, dstbo;
 	struct intel_buf *srcbuf, *dstbuf;
@@ -509,6 +515,10 @@ static void test_render_pxp_src_to_protdest(int i915)
 	assert_bo_content_check(i915, dstbo, COMPARE_COLOR_UNREADIBLE,
 				TSTSURF_SIZE, TSTSURF_FILLCOLOR2, NULL, 0);
 
+	if (outpixels)
+		assert_bo_content_check(i915, dstbo, COPY_BUFFER,
+					TSTSURF_SIZE, 0, outpixels, outsize);
+
 	intel_bb_destroy(ibb);
 	intel_buf_destroy(srcbuf);
 	gem_close(i915, srcbo);
@@ -518,6 +528,11 @@ static void test_render_pxp_src_to_protdest(int i915)
 	buf_ops_destroy(bops);
 }
 
+static void test_render_pxp_src_to_protdest(int i915)
+{
+	__test_render_pxp_src_to_protdest(i915, NULL, 0);
+}
+
 static void test_render_pxp_protsrc_to_protdest(int i915)
 {
 	uint32_t ctx, srcbo, dstbo, dstbo2;
@@ -597,10 +612,46 @@ static void test_render_pxp_protsrc_to_protdest(int i915)
 	buf_ops_destroy(bops);
 }
 
+static void init_powermgt_resources(int i915, struct powermgt_data *pm)
+{
+	pm->debugfsdir = igt_debugfs_dir(i915);
+	igt_require(pm->debugfsdir != -1);
+	pm->has_runtime_pm = igt_setup_runtime_pm(i915);
+	igt_require(pm->has_runtime_pm);
+}
+
+static void trigger_powermgt_suspend_cycle(int i915,
+	struct powermgt_data *pm)
+{
+	igt_pm_enable_sata_link_power_management();
+	igt_system_suspend_autoresume(SUSPEND_STATE_MEM, SUSPEND_TEST_DEVICES);
+}
+
+static void test_pxp_pwrcycle_teardown_keychange(int i915, struct powermgt_data *pm)
+{
+	uint32_t encrypted_pixels_b4[TSTSURF_SIZE/TSTSURF_BYTESPP];
+	uint32_t encrypted_pixels_aft[TSTSURF_SIZE/TSTSURF_BYTESPP];
+	int matched_after_keychange = 0, loop = 0;
+
+	__test_render_pxp_src_to_protdest(i915, encrypted_pixels_b4, TSTSURF_SIZE);
+
+	trigger_powermgt_suspend_cycle(i915, pm);
+
+	__test_render_pxp_src_to_protdest(i915, encrypted_pixels_aft, TSTSURF_SIZE);
+
+	while (loop < (TSTSURF_SIZE/TSTSURF_BYTESPP)) {
+		if (encrypted_pixels_b4[loop] == encrypted_pixels_aft[loop])
+			++matched_after_keychange;
+		++loop;
+	}
+	igt_assert_eq(matched_after_keychange, 0);
+}
+
 igt_main
 {
 	int i915 = -1;
 	bool pxp_supported = false;
+	struct powermgt_data pm = {0};
 	igt_render_copyfunc_t rendercopy = NULL;
 	uint32_t devid = 0;
 
@@ -673,6 +724,19 @@ igt_main
 		igt_subtest("protected-encrypted-src-copy-not-readible")
 			test_render_pxp_protsrc_to_protdest(i915);
 	}
+	igt_subtest_group {
+		igt_fixture {
+			igt_require(pxp_supported);
+			devid = intel_get_drm_devid(i915);
+			igt_assert(devid);
+			rendercopy = igt_get_render_copyfunc(devid);
+			igt_require(rendercopy);
+			init_powermgt_resources(i915, &pm);
+		}
+		igt_describe("Verify suspend-resume teardown management:");
+		igt_subtest("verify-pxp-key-change-after-suspend-resume")
+			test_pxp_pwrcycle_teardown_keychange(i915, &pm);
+	}
 
 	igt_fixture {
 		close(i915);
-- 
2.25.1

[igt-dev] [PATCH i-g-t v11 10/15] Verify execbuf fails with stale PXP context after teardown

[Alan Previn]

Add a subtest to verify that reusing a stale protected context
in a gem_execbuff after a teardown fails with -EIO error because
it's banned. Trigger the teardown via the pxp invalidation
debugfs that simulates a HW teardown IRQ.

NOTE: The end-to-end architecture requirement includes that
any break in the links of the PXP sessions needs to trigger a
full teardown and the application needs to be made aware of that
allowing it to re-establish the end-to-end pipeline of buffers,
contexts and renders again if it chooses to. This stricter
behavior targets only contexts created with PXP enabled.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 lib/intel_batchbuffer.c |   2 +-
 lib/intel_batchbuffer.h |   3 +
 tests/i915/gem_pxp.c    | 151 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 155 insertions(+), 1 deletion(-)

diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 773d0d27..3aebcc16 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -2529,7 +2529,7 @@ static void update_offsets(struct intel_bb *ibb,
  * Note: In this step execobj for bb is allocated and inserted to the objects
  * array.
 */
-static int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
+int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
 			   uint64_t flags, bool sync)
 {
 	struct drm_i915_gem_execbuffer2 execbuf;
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index 10fa66ee..58bddb1a 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -668,6 +668,9 @@ uint64_t intel_bb_offset_reloc_to_object(struct intel_bb *ibb,
 					 uint32_t offset,
 					 uint64_t presumed_offset);
 
+int __intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
+			uint64_t flags, bool sync);
+
 void intel_bb_dump_cache(struct intel_bb *ibb);
 
 void intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset,
diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
index 3233fa7f..7d508674 100644
--- a/tests/i915/gem_pxp.c
+++ b/tests/i915/gem_pxp.c
@@ -6,6 +6,7 @@
 #include "igt.h"
 #include "i915/gem.h"
 #include "i915/gem_create.h"
+#include <fcntl.h>
 
 IGT_TEST_DESCRIPTION("Test PXP that manages protected content through arbitrated HW-PXP-session");
 /* Note: PXP = "Protected Xe Path" */
@@ -16,6 +17,14 @@ struct powermgt_data {
 	bool has_runtime_pm;
 };
 
+struct simple_exec_assets {
+	uint32_t ctx;
+	uint32_t fencebo;
+	struct intel_buf *fencebuf;
+	struct buf_ops *bops;
+	struct intel_bb *ibb;
+};
+
 static int create_bo_ext(int i915, uint32_t size, bool protected_is_true, uint32_t *bo_out)
 {
 	int ret;
@@ -647,6 +656,146 @@ static void test_pxp_pwrcycle_teardown_keychange(int i915, struct powermgt_data
 	igt_assert_eq(matched_after_keychange, 0);
 }
 
+#define GFX_OP_PIPE_CONTROL    ((3 << 29) | (3 << 27) | (2 << 24))
+#define PIPE_CONTROL_CS_STALL	            (1 << 20)
+#define PIPE_CONTROL_RENDER_TARGET_FLUSH    (1 << 12)
+#define PIPE_CONTROL_FLUSH_ENABLE           (1 << 7)
+#define PIPE_CONTROL_DATA_CACHE_INVALIDATE  (1 << 5)
+#define PIPE_CONTROL_PROTECTEDPATH_DISABLE  (1 << 27)
+#define PIPE_CONTROL_PROTECTEDPATH_ENABLE   (1 << 22)
+#define PIPE_CONTROL_POST_SYNC_OP           (1 << 14)
+#define PIPE_CONTROL_POST_SYNC_OP_STORE_DW_IDX (1 << 21)
+#define PS_OP_TAG_BEFORE                    0x1234fed0
+#define PS_OP_TAG_AFTER                     0x5678cbaf
+
+static void emit_pipectrl(struct intel_bb *ibb, struct intel_buf *fenceb, bool before)
+{
+	uint32_t pipe_ctl_flags = 0;
+	uint32_t ps_op_id;
+
+	intel_bb_out(ibb, GFX_OP_PIPE_CONTROL);
+	intel_bb_out(ibb, pipe_ctl_flags);
+
+	if (before)
+		ps_op_id = PS_OP_TAG_BEFORE;
+	else
+		ps_op_id = PS_OP_TAG_AFTER;
+
+	pipe_ctl_flags = (PIPE_CONTROL_FLUSH_ENABLE |
+			  PIPE_CONTROL_CS_STALL |
+			  PIPE_CONTROL_POST_SYNC_OP);
+	intel_bb_out(ibb, GFX_OP_PIPE_CONTROL | 4);
+	intel_bb_out(ibb, pipe_ctl_flags);
+	intel_bb_emit_reloc(ibb, fenceb->handle, 0, I915_GEM_DOMAIN_COMMAND, (before?0:8),
+			    fenceb->addr.offset);
+	intel_bb_out(ibb, ps_op_id);
+	intel_bb_out(ibb, ps_op_id);
+	intel_bb_out(ibb, MI_NOOP);
+	intel_bb_out(ibb, MI_NOOP);
+}
+
+static void assert_pipectl_storedw_done(int i915, uint32_t bo)
+{
+	uint32_t *ptr;
+	uint32_t success_mask = 0x0;
+
+	ptr = gem_mmap__device_coherent(i915, bo, 0, 4096, PROT_READ);
+
+	if (ptr[0] == PS_OP_TAG_BEFORE && ptr[1] == PS_OP_TAG_BEFORE)
+		success_mask |= 0x1;
+
+	igt_assert_eq(success_mask, 0x1);
+	igt_assert(gem_munmap(ptr, 4096) == 0);
+}
+
+static int gem_execbuf_flush_store_dw(int i915, struct intel_bb *ibb, uint32_t ctx,
+				      struct intel_buf *fence)
+{
+	int ret;
+
+	intel_bb_ptr_set(ibb, 0);
+	intel_bb_add_intel_buf(ibb, fence, true);
+	emit_pipectrl(ibb, fence, true);
+	intel_bb_emit_bbe(ibb);
+	ret = __intel_bb_exec(ibb, intel_bb_offset(ibb),
+				  I915_EXEC_RENDER | I915_EXEC_NO_RELOC, false);
+	if (ret == 0) {
+		gem_sync(ibb->i915, fence->handle);
+		assert_pipectl_storedw_done(i915, fence->handle);
+	}
+	return ret;
+}
+
+static void prepare_exec_assets(int i915, struct simple_exec_assets *data, bool ctx_pxp,
+				bool buf_pxp)
+{
+	int ret;
+
+	if (ctx_pxp)
+		ret = create_ctx_with_params(i915, true, true, true, false, &(data->ctx));
+	else
+		ret = create_ctx_with_params(i915, false, false, false, false, &(data->ctx));
+	igt_assert_eq(ret, 0);
+	igt_assert_eq(get_ctx_protected_param(i915, data->ctx), ctx_pxp);
+	data->ibb = intel_bb_create_with_context(i915, data->ctx, 4096);
+	igt_assert(data->ibb);
+
+	data->fencebo = alloc_and_fill_dest_buff(i915, buf_pxp, 4096, 0);
+
+	data->bops = buf_ops_create(i915);
+	igt_assert(data->bops);
+
+	data->fencebuf = intel_buf_create_using_handle(data->bops, data->fencebo, 256, 4,
+						       32, 0, I915_TILING_NONE, 0);
+	intel_bb_add_intel_buf(data->ibb, data->fencebuf, true);
+}
+
+static void free_exec_assets(int i915, struct simple_exec_assets *data)
+{
+	intel_bb_destroy(data->ibb);
+	gem_close(i915, data->fencebo);
+	intel_buf_destroy(data->fencebuf);
+	gem_context_destroy(i915, data->ctx);
+	buf_ops_destroy(data->bops);
+}
+
+static void trigger_pxp_debugfs_forced_teardown(int i915)
+{
+	int fd, ret;
+	char str[32];
+
+	fd = igt_debugfs_open(i915, "gt/pxp/terminate_state", O_RDWR);
+	igt_assert_f(fd >= 0, "Can't open pxp termination debugfs\n");
+	ret = snprintf(str, sizeof(str), "0x1");
+	igt_assert(ret > 2 && ret < sizeof(str));
+	ret = write(fd, str, ret);
+	igt_assert_f(ret > 0, "Can't write pxp termination debugfs\n");
+
+	close(fd);
+}
+
+static void test_pxp_stale_ctx_execution(int i915)
+{
+	int ret;
+	struct simple_exec_assets data = {0};
+
+	/*
+	 * Use normal buffers for testing for invalidation
+	 * of protected contexts to ensure kernel is catching
+	 * the invalidated context (not buffer)
+	 */
+	prepare_exec_assets(i915, &data, true, false);
+	ret = gem_execbuf_flush_store_dw(i915, data.ibb, data.ctx, data.fencebuf);
+	igt_assert(ret == 0);
+
+	trigger_pxp_debugfs_forced_teardown(i915);
+
+	ret = gem_execbuf_flush_store_dw(i915, data.ibb, data.ctx, data.fencebuf);
+	igt_assert_f((ret == -EIO), "Executing stale pxp context didn't fail with -EIO\n");
+
+	free_exec_assets(i915, &data);
+}
+
 igt_main
 {
 	int i915 = -1;
@@ -736,6 +885,8 @@ igt_main
 		igt_describe("Verify suspend-resume teardown management:");
 		igt_subtest("verify-pxp-key-change-after-suspend-resume")
 			test_pxp_pwrcycle_teardown_keychange(i915, &pm);
+		igt_subtest("verify-pxp-stale-ctx-execution")
+			test_pxp_stale_ctx_execution(i915);
 	}
 
 	igt_fixture {
-- 
2.25.1

[igt-dev] [PATCH i-g-t v11 11/15] Verify execbuf fails with stale PXP buffer after teardown

[Alan Previn]

Add a check to verify that reusing a stale protected buffer
in a gem_execbuff (with a protected context) after a teardown
event fails with -ENOEXEC error. Trigger the teardown via the
pxp invalidation debugfs that simulates a HW teardown IRQ.

NOTE: The end-to-end architecture requirement includes that
any break in the links of the PXP sessions needs to trigger a
full teardown and the application needs to be made aware of that
allowing it to re-establish the end-to-end pipeline of buffers,
contexts and renders again if it chooses to. This stricter
behavior targets only contexts created with PXP enabled.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 tests/i915/gem_pxp.c | 35 +++++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
index 7d508674..22a2e5a4 100644
--- a/tests/i915/gem_pxp.c
+++ b/tests/i915/gem_pxp.c
@@ -796,6 +796,39 @@ static void test_pxp_stale_ctx_execution(int i915)
 	free_exec_assets(i915, &data);
 }
 
+static void test_pxp_stale_buf_execution(int i915)
+{
+	int ret;
+	struct simple_exec_assets data = {0};
+	uint32_t ctx2;
+	struct intel_bb *ibb2;
+
+	/* Use pxp buffers with pxp context for testing for invalidation of protected buffers. */
+	prepare_exec_assets(i915, &data, true, true);
+	ret = gem_execbuf_flush_store_dw(i915, data.ibb, data.ctx, data.fencebuf);
+	igt_assert(ret == 0);
+
+	trigger_pxp_debugfs_forced_teardown(i915);
+
+	/*
+	 * After teardown, use a new pxp context but reuse the stale bo to ensure
+	 * the kernel is catching the invalidated bo (not context)
+	 */
+	ret = create_ctx_with_params(i915, true, true, true, false, &ctx2);
+	igt_assert_eq(ret, 0);
+	igt_assert_eq(get_ctx_protected_param(i915, ctx2), 1);
+	ibb2 = intel_bb_create_with_context(i915, ctx2, 4096);
+	igt_assert(ibb2);
+	intel_bb_remove_intel_buf(data.ibb, data.fencebuf);
+	intel_bb_add_intel_buf(ibb2, data.fencebuf, true);
+	ret = gem_execbuf_flush_store_dw(i915, ibb2, ctx2, data.fencebuf);
+	igt_assert_f((ret == -ENOEXEC), "Executing stale pxp buffer didn't fail with -ENOEXEC\n");
+
+	intel_bb_destroy(ibb2);
+	gem_context_destroy(i915, ctx2);
+	free_exec_assets(i915, &data);
+}
+
 igt_main
 {
 	int i915 = -1;
@@ -887,6 +920,8 @@ igt_main
 			test_pxp_pwrcycle_teardown_keychange(i915, &pm);
 		igt_subtest("verify-pxp-stale-ctx-execution")
 			test_pxp_stale_ctx_execution(i915);
+		igt_subtest("verify-pxp-stale-buf-execution")
+			test_pxp_stale_buf_execution(i915);
 	}
 
 	igt_fixture {
-- 
2.25.1

[igt-dev] [PATCH i-g-t v11 12/15] Verify execbuf ok with stale PXP buf in opt-out use

[Alan Previn]

Add a check to verify that reusing a stale protected
buffer in a gem_execbuff call, but using a regular (not-
protected) context will succeed after a teardown event.
Trigger the teardown via the pxp invalidation debugfs
that simulates a HW teardown IRQ.

This ensures that user space applications that choose
not to opt-in for strict PXP teardown awareness (by
using a regular context) won't suffer gem_execbuff
failures if a protected buffer was among the assets
used in any of its rendering operations.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 tests/i915/gem_pxp.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
index 22a2e5a4..8e3bc3cf 100644
--- a/tests/i915/gem_pxp.c
+++ b/tests/i915/gem_pxp.c
@@ -829,6 +829,27 @@ static void test_pxp_stale_buf_execution(int i915)
 	free_exec_assets(i915, &data);
 }
 
+static void test_pxp_stale_buf_optout_execution(int i915)
+{
+	int ret;
+	struct simple_exec_assets data = {0};
+
+	/*
+	 * Use a normal context for testing opt-out behavior
+	 * when executing with a pxp buffer across a teardown event.
+	 */
+	prepare_exec_assets(i915, &data, false, true);
+	ret = gem_execbuf_flush_store_dw(i915, data.ibb, data.ctx, data.fencebuf);
+	igt_assert(ret == 0);
+
+	trigger_pxp_debugfs_forced_teardown(i915);
+
+	ret = gem_execbuf_flush_store_dw(i915, data.ibb, data.ctx, data.fencebuf);
+	igt_assert_f((ret == 0), "Opt-out-execution with stale pxp buffer didn't succeed\n");
+
+	free_exec_assets(i915, &data);
+}
+
 igt_main
 {
 	int i915 = -1;
@@ -922,6 +943,8 @@ igt_main
 			test_pxp_stale_ctx_execution(i915);
 		igt_subtest("verify-pxp-stale-buf-execution")
 			test_pxp_stale_buf_execution(i915);
+		igt_subtest("verify-pxp-stale-buf-optout-execution")
+			test_pxp_stale_buf_optout_execution(i915);
 	}
 
 	igt_fixture {
-- 
2.25.1

[igt-dev] [PATCH i-g-t v11 13/15] Verify execution behavior with stale PXP assets through suspend-resume

[Alan Previn]

Add a subtest to repeat the same previous three scenarios when attempting
to execute work with either stale PXP contexts or buffers but this time
trigger the teardown event via an S3 suspend-resume power state cycle.

NOTE: The end-to-end architecture requirement includes that
any break in the links of the PXP sessions needs to trigger a
full teardown and the application needs to be made aware of that
allowing it to re-establish the end-to-end pipeline of buffers,
contexts and renders again if it chooses to. This stricter
behavior targets only contexts created with PXP enabled.

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 tests/i915/gem_pxp.c | 65 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 65 insertions(+)

diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
index 8e3bc3cf..0ccba6aa 100644
--- a/tests/i915/gem_pxp.c
+++ b/tests/i915/gem_pxp.c
@@ -850,6 +850,69 @@ static void test_pxp_stale_buf_optout_execution(int i915)
 	free_exec_assets(i915, &data);
 }
 
+static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_data *pm)
+{
+	int ret;
+	struct simple_exec_assets data[3] = {{0}, {0}, {0}};
+	uint32_t ctx2;
+	struct intel_bb *ibb2;
+
+	/*
+	 * For asset data[0]: Use normal buffers for testing for invalidation
+	 * of protected contexts to ensure kernel is catching
+	 * the invalidated context (not buffer)
+	 */
+	prepare_exec_assets(i915, &data[0], true, false);
+	ret = gem_execbuf_flush_store_dw(i915, data[0].ibb, data[0].ctx, data[0].fencebuf);
+	igt_assert(ret == 0);
+
+	/*
+	 * For asset data[1]: Use pxp buffers with pxp context for testing for invalidation
+	 * of protected buffers.
+	 */
+	prepare_exec_assets(i915, &data[1], true, true);
+	ret = gem_execbuf_flush_store_dw(i915, data[1].ibb, data[1].ctx, data[1].fencebuf);
+	igt_assert(ret == 0);
+
+	/*
+	 * For asset data[2]: Use a normal context for testing opt-out behavior
+	 * when executing with a pxp buffer across a teardown event.
+	 */
+	prepare_exec_assets(i915, &data[2], false, true);
+	ret = gem_execbuf_flush_store_dw(i915, data[2].ibb, data[2].ctx, data[2].fencebuf);
+	igt_assert(ret == 0);
+
+	/* Do an S3 suspend resume cycle which also causes the pxp teardown event */
+	trigger_powermgt_suspend_cycle(i915, pm);
+
+	ret = gem_execbuf_flush_store_dw(i915, data[0].ibb, data[0].ctx, data[0].fencebuf);
+	igt_assert_f((ret == -EIO), "Executing stale pxp context didn't fail with -EIO\n");
+
+	/*
+	 * For asset data[1]: after teardown, alloc new assets for context but
+	 * reuse the bo to ensure the kernel is catching the
+	 * invalidated bo (not context)
+	 */
+	ret = create_ctx_with_params(i915, true, true, true, false, &ctx2);
+	igt_assert_eq(ret, 0);
+	igt_assert_eq(get_ctx_protected_param(i915, ctx2), 1);
+	ibb2 = intel_bb_create_with_context(i915, ctx2, 4096);
+	igt_assert(ibb2);
+	intel_bb_remove_intel_buf(data[1].ibb, data[1].fencebuf);
+	intel_bb_add_intel_buf(ibb2, data[1].fencebuf, true);
+	ret = gem_execbuf_flush_store_dw(i915, ibb2, ctx2, data[1].fencebuf);
+	igt_assert_f((ret == -ENOEXEC), "Executing stale pxp buffer didn't fail with -ENOEXEC\n");
+
+	ret = gem_execbuf_flush_store_dw(i915, data[2].ibb, data[2].ctx, data[2].fencebuf);
+	igt_assert_f((ret == 0), "Opt-out-execution with stale pxp buffer didn't succeed\n");
+
+	free_exec_assets(i915, &data[0]);
+	intel_bb_destroy(ibb2);
+	gem_context_destroy(i915, ctx2);
+	free_exec_assets(i915, &data[1]);
+	free_exec_assets(i915, &data[2]);
+}
+
 igt_main
 {
 	int i915 = -1;
@@ -945,6 +1008,8 @@ igt_main
 			test_pxp_stale_buf_execution(i915);
 		igt_subtest("verify-pxp-stale-buf-optout-execution")
 			test_pxp_stale_buf_optout_execution(i915);
+		igt_subtest("verify-pxp-execution-after-suspend-resume")
+			test_pxp_pwrcycle_staleasset_execution(i915, &pm);
 	}
 
 	igt_fixture {
-- 
2.25.1

[igt-dev] [PATCH i-g-t v11 14/15] Verify protected surfaces are dma buffer sharable

[Alan Previn]

Verify we can export a protected surface from
protected context A into protected context B (with
different client driver handles) and protected
rendering is successful even after prior file
handle is closed (i.e. pxp specific refcounting
works).

Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 tests/i915/gem_pxp.c | 102 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 102 insertions(+)

diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
index 0ccba6aa..2848e487 100644
--- a/tests/i915/gem_pxp.c
+++ b/tests/i915/gem_pxp.c
@@ -621,6 +621,106 @@ static void test_render_pxp_protsrc_to_protdest(int i915)
 	buf_ops_destroy(bops);
 }
 
+static int export_handle(int fd, uint32_t handle, int *outfd)
+{
+	struct drm_prime_handle args;
+	int ret;
+
+	args.handle = handle;
+	args.flags = DRM_CLOEXEC;
+	args.fd = -1;
+
+	ret = drmIoctl(fd, DRM_IOCTL_PRIME_HANDLE_TO_FD, &args);
+	if (ret)
+		ret = errno;
+	*outfd = args.fd;
+
+	return ret;
+}
+
+static void test_pxp_dmabuffshare_refcnt(void)
+{
+	uint32_t ctx[2], sbo[2], dbo[2];
+	struct intel_buf *sbuf[2], *dbuf[2];
+	struct buf_ops *bops[2];
+	struct intel_bb *ibb[2];
+	int fd[2], dmabuf_fd = 0, ret, n, num_matches = 0;
+	uint32_t encrypted[2][TSTSURF_SIZE/TSTSURF_BYTESPP];
+
+	/* First, create the client driver handles and
+	 * protected dest buffer (is exported via dma-buff
+	 * from first handle and imported to the second).
+	 */
+	for (n = 0; n < 2; ++n) {
+		fd[n] = drm_open_driver(DRIVER_INTEL);
+		igt_require(fd[n]);
+		if (n == 0) {
+			dbo[0] = alloc_and_fill_dest_buff(fd[0], true, TSTSURF_SIZE,
+							  TSTSURF_INITCOLOR1);
+		} else {
+			ret = export_handle(fd[0], dbo[0], &dmabuf_fd);
+			igt_assert(ret == 0);
+			dbo[1] = prime_fd_to_handle(fd[1], dmabuf_fd);
+			igt_assert(dbo[1]);
+		}
+	}
+	/* Repeat twice: Create a full set of assets to perform
+	 * a protected 3D session but using the same dest buffer
+	 * from above.
+	 */
+	for (n = 0; n < 2; ++n) {
+		ret = create_ctx_with_params(fd[n], true, true, true, false, &ctx[n]);
+		igt_assert_eq(ret, 0);
+		igt_assert_eq(get_ctx_protected_param(fd[n], ctx[n]), 1);
+		ibb[n] = intel_bb_create_with_context(fd[n], ctx[n], 4096);
+		intel_bb_set_pxp(ibb[n], true, DISPLAY_APPTYPE,
+				 I915_PROTECTED_CONTENT_DEFAULT_SESSION);
+
+		bops[n] = buf_ops_create(fd[n]);
+		if (n == 1)
+			fill_bo_content(fd[1], dbo[1], TSTSURF_SIZE, TSTSURF_INITCOLOR2);
+
+		dbuf[n] = intel_buf_create_using_handle(bops[n], dbo[n], TSTSURF_WIDTH,
+							TSTSURF_HEIGHT,	TSTSURF_BYTESPP*8, 0,
+							I915_TILING_NONE, 0);
+		intel_buf_set_pxp(dbuf[n], true);
+
+		sbo[n] = alloc_and_fill_dest_buff(fd[n], false, TSTSURF_SIZE, TSTSURF_FILLCOLOR1);
+		sbuf[n] = intel_buf_create_using_handle(bops[n], sbo[n], TSTSURF_WIDTH,
+							TSTSURF_HEIGHT, TSTSURF_BYTESPP*8, 0,
+							I915_TILING_NONE, 0);
+
+		gen12_render_copyfunc(ibb[n], sbuf[n], 0, 0, TSTSURF_WIDTH, TSTSURF_HEIGHT,
+				      dbuf[n], 0, 0);
+		gem_sync(fd[n], dbo[n]);
+
+		assert_bo_content_check(fd[n], dbo[n], COMPARE_COLOR_UNREADIBLE, TSTSURF_SIZE,
+					TSTSURF_FILLCOLOR1, NULL, 0);
+		assert_bo_content_check(fd[n], dbo[n], COPY_BUFFER, TSTSURF_SIZE, 0, encrypted[n],
+					TSTSURF_SIZE);
+
+		/* free up all assets except the dest buffer to
+		 * verify dma buff refcounting is performed on
+		 * the protected dest buffer on the 2nd loop with
+		 * successful reuse in another protected render.
+		 */
+		intel_bb_destroy(ibb[n]);
+		intel_buf_destroy(sbuf[n]);
+		intel_buf_destroy(dbuf[n]);
+		gem_close(fd[n], sbo[n]);
+		gem_close(fd[n], dbo[n]);
+		gem_context_destroy(fd[n], ctx[n]);
+		close(fd[n]);
+	}
+
+	/* Verify that encrypted output across loops were equal */
+	for (n = 0; n < (TSTSURF_SIZE/4); ++n)
+		if (encrypted[0][n] == encrypted[1][n])
+			++num_matches;
+	igt_assert(num_matches == (TSTSURF_SIZE/4));
+}
+
+
 static void init_powermgt_resources(int i915, struct powermgt_data *pm)
 {
 	pm->debugfsdir = igt_debugfs_dir(i915);
@@ -989,6 +1089,8 @@ igt_main
 			test_render_pxp_src_to_protdest(i915);
 		igt_subtest("protected-encrypted-src-copy-not-readible")
 			test_render_pxp_protsrc_to_protdest(i915);
+		igt_subtest("dmabuf-shared-protected-dst-is-context-refcounted")
+			test_pxp_dmabuffshare_refcnt();
 	}
 	igt_subtest_group {
 		igt_fixture {
-- 
2.25.1

[igt-dev] [PATCH i-g-t v11 15/15] tests/i915_pxp: CRC validation for display tests.

[Alan Previn]

From: Karthik B S <karthik.b.s@intel.com>

Added subtests to validate pxp using CRC validation.

Signed-off-by: Karthik B S <karthik.b.s@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
 tests/i915/gem_pxp.c | 163 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 163 insertions(+)

diff --git a/tests/i915/gem_pxp.c b/tests/i915/gem_pxp.c
index 2848e487..79040165 100644
--- a/tests/i915/gem_pxp.c
+++ b/tests/i915/gem_pxp.c
@@ -437,6 +437,7 @@ static uint32_t alloc_and_fill_dest_buff(int i915, bool protected, uint32_t size
 #define TSTSURF_INITCOLOR1  0x12341234
 #define TSTSURF_INITCOLOR2  0x56785678
 #define TSTSURF_INITCOLOR3  0xabcdabcd
+#define TSTSURF_GREENCOLOR  0xFF00FF00
 
 static void test_render_baseline(int i915)
 {
@@ -1013,6 +1014,152 @@ static void test_pxp_pwrcycle_staleasset_execution(int i915, struct powermgt_dat
 	free_exec_assets(i915, &data[2]);
 }
 
+static void setup_protected_fb(int i915, int width, int height, igt_fb_t *fb, uint32_t ctx)
+{
+	int err;
+	uint32_t srcbo;
+	struct intel_buf *srcbuf, *dstbuf;
+	struct buf_ops *bops;
+	struct intel_bb *ibb;
+	uint32_t devid;
+	igt_render_copyfunc_t rendercopy;
+
+	devid = intel_get_drm_devid(i915);
+	igt_assert(devid);
+
+	rendercopy = igt_get_render_copyfunc(devid);
+	igt_assert(rendercopy);
+
+	bops = buf_ops_create(i915);
+	igt_assert(bops);
+
+	igt_init_fb(fb, i915, width, height, DRM_FORMAT_XRGB8888, DRM_FORMAT_MOD_NONE,
+		    IGT_COLOR_YCBCR_BT709, IGT_COLOR_YCBCR_LIMITED_RANGE);
+
+	igt_calc_fb_size(i915, width, height, DRM_FORMAT_XRGB8888, DRM_FORMAT_MOD_NONE,
+			 &fb->size, &fb->strides[0]);
+
+	err = create_bo_ext(i915, fb->size, true, &(fb->gem_handle));
+	igt_assert_eq(err, 0);
+	igt_assert(fb->gem_handle);
+
+	err = __gem_set_tiling(i915, fb->gem_handle, igt_fb_mod_to_tiling(fb->modifier),
+			       fb->strides[0]);
+	igt_assert(err == 0 || err == -EOPNOTSUPP);
+
+	do_or_die(__kms_addfb(fb->fd, fb->gem_handle, fb->width, fb->height, fb->drm_format,
+			      fb->modifier, fb->strides, fb->offsets, fb->num_planes,
+			      DRM_MODE_FB_MODIFIERS, &fb->fb_id));
+
+	dstbuf = intel_buf_create_using_handle(bops, fb->gem_handle, fb->width, fb->height,
+					       fb->plane_bpp[0], 0,
+					       igt_fb_mod_to_tiling(fb->modifier), 0);
+	dstbuf->is_protected = true;
+
+	srcbo = alloc_and_fill_dest_buff(i915, false, fb->size, TSTSURF_GREENCOLOR);
+	srcbuf = intel_buf_create_using_handle(bops, srcbo, fb->width, fb->height,
+					       fb->plane_bpp[0], 0,
+					       igt_fb_mod_to_tiling(fb->modifier), 0);
+
+	ibb = intel_bb_create_with_context(i915, ctx, 4096);
+	igt_assert(ibb);
+
+	ibb->pxp.enabled = true;
+	ibb->pxp.apptype = DISPLAY_APPTYPE;
+	ibb->pxp.appid = I915_PROTECTED_CONTENT_DEFAULT_SESSION;
+
+	gen12_render_copyfunc(ibb, srcbuf, 0, 0, fb->width, fb->height, dstbuf, 0, 0);
+
+	gem_sync(i915, fb->gem_handle);
+	assert_bo_content_check(i915, fb->gem_handle, COMPARE_COLOR_UNREADIBLE, fb->size,
+				TSTSURF_GREENCOLOR, NULL, 0);
+
+	intel_bb_destroy(ibb);
+	intel_buf_destroy(srcbuf);
+	gem_close(i915, srcbo);
+}
+
+#define KERNEL_AUTH_TIME_ALLOWED_MSEC		(3 *  6 * 1000)
+#define KERNEL_DISABLE_TIME_ALLOWED_MSEC	(1 * 1000)
+
+static void test_display_protected_crc(int i915, igt_display_t *display)
+{
+	igt_output_t *output;
+	drmModeModeInfo *mode;
+	igt_fb_t ref_fb, protected_fb;
+	igt_plane_t *plane;
+	igt_pipe_t *pipe;
+	igt_pipe_crc_t *pipe_crc;
+	igt_crc_t ref_crc, new_crc;
+	int width = 0, height = 0, i = 0, ret;
+	uint32_t ctx;
+
+	ret = create_ctx_with_params(i915, true, true, true, false, &ctx);
+	igt_assert_eq(ret, 0);
+
+	for_each_connected_output(display, output) {
+		mode = igt_output_get_mode(output);
+
+		width = max(width, mode->hdisplay);
+		height = max(height, mode->vdisplay);
+	}
+
+	igt_create_color_fb(i915, width, height, DRM_FORMAT_XRGB8888, DRM_FORMAT_MOD_NONE,
+			    0, 1, 0, &ref_fb);
+
+	/* Do a modeset on all outputs */
+	for_each_connected_output(display, output) {
+		mode = igt_output_get_mode(output);
+		pipe = &display->pipes[i];
+		plane = igt_pipe_get_plane_type(pipe, DRM_PLANE_TYPE_PRIMARY);
+		igt_require(igt_pipe_connector_valid(i, output));
+		igt_output_set_pipe(output, i);
+
+		igt_plane_set_fb(plane, &ref_fb);
+		igt_fb_set_size(&ref_fb, plane, mode->hdisplay, mode->vdisplay);
+		igt_plane_set_size(plane, mode->hdisplay, mode->vdisplay);
+
+		igt_display_commit2(display, COMMIT_ATOMIC);
+		i++;
+	}
+
+	setup_protected_fb(i915, width, height, &protected_fb, ctx);
+
+	for_each_connected_output(display, output) {
+		mode = igt_output_get_mode(output);
+		pipe = &display->pipes[output->pending_pipe];
+		pipe_crc = igt_pipe_crc_new(i915, pipe->pipe, INTEL_PIPE_CRC_SOURCE_AUTO);
+		plane = igt_pipe_get_plane_type(pipe, DRM_PLANE_TYPE_PRIMARY);
+		igt_require(igt_pipe_connector_valid(pipe->pipe, output));
+		igt_output_set_pipe(output, pipe->pipe);
+
+		igt_plane_set_fb(plane, &ref_fb);
+		igt_fb_set_size(&ref_fb, plane, mode->hdisplay, mode->vdisplay);
+		igt_plane_set_size(plane, mode->hdisplay, mode->vdisplay);
+
+		igt_display_commit2(display, COMMIT_ATOMIC);
+		igt_pipe_crc_collect_crc(pipe_crc, &ref_crc);
+
+		igt_plane_set_fb(plane, &protected_fb);
+		igt_fb_set_size(&protected_fb, plane, mode->hdisplay, mode->vdisplay);
+		igt_plane_set_size(plane, mode->hdisplay, mode->vdisplay);
+
+		igt_display_commit2(display, COMMIT_ATOMIC);
+		igt_pipe_crc_collect_crc(pipe_crc, &new_crc);
+		igt_assert_crc_equal(&ref_crc, &new_crc);
+
+		/*
+		 * Testing with one pipe-output combination is sufficient.
+		 * So break the loop.
+		 */
+		break;
+	}
+
+	gem_context_destroy(i915, ctx);
+	igt_remove_fb(i915, &ref_fb);
+	igt_remove_fb(i915, &protected_fb);
+}
+
 igt_main
 {
 	int i915 = -1;
@@ -1020,6 +1167,7 @@ igt_main
 	struct powermgt_data pm = {0};
 	igt_render_copyfunc_t rendercopy = NULL;
 	uint32_t devid = 0;
+	igt_display_t display;
 
 	igt_fixture
 	{
@@ -1113,6 +1261,21 @@ igt_main
 		igt_subtest("verify-pxp-execution-after-suspend-resume")
 			test_pxp_pwrcycle_staleasset_execution(i915, &pm);
 	}
+	igt_subtest_group {
+		igt_fixture {
+			igt_require(pxp_supported);
+			devid = intel_get_drm_devid(i915);
+			igt_assert(devid);
+			rendercopy = igt_get_render_copyfunc(devid);
+			igt_require(rendercopy);
+
+			igt_require_pipe_crc(i915);
+			igt_display_require(&display, i915);
+		}
+		igt_describe("Test the display CRC");
+		igt_subtest("display-protected-crc")
+			test_display_protected_crc(i915, &display);
+	}
 
 	igt_fixture {
 		close(i915);
-- 
2.25.1

[igt-dev] ✓ Fi.CI.BAT: success for Introduce PXP Test (rev11)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 8199 bytes --]

== Series Details ==

Series: Introduce PXP Test (rev11)
URL   : https://patchwork.freedesktop.org/series/87570/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10605 -> IGTPW_6235
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_6235:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_pm_rpm@module-reload:
    - {fi-jsl-1}:         [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-jsl-1/igt@i915_pm_rpm@module-reload.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/fi-jsl-1/igt@i915_pm_rpm@module-reload.html

  * igt@runner@aborted:
    - {fi-jsl-1}:         NOTRUN -> [FAIL][3]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/fi-jsl-1/igt@runner@aborted.html

  
Known issues
------------

  Here are the changes found in IGTPW_6235 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_basic@cs-gfx:
    - fi-skl-6700k2:      NOTRUN -> [SKIP][4] ([fdo#109271]) +17 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/fi-skl-6700k2/igt@amdgpu/amd_basic@cs-gfx.html

  * igt@amdgpu/amd_basic@cs-sdma:
    - fi-cfl-8109u:       NOTRUN -> [SKIP][5] ([fdo#109271]) +17 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/fi-cfl-8109u/igt@amdgpu/amd_basic@cs-sdma.html
    - fi-kbl-7500u:       NOTRUN -> [SKIP][6] ([fdo#109271]) +17 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/fi-kbl-7500u/igt@amdgpu/amd_basic@cs-sdma.html

  * igt@amdgpu/amd_basic@semaphore:
    - fi-icl-y:           NOTRUN -> [SKIP][7] ([fdo#109315]) +17 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/fi-icl-y/igt@amdgpu/amd_basic@semaphore.html

  * igt@amdgpu/amd_cs_nop@sync-fork-gfx0:
    - fi-cfl-8700k:       NOTRUN -> [SKIP][8] ([fdo#109271]) +17 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/fi-cfl-8700k/igt@amdgpu/amd_cs_nop@sync-fork-gfx0.html

  * igt@core_hotunplug@unbind-rebind:
    - fi-rkl-guc:         [PASS][9] -> [INCOMPLETE][10] ([i915#4130])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-rkl-guc/igt@core_hotunplug@unbind-rebind.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/fi-rkl-guc/igt@core_hotunplug@unbind-rebind.html
    - fi-icl-u2:          [PASS][11] -> [INCOMPLETE][12] ([i915#4130])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-icl-u2/igt@core_hotunplug@unbind-rebind.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/fi-icl-u2/igt@core_hotunplug@unbind-rebind.html
    - fi-skl-guc:         [PASS][13] -> [INCOMPLETE][14] ([i915#4130])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-skl-guc/igt@core_hotunplug@unbind-rebind.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/fi-skl-guc/igt@core_hotunplug@unbind-rebind.html

  
#### Possible fixes ####

  * igt@core_hotunplug@unbind-rebind:
    - fi-cfl-8700k:       [INCOMPLETE][15] ([i915#4130]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-cfl-8700k/igt@core_hotunplug@unbind-rebind.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/fi-cfl-8700k/igt@core_hotunplug@unbind-rebind.html
    - fi-kbl-7500u:       [INCOMPLETE][17] ([i915#4130]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-kbl-7500u/igt@core_hotunplug@unbind-rebind.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/fi-kbl-7500u/igt@core_hotunplug@unbind-rebind.html
    - fi-cfl-8109u:       [INCOMPLETE][19] ([i915#4130]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-cfl-8109u/igt@core_hotunplug@unbind-rebind.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/fi-cfl-8109u/igt@core_hotunplug@unbind-rebind.html

  * igt@i915_module_load@reload:
    - fi-skl-6700k2:      [INCOMPLETE][21] ([i915#4136]) -> [PASS][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-skl-6700k2/igt@i915_module_load@reload.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/fi-skl-6700k2/igt@i915_module_load@reload.html
    - fi-icl-y:           [INCOMPLETE][23] ([i915#4130]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-icl-y/igt@i915_module_load@reload.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/fi-icl-y/igt@i915_module_load@reload.html

  
#### Warnings ####

  * igt@i915_module_load@reload:
    - fi-cml-u2:          [INCOMPLETE][25] ([i915#4130] / [i915#4136]) -> [INCOMPLETE][26] ([i915#4136])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-cml-u2/igt@i915_module_load@reload.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/fi-cml-u2/igt@i915_module_load@reload.html
    - fi-kbl-7567u:       [DMESG-WARN][27] ([i915#4136]) -> [INCOMPLETE][28] ([i915#4136])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-kbl-7567u/igt@i915_module_load@reload.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/fi-kbl-7567u/igt@i915_module_load@reload.html
    - fi-kbl-guc:         [INCOMPLETE][29] ([i915#4139]) -> [INCOMPLETE][30] ([i915#4130] / [i915#4139])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/fi-kbl-guc/igt@i915_module_load@reload.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/fi-kbl-guc/igt@i915_module_load@reload.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [i915#2932]: https://gitlab.freedesktop.org/drm/intel/issues/2932
  [i915#3690]: https://gitlab.freedesktop.org/drm/intel/issues/3690
  [i915#4130]: https://gitlab.freedesktop.org/drm/intel/issues/4130
  [i915#4136]: https://gitlab.freedesktop.org/drm/intel/issues/4136
  [i915#4139]: https://gitlab.freedesktop.org/drm/intel/issues/4139


Participating hosts (38 -> 29)
------------------------------

  Missing    (9): fi-kbl-soraka fi-ilk-m540 fi-rkl-11600 bat-dg1-6 fi-tgl-u2 fi-hsw-4200u fi-ctg-p8600 bat-jsl-2 fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_6211 -> IGTPW_6235

  CI-20190529: 20190529
  CI_DRM_10605: e61e36045f57a5aaeef91f54274937843ee3d0d5 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_6235: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/index.html
  IGT_6211: 7b275b3eb17ddf6e7c5b7b9ba359b7f5345a5311 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git



== Testlist changes ==

+igt@gem_pxp@create-protected-buffer
+igt@gem_pxp@create-regular-buffer
+igt@gem_pxp@create-regular-context-1
+igt@gem_pxp@create-regular-context-2
+igt@gem_pxp@create-valid-protected-context
+igt@gem_pxp@display-protected-crc
+igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted
+igt@gem_pxp@fail-invalid-protected-context
+igt@gem_pxp@hw-rejects-pxp-buffer
+igt@gem_pxp@hw-rejects-pxp-context
+igt@gem_pxp@protected-encrypted-src-copy-not-readible
+igt@gem_pxp@protected-raw-src-copy-not-readible
+igt@gem_pxp@regular-baseline-src-copy-readible
+igt@gem_pxp@reject-modify-context-protection-off-1
+igt@gem_pxp@reject-modify-context-protection-off-2
+igt@gem_pxp@reject-modify-context-protection-off-3
+igt@gem_pxp@reject-modify-context-protection-on
+igt@gem_pxp@verify-pxp-execution-after-suspend-resume
+igt@gem_pxp@verify-pxp-key-change-after-suspend-resume
+igt@gem_pxp@verify-pxp-stale-buf-execution
+igt@gem_pxp@verify-pxp-stale-buf-optout-execution
+igt@gem_pxp@verify-pxp-stale-ctx-execution

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/index.html

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[igt-dev] ✓ Fi.CI.IGT: success for Introduce PXP Test (rev11)

[Patchwork]

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== Series Details ==

Series: Introduce PXP Test (rev11)
URL   : https://patchwork.freedesktop.org/series/87570/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10605_full -> IGTPW_6235_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_6235_full:

### IGT changes ###

#### Possible regressions ####

  * {igt@gem_pxp@create-regular-context-1} (NEW):
    - shard-iclb:         NOTRUN -> [SKIP][1] +18 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-iclb1/igt@gem_pxp@create-regular-context-1.html

  * {igt@gem_pxp@hw-rejects-pxp-buffer} (NEW):
    - shard-tglb:         NOTRUN -> [FAIL][2]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-tglb5/igt@gem_pxp@hw-rejects-pxp-buffer.html

  * {igt@gem_pxp@hw-rejects-pxp-context} (NEW):
    - shard-iclb:         NOTRUN -> [FAIL][3] +1 similar issue
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-iclb1/igt@gem_pxp@hw-rejects-pxp-context.html
    - shard-kbl:          NOTRUN -> [FAIL][4]
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-kbl4/igt@gem_pxp@hw-rejects-pxp-context.html

  * {igt@gem_pxp@regular-baseline-src-copy-readible} (NEW):
    - shard-tglb:         NOTRUN -> [SKIP][5] +18 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-tglb1/igt@gem_pxp@regular-baseline-src-copy-readible.html

  
New tests
---------

  New tests have been introduced between CI_DRM_10605_full and IGTPW_6235_full:

### New IGT tests (22) ###

  * igt@gem_pxp@create-protected-buffer:
    - Statuses :
    - Exec time: [None] s

  * igt@gem_pxp@create-regular-buffer:
    - Statuses : 3 skip(s)
    - Exec time: [0.0] s

  * igt@gem_pxp@create-regular-context-1:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@gem_pxp@create-regular-context-2:
    - Statuses : 3 skip(s)
    - Exec time: [0.0] s

  * igt@gem_pxp@create-valid-protected-context:
    - Statuses : 3 skip(s)
    - Exec time: [0.0] s

  * igt@gem_pxp@display-protected-crc:
    - Statuses : 3 skip(s)
    - Exec time: [0.0] s

  * igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@gem_pxp@fail-invalid-protected-context:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@gem_pxp@hw-rejects-pxp-buffer:
    - Statuses : 2 fail(s)
    - Exec time: [0.01, 0.06] s

  * igt@gem_pxp@hw-rejects-pxp-context:
    - Statuses : 2 fail(s)
    - Exec time: [0.01, 0.02] s

  * igt@gem_pxp@protected-encrypted-src-copy-not-readible:
    - Statuses : 3 skip(s)
    - Exec time: [0.0] s

  * igt@gem_pxp@protected-raw-src-copy-not-readible:
    - Statuses : 3 skip(s)
    - Exec time: [0.0] s

  * igt@gem_pxp@regular-baseline-src-copy-readible:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@gem_pxp@reject-modify-context-protection-off-1:
    - Statuses : 3 skip(s)
    - Exec time: [0.0] s

  * igt@gem_pxp@reject-modify-context-protection-off-2:
    - Statuses : 3 skip(s)
    - Exec time: [0.0] s

  * igt@gem_pxp@reject-modify-context-protection-off-3:
    - Statuses : 2 skip(s)
    - Exec time: [0.0] s

  * igt@gem_pxp@reject-modify-context-protection-on:
    - Statuses : 3 skip(s)
    - Exec time: [0.0] s

  * igt@gem_pxp@verify-pxp-execution-after-suspend-resume:
    - Statuses : 3 skip(s)
    - Exec time: [0.0] s

  * igt@gem_pxp@verify-pxp-key-change-after-suspend-resume:
    - Statuses : 3 skip(s)
    - Exec time: [0.0] s

  * igt@gem_pxp@verify-pxp-stale-buf-execution:
    - Statuses : 3 skip(s)
    - Exec time: [0.0] s

  * igt@gem_pxp@verify-pxp-stale-buf-optout-execution:
    - Statuses : 3 skip(s)
    - Exec time: [0.0] s

  * igt@gem_pxp@verify-pxp-stale-ctx-execution:
    - Statuses : 3 skip(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in IGTPW_6235_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_sseu@engines:
    - shard-tglb:         NOTRUN -> [SKIP][6] ([i915#280])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-tglb5/igt@gem_ctx_sseu@engines.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-tglb:         [PASS][7] -> [FAIL][8] ([i915#2842])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-tglb6/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-iclb:         NOTRUN -> [FAIL][9] ([i915#2842])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-iclb7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
    - shard-tglb:         NOTRUN -> [FAIL][10] ([i915#2842])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-tglb1/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_exec_params@rsvd2-dirt:
    - shard-tglb:         NOTRUN -> [SKIP][11] ([fdo#109283])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-tglb6/igt@gem_exec_params@rsvd2-dirt.html

  * igt@gem_huc_copy@huc-copy:
    - shard-kbl:          NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#2190])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-kbl4/igt@gem_huc_copy@huc-copy.html

  * igt@gem_media_vme:
    - shard-tglb:         NOTRUN -> [SKIP][13] ([i915#284])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-tglb2/igt@gem_media_vme.html

  * igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs:
    - shard-iclb:         NOTRUN -> [SKIP][14] ([i915#768]) +2 similar issues
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-iclb4/igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs.html

  * igt@gem_userptr_blits@create-destroy-unsync:
    - shard-tglb:         NOTRUN -> [SKIP][15] ([i915#3297])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-tglb1/igt@gem_userptr_blits@create-destroy-unsync.html
    - shard-iclb:         NOTRUN -> [SKIP][16] ([i915#3297])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-iclb7/igt@gem_userptr_blits@create-destroy-unsync.html

  * igt@gem_userptr_blits@input-checking:
    - shard-kbl:          NOTRUN -> [DMESG-WARN][17] ([i915#3002])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-kbl6/igt@gem_userptr_blits@input-checking.html

  * igt@gen3_render_mixed_blits:
    - shard-tglb:         NOTRUN -> [SKIP][18] ([fdo#109289]) +2 similar issues
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-tglb2/igt@gen3_render_mixed_blits.html

  * igt@gen3_render_tiledx_blits:
    - shard-iclb:         NOTRUN -> [SKIP][19] ([fdo#109289]) +4 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-iclb1/igt@gen3_render_tiledx_blits.html

  * igt@gen9_exec_parse@bb-secure:
    - shard-tglb:         NOTRUN -> [SKIP][20] ([i915#2856]) +2 similar issues
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-tglb7/igt@gen9_exec_parse@bb-secure.html

  * igt@gen9_exec_parse@unaligned-access:
    - shard-iclb:         NOTRUN -> [SKIP][21] ([i915#2856]) +3 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-iclb2/igt@gen9_exec_parse@unaligned-access.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-iclb:         [PASS][22] -> [FAIL][23] ([i915#454])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-iclb8/igt@i915_pm_dc@dc6-psr.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-iclb4/igt@i915_pm_dc@dc6-psr.html

  * igt@i915_pm_rpm@gem-execbuf-stress-pc8:
    - shard-iclb:         NOTRUN -> [SKIP][24] ([fdo#109293] / [fdo#109506])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-iclb7/igt@i915_pm_rpm@gem-execbuf-stress-pc8.html
    - shard-tglb:         NOTRUN -> [SKIP][25] ([fdo#109506] / [i915#2411]) +1 similar issue
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-tglb1/igt@i915_pm_rpm@gem-execbuf-stress-pc8.html

  * igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
    - shard-tglb:         NOTRUN -> [SKIP][26] ([fdo#111644] / [i915#1397] / [i915#2411])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-tglb8/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
    - shard-iclb:         NOTRUN -> [SKIP][27] ([fdo#110892])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-iclb4/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html

  * igt@i915_suspend@fence-restore-untiled:
    - shard-kbl:          NOTRUN -> [DMESG-WARN][28] ([i915#180])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-kbl7/igt@i915_suspend@fence-restore-untiled.html

  * igt@kms_big_fb@linear-8bpp-rotate-270:
    - shard-tglb:         NOTRUN -> [SKIP][29] ([fdo#111614])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-tglb7/igt@kms_big_fb@linear-8bpp-rotate-270.html

  * igt@kms_big_fb@x-tiled-64bpp-rotate-90:
    - shard-iclb:         NOTRUN -> [SKIP][30] ([fdo#110725] / [fdo#111614])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-iclb8/igt@kms_big_fb@x-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-kbl:          NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#3777]) +1 similar issue
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-kbl3/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@yf-tiled-8bpp-rotate-90:
    - shard-iclb:         NOTRUN -> [SKIP][32] ([fdo#110723]) +2 similar issues
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-iclb7/igt@kms_big_fb@yf-tiled-8bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-tglb:         NOTRUN -> [SKIP][33] ([fdo#111615]) +3 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-tglb1/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_mc_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][34] ([i915#3689] / [i915#3886]) +1 similar issue
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-tglb1/igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
    - shard-kbl:          NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#3886]) +15 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-kbl4/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][36] ([i915#3689]) +6 similar issues
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-tglb8/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_ccs.html

  * igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
    - shard-iclb:         NOTRUN -> [SKIP][37] ([fdo#109278] / [i915#3886]) +4 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-iclb1/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html

  * igt@kms_color@pipe-d-ctm-max:
    - shard-iclb:         NOTRUN -> [SKIP][38] ([fdo#109278] / [i915#1149]) +1 similar issue
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-iclb4/igt@kms_color@pipe-d-ctm-max.html

  * igt@kms_color_chamelium@pipe-a-ctm-blue-to-red:
    - shard-kbl:          NOTRUN -> [SKIP][39] ([fdo#109271] / [fdo#111827]) +32 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-kbl4/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html

  * igt@kms_color_chamelium@pipe-c-ctm-green-to-red:
    - shard-iclb:         NOTRUN -> [SKIP][40] ([fdo#109284] / [fdo#111827]) +3 similar issues
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-iclb2/igt@kms_color_chamelium@pipe-c-ctm-green-to-red.html

  * igt@kms_color_chamelium@pipe-d-ctm-max:
    - shard-tglb:         NOTRUN -> [SKIP][41] ([fdo#109284] / [fdo#111827]) +5 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-tglb3/igt@kms_color_chamelium@pipe-d-ctm-max.html

  * igt@kms_color_chamelium@pipe-d-ctm-negative:
    - shard-iclb:         NOTRUN -> [SKIP][42] ([fdo#109278] / [fdo#109284] / [fdo#111827]) +1 similar issue
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-iclb1/igt@kms_color_chamelium@pipe-d-ctm-negative.html

  * igt@kms_content_protection@dp-mst-lic-type-1:
    - shard-tglb:         NOTRUN -> [SKIP][43] ([i915#3116])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-tglb5/igt@kms_content_protection@dp-mst-lic-type-1.html

  * igt@kms_content_protection@legacy:
    - shard-kbl:          NOTRUN -> [TIMEOUT][44] ([i915#1319]) +1 similar issue
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-kbl4/igt@kms_content_protection@legacy.html

  * igt@kms_content_protection@type1:
    - shard-iclb:         NOTRUN -> [SKIP][45] ([fdo#109300] / [fdo#111066])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-iclb8/igt@kms_content_protection@type1.html

  * igt@kms_cursor_crc@pipe-a-cursor-suspend:
    - shard-tglb:         [PASS][46] -> [INCOMPLETE][47] ([i915#2828] / [i915#456])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-tglb6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-tglb7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html

  * igt@kms_cursor_crc@pipe-b-cursor-32x10-random:
    - shard-tglb:         NOTRUN -> [SKIP][48] ([i915#3359]) +3 similar issues
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-tglb1/igt@kms_cursor_crc@pipe-b-cursor-32x10-random.html

  * igt@kms_cursor_crc@pipe-c-cursor-32x32-rapid-movement:
    - shard-tglb:         NOTRUN -> [SKIP][49] ([i915#3319])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-tglb8/igt@kms_cursor_crc@pipe-c-cursor-32x32-rapid-movement.html

  * igt@kms_cursor_crc@pipe-c-cursor-512x512-random:
    - shard-iclb:         NOTRUN -> [SKIP][50] ([fdo#109278] / [fdo#109279]) +2 similar issues
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-iclb7/igt@kms_cursor_crc@pipe-c-cursor-512x512-random.html

  * igt@kms_cursor_crc@pipe-d-cursor-512x512-offscreen:
    - shard-tglb:         NOTRUN -> [SKIP][51] ([fdo#109279] / [i915#3359]) +5 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-tglb6/igt@kms_cursor_crc@pipe-d-cursor-512x512-offscreen.html

  * igt@kms_cursor_crc@pipe-d-cursor-64x21-sliding:
    - shard-iclb:         NOTRUN -> [SKIP][52] ([fdo#109278]) +12 similar issues
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-iclb6/igt@kms_cursor_crc@pipe-d-cursor-64x21-sliding.html

  * igt@kms_cursor_crc@pipe-d-cursor-suspend:
    - shard-kbl:          NOTRUN -> [SKIP][53] ([fdo#109271]) +275 similar issues
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-kbl7/igt@kms_cursor_crc@pipe-d-cursor-suspend.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic:
    - shard-tglb:         NOTRUN -> [SKIP][54] ([fdo#111825]) +23 similar issues
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-tglb8/igt@kms_cursor_legacy@cursora-vs-flipb-atomic.html
    - shard-iclb:         NOTRUN -> [SKIP][55] ([fdo#109274] / [fdo#109278]) +1 similar issue
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-iclb4/igt@kms_cursor_legacy@cursora-vs-flipb-atomic.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-kbl:          NOTRUN -> [INCOMPLETE][56] ([i915#155] / [i915#180] / [i915#636])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-kbl4/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip@2x-flip-vs-rmfb-interruptible:
    - shard-iclb:         NOTRUN -> [SKIP][57] ([fdo#109274]) +2 similar issues
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-iclb6/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-kbl:          [PASS][58] -> [DMESG-WARN][59] ([i915#180]) +3 similar issues
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-pwrite:
    - shard-iclb:         NOTRUN -> [SKIP][60] ([fdo#109280]) +14 similar issues
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-pwrite.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence:
    - shard-kbl:          NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#533]) +3 similar issues
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-kbl6/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
    - shard-tglb:         [PASS][62] -> [INCOMPLETE][63] ([i915#456]) +2 similar issues
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-tglb6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-tglb7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html

  * igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
    - shard-kbl:          NOTRUN -> [FAIL][64] ([i915#265]) +1 similar issue
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-kbl1/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
    - shard-kbl:          NOTRUN -> [FAIL][65] ([fdo#108145] / [i915#265]) +2 similar issues
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-kbl2/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html

  * igt@kms_plane_lowres@pipe-b-tiling-none:
    - shard-tglb:         NOTRUN -> [SKIP][66] ([i915#3536])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-tglb3/igt@kms_plane_lowres@pipe-b-tiling-none.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1:
    - shard-kbl:          NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#658]) +6 similar issues
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-kbl3/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4:
    - shard-iclb:         NOTRUN -> [SKIP][68] ([i915#658])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-iclb6/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5:
    - shard-tglb:         NOTRUN -> [SKIP][69] ([i915#2920]) +2 similar issues
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-tglb7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html

  * igt@kms_psr2_su@page_flip:
    - shard-tglb:         NOTRUN -> [SKIP][70] ([i915#1911])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-tglb8/igt@kms_psr2_su@page_flip.html
    - shard-iclb:         NOTRUN -> [SKIP][71] ([fdo#109642] / [fdo#111068] / [i915#658])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-iclb8/igt@kms_psr2_su@page_flip.html

  * igt@kms_psr@psr2_no_drrs:
    - shard-iclb:         [PASS][72] -> [SKIP][73] ([fdo#109441]) +1 similar issue
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-iclb6/igt@kms_psr@psr2_no_drrs.html

  * igt@kms_psr@psr2_sprite_blt:
    - shard-iclb:         NOTRUN -> [SKIP][74] ([fdo#109441]) +1 similar issue
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-iclb3/igt@kms_psr@psr2_sprite_blt.html

  * igt@kms_vrr@flip-suspend:
    - shard-iclb:         NOTRUN -> [SKIP][75] ([fdo#109502])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-iclb7/igt@kms_vrr@flip-suspend.html

  * igt@kms_writeback@writeback-fb-id:
    - shard-kbl:          NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#2437])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-kbl7/igt@kms_writeback@writeback-fb-id.html

  * igt@nouveau_crc@pipe-a-source-rg:
    - shard-iclb:         NOTRUN -> [SKIP][77] ([i915#2530])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-iclb3/igt@nouveau_crc@pipe-a-source-rg.html

  * igt@nouveau_crc@pipe-d-ctx-flip-detection:
    - shard-tglb:         NOTRUN -> [SKIP][78] ([i915#2530])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-tglb3/igt@nouveau_crc@pipe-d-ctx-flip-detection.html

  * igt@sysfs_clients@sema-25:
    - shard-iclb:         NOTRUN -> [SKIP][79] ([i915#2994])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-iclb1/igt@sysfs_clients@sema-25.html
    - shard-tglb:         NOTRUN -> [SKIP][80] ([i915#2994]) +2 similar issues
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-tglb5/igt@sysfs_clients@sema-25.html

  * igt@sysfs_clients@sema-50:
    - shard-kbl:          NOTRUN -> [SKIP][81] ([fdo#109271] / [i915#2994]) +4 similar issues
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-kbl6/igt@sysfs_clients@sema-50.html

  
#### Possible fixes ####

  * igt@core_hotunplug@unbind-rebind:
    - shard-iclb:         [INCOMPLETE][82] ([i915#4130]) -> [PASS][83]
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-iclb3/igt@core_hotunplug@unbind-rebind.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-iclb8/igt@core_hotunplug@unbind-rebind.html

  * igt@gem_eio@unwedge-stress:
    - shard-iclb:         [TIMEOUT][84] ([i915#2369] / [i915#2481] / [i915#3070]) -> [PASS][85]
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-iclb8/igt@gem_eio@unwedge-stress.html
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-iclb2/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-kbl:          [FAIL][86] ([i915#2846]) -> [PASS][87]
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-kbl7/igt@gem_exec_fair@basic-deadline.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-kbl2/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-pace@vcs1:
    - shard-kbl:          [SKIP][88] ([fdo#109271]) -> [PASS][89]
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-kbl6/igt@gem_exec_fair@basic-pace@vcs1.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-kbl7/igt@gem_exec_fair@basic-pace@vcs1.html

  * igt@i915_suspend@forcewake:
    - shard-kbl:          [DMESG-WARN][90] ([i915#180]) -> [PASS][91] +3 similar issues
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-kbl7/igt@i915_suspend@forcewake.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-kbl6/igt@i915_suspend@forcewake.html

  * igt@kms_frontbuffer_tracking@fbcpsr-suspend:
    - shard-tglb:         [INCOMPLETE][92] ([i915#2411] / [i915#456]) -> [PASS][93]
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html

  * igt@kms_psr@psr2_primary_blt:
    - shard-iclb:         [SKIP][94] ([fdo#109441]) -> [PASS][95]
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-iclb1/igt@kms_psr@psr2_primary_blt.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-iclb2/igt@kms_psr@psr2_primary_blt.html

  * igt@perf@polling-small-buf:
    - shard-tglb:         [FAIL][96] ([i915#1722]) -> [PASS][97]
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-tglb6/igt@perf@polling-small-buf.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-tglb6/igt@perf@polling-small-buf.html

  
#### Warnings ####

  * igt@i915_pm_rc6_residency@rc6-fence:
    - shard-iclb:         [WARN][98] ([i915#1804] / [i915#2684]) -> [WARN][99] ([i915#2684]) +1 similar issue
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-iclb7/igt@i915_pm_rc6_residency@rc6-fence.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-iclb1/igt@i915_pm_rc6_residency@rc6-fence.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1:
    - shard-iclb:         [SKIP][100] ([i915#658]) -> [SKIP][101] ([i915#2920])
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-iclb6/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html

  * igt@runner@aborted:
    - shard-kbl:          ([FAIL][102], [FAIL][103], [FAIL][104], [FAIL][105], [FAIL][106], [FAIL][107], [FAIL][108], [FAIL][109], [FAIL][110], [FAIL][111], [FAIL][112]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363] / [i915#602]) -> ([FAIL][113], [FAIL][114], [FAIL][115], [FAIL][116], [FAIL][117], [FAIL][118], [FAIL][119], [FAIL][120], [FAIL][121], [FAIL][122], [FAIL][123], [FAIL][124]) ([fdo#109271] / [i915#1436] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363] / [i915#92])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-kbl3/igt@runner@aborted.html
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-kbl6/igt@runner@aborted.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-kbl6/igt@runner@aborted.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-kbl6/igt@runner@aborted.html
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-kbl3/igt@runner@aborted.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-kbl3/igt@runner@aborted.html
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-kbl7/igt@runner@aborted.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-kbl7/igt@runner@aborted.html
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-kbl7/igt@runner@aborted.html
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-kbl7/igt@runner@aborted.html
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-kbl7/igt@runner@aborted.html
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-kbl4/igt@runner@aborted.html
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-kbl6/igt@runner@aborted.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-kbl3/igt@runner@aborted.html
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-kbl1/igt@runner@aborted.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-kbl4/igt@runner@aborted.html
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-kbl6/igt@runner@aborted.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-kbl1/igt@runner@aborted.html
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-kbl1/igt@runner@aborted.html
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-kbl3/igt@runner@aborted.html
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-kbl7/igt@runner@aborted.html
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-kbl7/igt@runner@aborted.html
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-kbl7/igt@runner@aborted.html
    - shard-iclb:         ([FAIL][125], [FAIL][126]) ([i915#1814] / [i915#3002]) -> ([FAIL][127], [FAIL][128]) ([i915#3002])
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-iclb8/igt@runner@aborted.html
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10605/shard-iclb3/igt@runner@aborted.html
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-iclb2/igt@runner@aborted.html
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/shard-iclb7/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109293]: https://bugs.freedesktop.org/show_bug.cgi?id=109293
  [fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109502]: https://bugs.freedesktop.org/show_bug.cgi?id=109502
  [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
  [fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725
  [fdo#110892]: https://bugs.freedesktop.org/show_bug.cgi?id=110892
  [fdo#111066]: https://bugs.freedesktop.org/show_bug.cgi?id=111066
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#11164

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6235/index.html

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Re: [igt-dev] [PATCH i-g-t v11 00/15] Introduce PXP Test

[Rodrigo Vivi]

On Fri, Sep 17, 2021 at 09:54:21PM -0700, Alan Previn wrote:
> This series adds gem_pxp tests for the new PXP subsystem currently
> being reviewed at https://patchwork.freedesktop.org/series/90504/.
> This series currently includes 4 groups of tests addressing the
> features and restrictions described by Daniele's series :
>    1. test i915 interfaces for allocation of protected bo's
>       and contexts and enforcement of UAPI rule disallowing the
>       modification of parameters after it's been created.
>    2. verify PXP subsystem protected sessions generate encrypted
>       content on protected output buffers and decrypt protected
>       inputs buffers.
>    3. verify i915 PXP auto-teardown succeeds on suspend-resume
>       cycles and gem-exec of stale protected assets fail. Ensure
>       protected-contexts adhere to stricter invalidation
>       enforcement upon teardown event.
>    4. Ensure that display plane decryption works as expected with
>       protected buffers.
> 
> NOTE: This series is on the tenth revision. All R-v-b's have been
> received except UAPI patch which will be dropped at merge time (after
> kernel patches gets merged and igt's drm UAPI gets sync'd).
> 
> Changes from prior rev1 to now:
>    v11:
>       - When detecting hw support, retry pxp context creation
>         multiple times a timeout as per HW SLA.
>       - initialize bo or ctx handles to zero before calling
>         creation ioctl wrapper.

Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

>    v10:
>       - In patch #2, reuse existing gem_create_ext wrapper.
>       - In patch #10, kernel side changed the debugfs file name
>         (but no difference in behavior / usage).
>       - Removed patch #14 from Rev9 as decision on kernel side
>         was to drop the usage of RESET_STATS IOCTL to track
>         invalidated pxp contexts.
>    v9:
>       - Remove patch #2 from rev7 as it was duplicating
>         an existing ioctl wrapper helper
>       - Fix the false-negative warnings when triggering
>         auto-suspend-resume (remove checking if we are
>         suspending after the system has already resumed).
>    v8:
>       - Nothing - mistaken detection from patchwork
>    v7:
>       - In prior rev, Patches #11->13 was testing expected results
>         from calling gem_execbuf with stale pxp-context, pxp-buffer
>         or combinations of them (including an opt-out usage). All
>         of them used a single suspend-resume power state cycles to
>         trigger the PXP teardown event. These patches have been
>         combined into patch #14 that continues to carry the prior rev
>         Rvb.
>       - In its place, the new patches of #11->#13 do the identical
>         set of tests as before (results from gem_execbuf with various
>         combinations of stale pxp context and buffer), but this time
>         using a debugfs file handle that triggers the same code path
>         taken when the HW triggers the pxp teardown. That said, the
>         code is nearly identical as v6 but I did not keep the Rvb's.
>       - In patch #15, RESET_STAT now reports invalidated / banned
>         pxp contexts via the existing batch_active's lost count.
>    v6:
>       - Addressed rev5 review comments for patch #1, #7, #14
>         and #17.
>       - For #17, I'm using Rodrigo's Rv-b because offline 
>         discussions concluded that we couldn't use those
>         test sequences with HDCP and so it was removed it.
>       - Added Rv-b into all patches that received it.
>       - Modified the test requirement from a list of device
>         ids to checking if runtime PXP interface succeeds
>         due to kernel's build config dependency.
>    v5:
>       - Addressed all rev4 review comments. No changes to
>         overall flow and logic compared to the last rev.
>    v4:
>       - Addressed all rev3 review comments. NOTE: that all
>         test cases and code logic are the same but a decent
>         amount of refactoring has occured due to address
>         v3 comments to break out subtests into separate
>         functions while combining certain checks into the same
>         function to reduce test time by minimizing number of
>         suspend-resume power cycles.
>    v3:
>       - Addressed all rev2 review comments.
>       - In line with one of the rev2 comments, a thorough fixup
>         of all line-breaks in function calls was made for a more
>         consistent styling.
>       - Rebased on igt upstream repo and updated to latest kernel
>         UAPI that added GEM_CREATE_EXT.
>    v2: 
>       - Addressed all rev1 review comments except these:
>            1.Chris Wilson : "...have the caller do 1-3 once for its protected
>              context. Call it something like intel_bb_enable_pxp(),
>              intel_bb_set_pxp if it should be reversible.".
>              -  This couldn't be implemented because [1] HW needs different
>              instruction sequences for enabling/disabling PXP depending
>              on the engine class and [2] the pair of "pxp-enable" and "pxp-
>              disable" instructions need to be contained within the same batch
>              that is dispatched to the hardware. That said, implementing
>              internal intel_batchbuffer funtionality for this would conflict
>              with how rendercopy_gen9 uses batch buffer memory by repositioing
>              the pointer and consuming unused portions of the batch buffer as
>              3d state offsets that batchbuffer has no visibility.
>          
>       - Added these additional subtests:
>            1. verify that buffer sharing works across testing pxp context.
>            2. verify teardown bans contexts via DRM_IOCTL_I915_GET_RESET_STAT.
>            3. verify display plane decryption of protected buffers.
> 
> Alan Previn (14):
>   Add PXP UAPI support in i915_drm.h
>   Add basic PXP testing of buffer and context alloc
>   Perform a regular 3d copy as a control checkpoint
>   Add PXP attribute support in batchbuffer and buffer_ops libs
>   Add MI_SET_APPID instruction definition
>   Enable protected session cmd in gen12_render_copyfunc
>   Add subtest to copy raw source to protected dest
>   Add test where both src and dest are protected
>   Verify PXP teardown occurred through suspend-resume
>   Verify execbuf fails with stale PXP context after teardown
>   Verify execbuf fails with stale PXP buffer after teardown
>   Verify execbuf ok with stale PXP buf in opt-out use
>   Verify execution behavior with stale PXP assets through suspend-resume
>   Verify protected surfaces are dma buffer sharable
> 
> Karthik B S (1):
>   tests/i915_pxp: CRC validation for display tests.
> 
>  lib/i915/i915_drm_local.h |  102 +++
>  lib/intel_batchbuffer.c   |   23 +-
>  lib/intel_batchbuffer.h   |   31 +
>  lib/intel_bufops.h        |   15 +
>  lib/intel_reg.h           |    8 +
>  lib/rendercopy_gen9.c     |   57 ++
>  tests/i915/gem_pxp.c      | 1283 +++++++++++++++++++++++++++++++++++++
>  tests/meson.build         |    1 +
>  8 files changed, 1519 insertions(+), 1 deletion(-)
>  create mode 100644 tests/i915/gem_pxp.c
> 
> -- 
> 2.25.1
>