* [Intel-gfx] [PATCH v6 0/9] drm/i915: Suspend / resume backup- and restore of LMEM.
@ 2021-09-22 6:25 ` Thomas Hellström
0 siblings, 0 replies; 39+ messages in thread
From: Thomas Hellström @ 2021-09-22 6:25 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: maarten.lankhorst, matthew.auld
Implement backup and restore of LMEM during suspend / resume.
What complicates things a bit is handling of pinned LMEM memory during
suspend and the fact that we might be dealing with unmappable LMEM in
the future, which makes us want to restrict the number of pinned objects that
need memcpy resume.
The first two patches are prereq patches implementing object content copy
and a generic means of iterating through all objects in a region.
The third patch adds the backup / recover / restore functions and the
two last patches deal with restricting the number of objects we need to
use memcpy for.
v2:
- Some polishing of patch 4/6, see patch commit message for details (Chris
Wilson)
- Rework of patch 3/6.
v3:
- Comment changes in patch 2/6 (Matthew Auld)
- A number of changes to patch 3/6, see commit message.
- Slightly reword comment in patch 5/6. (Matthew Auld).
v4:
- Various cleanups, among other things reworking the ttm / lmem backup-
and resume interfaces somewhat.
v5:
- GuC adaptations. Mark GuC LMEM objects for early resume and increase
the suspend idle timeout.
v6:
- Add two HAX patches to make broken CI happy.
Kai Vehmanen (1):
HAX: component: do not leave master devres group open after bind
Thomas Hellström (8):
drm/i915/ttm: Implement a function to copy the contents of two
TTM-based objects
drm/i915/gem: Implement a function to process all gem objects of a
region
drm/i915/gt: Increase suspend timeout
drm/i915 Implement LMEM backup and restore for suspend / resume
drm/i915/gt: Register the migrate contexts with their engines
drm/i915: Don't back up pinned LMEM context images and rings during
suspend
drm/i915: Reduce the number of objects subject to memcpy recover
HAX: drm/i915/gem: Fix the __i915_gem_is_lmem() function
drivers/base/component.c | 5 +-
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gem/i915_gem_context.c | 4 +-
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 2 +-
.../gpu/drm/i915/gem/i915_gem_object_types.h | 21 +-
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 91 ++++++++
drivers/gpu/drm/i915/gem/i915_gem_pm.h | 1 +
drivers/gpu/drm/i915/gem/i915_gem_region.c | 70 ++++++
drivers/gpu/drm/i915/gem/i915_gem_region.h | 37 ++++
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 99 +++++++--
drivers/gpu/drm/i915/gem/i915_gem_ttm.h | 14 ++
drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c | 206 ++++++++++++++++++
drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.h | 26 +++
.../gpu/drm/i915/gem/selftests/huge_pages.c | 2 +-
drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 2 +-
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 5 +-
drivers/gpu/drm/i915/gt/gen8_ppgtt.h | 4 +-
drivers/gpu/drm/i915/gt/intel_context_types.h | 8 +
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 +
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 23 ++
drivers/gpu/drm/i915/gt/intel_engine_pm.h | 2 +
drivers/gpu/drm/i915/gt/intel_engine_types.h | 7 +
.../drm/i915/gt/intel_execlists_submission.c | 2 +
drivers/gpu/drm/i915/gt/intel_ggtt.c | 3 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 8 +-
drivers/gpu/drm/i915/gt/intel_gtt.c | 3 +-
drivers/gpu/drm/i915/gt/intel_gtt.h | 9 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 3 +-
drivers/gpu/drm/i915/gt/intel_migrate.c | 2 +-
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 13 +-
drivers/gpu/drm/i915/gt/intel_ring.c | 3 +-
.../gpu/drm/i915/gt/intel_ring_submission.c | 3 +
drivers/gpu/drm/i915/gt/mock_engine.c | 2 +
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 3 +-
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 12 +-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 7 +-
drivers/gpu/drm/i915/gvt/scheduler.c | 2 +-
drivers/gpu/drm/i915/i915_drv.c | 4 +-
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 4 +-
41 files changed, 658 insertions(+), 63 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.h
--
2.31.1
^ permalink raw reply [flat|nested] 39+ messages in thread* [PATCH v6 1/9] drm/i915/ttm: Implement a function to copy the contents of two TTM-based objects
2021-09-22 6:25 ` [Intel-gfx] " Thomas Hellström
@ 2021-09-22 6:25 ` Thomas Hellström
-1 siblings, 0 replies; 39+ messages in thread
From: Thomas Hellström @ 2021-09-22 6:25 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: maarten.lankhorst, matthew.auld, Thomas Hellström
When backing up or restoring contents of pinned objects at suspend /
resume time we need to allocate a new object as the backup. Add a function
to facilitate copies between the two. Some data needs to be copied before
the migration context is ready for operation, so make sure we can
disable accelerated copies.
v2:
- Fix a missing return value check (Matthew Auld)
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 69 +++++++++++++++++++++----
drivers/gpu/drm/i915/gem/i915_gem_ttm.h | 4 ++
2 files changed, 64 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 2f672f06b169..22d59510d0c3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -428,6 +428,7 @@ i915_ttm_resource_get_st(struct drm_i915_gem_object *obj,
static int i915_ttm_accel_move(struct ttm_buffer_object *bo,
bool clear,
struct ttm_resource *dst_mem,
+ struct ttm_tt *dst_ttm,
struct sg_table *dst_st)
{
struct drm_i915_private *i915 = container_of(bo->bdev, typeof(*i915),
@@ -437,14 +438,14 @@ static int i915_ttm_accel_move(struct ttm_buffer_object *bo,
struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo);
struct sg_table *src_st;
struct i915_request *rq;
- struct ttm_tt *ttm = bo->ttm;
+ struct ttm_tt *src_ttm = bo->ttm;
enum i915_cache_level src_level, dst_level;
int ret;
if (!i915->gt.migrate.context)
return -EINVAL;
- dst_level = i915_ttm_cache_level(i915, dst_mem, ttm);
+ dst_level = i915_ttm_cache_level(i915, dst_mem, dst_ttm);
if (clear) {
if (bo->type == ttm_bo_type_kernel)
return -EINVAL;
@@ -461,10 +462,10 @@ static int i915_ttm_accel_move(struct ttm_buffer_object *bo,
}
intel_engine_pm_put(i915->gt.migrate.context->engine);
} else {
- src_st = src_man->use_tt ? i915_ttm_tt_get_st(ttm) :
+ src_st = src_man->use_tt ? i915_ttm_tt_get_st(src_ttm) :
obj->ttm.cached_io_st;
- src_level = i915_ttm_cache_level(i915, bo->resource, ttm);
+ src_level = i915_ttm_cache_level(i915, bo->resource, src_ttm);
intel_engine_pm_get(i915->gt.migrate.context->engine);
ret = intel_context_migrate_copy(i915->gt.migrate.context,
NULL, src_st->sgl, src_level,
@@ -484,11 +485,14 @@ static int i915_ttm_accel_move(struct ttm_buffer_object *bo,
static void __i915_ttm_move(struct ttm_buffer_object *bo, bool clear,
struct ttm_resource *dst_mem,
- struct sg_table *dst_st)
+ struct ttm_tt *dst_ttm,
+ struct sg_table *dst_st,
+ bool allow_accel)
{
- int ret;
+ int ret = -EINVAL;
- ret = i915_ttm_accel_move(bo, clear, dst_mem, dst_st);
+ if (allow_accel)
+ ret = i915_ttm_accel_move(bo, clear, dst_mem, dst_ttm, dst_st);
if (ret) {
struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo);
struct intel_memory_region *dst_reg, *src_reg;
@@ -503,7 +507,7 @@ static void __i915_ttm_move(struct ttm_buffer_object *bo, bool clear,
GEM_BUG_ON(!dst_reg || !src_reg);
dst_iter = !cpu_maps_iomem(dst_mem) ?
- ttm_kmap_iter_tt_init(&_dst_iter.tt, bo->ttm) :
+ ttm_kmap_iter_tt_init(&_dst_iter.tt, dst_ttm) :
ttm_kmap_iter_iomap_init(&_dst_iter.io, &dst_reg->iomap,
dst_st, dst_reg->region.start);
@@ -558,7 +562,7 @@ static int i915_ttm_move(struct ttm_buffer_object *bo, bool evict,
clear = !cpu_maps_iomem(bo->resource) && (!ttm || !ttm_tt_is_populated(ttm));
if (!(clear && ttm && !(ttm->page_flags & TTM_PAGE_FLAG_ZERO_ALLOC)))
- __i915_ttm_move(bo, clear, dst_mem, dst_st);
+ __i915_ttm_move(bo, clear, dst_mem, bo->ttm, dst_st, true);
ttm_bo_move_sync_cleanup(bo, dst_mem);
i915_ttm_adjust_domains_after_move(obj);
@@ -973,3 +977,50 @@ i915_gem_ttm_system_setup(struct drm_i915_private *i915,
intel_memory_region_set_name(mr, "system-ttm");
return mr;
}
+
+/**
+ * i915_gem_obj_copy_ttm - Copy the contents of one ttm-based gem object to
+ * another
+ * @dst: The destination object
+ * @src: The source object
+ * @allow_accel: Allow using the blitter. Otherwise TTM memcpy is used.
+ * @intr: Whether to perform waits interruptible:
+ *
+ * Note: The caller is responsible for assuring that the underlying
+ * TTM objects are populated if needed and locked.
+ *
+ * Return: Zero on success. Negative error code on error. If @intr == true,
+ * then it may return -ERESTARTSYS or -EINTR.
+ */
+int i915_gem_obj_copy_ttm(struct drm_i915_gem_object *dst,
+ struct drm_i915_gem_object *src,
+ bool allow_accel, bool intr)
+{
+ struct ttm_buffer_object *dst_bo = i915_gem_to_ttm(dst);
+ struct ttm_buffer_object *src_bo = i915_gem_to_ttm(src);
+ struct ttm_operation_ctx ctx = {
+ .interruptible = intr,
+ };
+ struct sg_table *dst_st;
+ int ret;
+
+ assert_object_held(dst);
+ assert_object_held(src);
+
+ /*
+ * Sync for now. This will change with async moves.
+ */
+ ret = ttm_bo_wait_ctx(dst_bo, &ctx);
+ if (!ret)
+ ret = ttm_bo_wait_ctx(src_bo, &ctx);
+ if (ret)
+ return ret;
+
+ dst_st = gpu_binds_iomem(dst_bo->resource) ?
+ dst->ttm.cached_io_st : i915_ttm_tt_get_st(dst_bo->ttm);
+
+ __i915_ttm_move(src_bo, false, dst_bo->resource, dst_bo->ttm,
+ dst_st, allow_accel);
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.h b/drivers/gpu/drm/i915/gem/i915_gem_ttm.h
index 40927f67b6d9..34ac78d47b0d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.h
@@ -46,4 +46,8 @@ int __i915_gem_ttm_object_init(struct intel_memory_region *mem,
resource_size_t size,
resource_size_t page_size,
unsigned int flags);
+
+int i915_gem_obj_copy_ttm(struct drm_i915_gem_object *dst,
+ struct drm_i915_gem_object *src,
+ bool allow_accel, bool intr);
#endif
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [Intel-gfx] [PATCH v6 1/9] drm/i915/ttm: Implement a function to copy the contents of two TTM-based objects
@ 2021-09-22 6:25 ` Thomas Hellström
0 siblings, 0 replies; 39+ messages in thread
From: Thomas Hellström @ 2021-09-22 6:25 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: maarten.lankhorst, matthew.auld, Thomas Hellström
When backing up or restoring contents of pinned objects at suspend /
resume time we need to allocate a new object as the backup. Add a function
to facilitate copies between the two. Some data needs to be copied before
the migration context is ready for operation, so make sure we can
disable accelerated copies.
v2:
- Fix a missing return value check (Matthew Auld)
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 69 +++++++++++++++++++++----
drivers/gpu/drm/i915/gem/i915_gem_ttm.h | 4 ++
2 files changed, 64 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 2f672f06b169..22d59510d0c3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -428,6 +428,7 @@ i915_ttm_resource_get_st(struct drm_i915_gem_object *obj,
static int i915_ttm_accel_move(struct ttm_buffer_object *bo,
bool clear,
struct ttm_resource *dst_mem,
+ struct ttm_tt *dst_ttm,
struct sg_table *dst_st)
{
struct drm_i915_private *i915 = container_of(bo->bdev, typeof(*i915),
@@ -437,14 +438,14 @@ static int i915_ttm_accel_move(struct ttm_buffer_object *bo,
struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo);
struct sg_table *src_st;
struct i915_request *rq;
- struct ttm_tt *ttm = bo->ttm;
+ struct ttm_tt *src_ttm = bo->ttm;
enum i915_cache_level src_level, dst_level;
int ret;
if (!i915->gt.migrate.context)
return -EINVAL;
- dst_level = i915_ttm_cache_level(i915, dst_mem, ttm);
+ dst_level = i915_ttm_cache_level(i915, dst_mem, dst_ttm);
if (clear) {
if (bo->type == ttm_bo_type_kernel)
return -EINVAL;
@@ -461,10 +462,10 @@ static int i915_ttm_accel_move(struct ttm_buffer_object *bo,
}
intel_engine_pm_put(i915->gt.migrate.context->engine);
} else {
- src_st = src_man->use_tt ? i915_ttm_tt_get_st(ttm) :
+ src_st = src_man->use_tt ? i915_ttm_tt_get_st(src_ttm) :
obj->ttm.cached_io_st;
- src_level = i915_ttm_cache_level(i915, bo->resource, ttm);
+ src_level = i915_ttm_cache_level(i915, bo->resource, src_ttm);
intel_engine_pm_get(i915->gt.migrate.context->engine);
ret = intel_context_migrate_copy(i915->gt.migrate.context,
NULL, src_st->sgl, src_level,
@@ -484,11 +485,14 @@ static int i915_ttm_accel_move(struct ttm_buffer_object *bo,
static void __i915_ttm_move(struct ttm_buffer_object *bo, bool clear,
struct ttm_resource *dst_mem,
- struct sg_table *dst_st)
+ struct ttm_tt *dst_ttm,
+ struct sg_table *dst_st,
+ bool allow_accel)
{
- int ret;
+ int ret = -EINVAL;
- ret = i915_ttm_accel_move(bo, clear, dst_mem, dst_st);
+ if (allow_accel)
+ ret = i915_ttm_accel_move(bo, clear, dst_mem, dst_ttm, dst_st);
if (ret) {
struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo);
struct intel_memory_region *dst_reg, *src_reg;
@@ -503,7 +507,7 @@ static void __i915_ttm_move(struct ttm_buffer_object *bo, bool clear,
GEM_BUG_ON(!dst_reg || !src_reg);
dst_iter = !cpu_maps_iomem(dst_mem) ?
- ttm_kmap_iter_tt_init(&_dst_iter.tt, bo->ttm) :
+ ttm_kmap_iter_tt_init(&_dst_iter.tt, dst_ttm) :
ttm_kmap_iter_iomap_init(&_dst_iter.io, &dst_reg->iomap,
dst_st, dst_reg->region.start);
@@ -558,7 +562,7 @@ static int i915_ttm_move(struct ttm_buffer_object *bo, bool evict,
clear = !cpu_maps_iomem(bo->resource) && (!ttm || !ttm_tt_is_populated(ttm));
if (!(clear && ttm && !(ttm->page_flags & TTM_PAGE_FLAG_ZERO_ALLOC)))
- __i915_ttm_move(bo, clear, dst_mem, dst_st);
+ __i915_ttm_move(bo, clear, dst_mem, bo->ttm, dst_st, true);
ttm_bo_move_sync_cleanup(bo, dst_mem);
i915_ttm_adjust_domains_after_move(obj);
@@ -973,3 +977,50 @@ i915_gem_ttm_system_setup(struct drm_i915_private *i915,
intel_memory_region_set_name(mr, "system-ttm");
return mr;
}
+
+/**
+ * i915_gem_obj_copy_ttm - Copy the contents of one ttm-based gem object to
+ * another
+ * @dst: The destination object
+ * @src: The source object
+ * @allow_accel: Allow using the blitter. Otherwise TTM memcpy is used.
+ * @intr: Whether to perform waits interruptible:
+ *
+ * Note: The caller is responsible for assuring that the underlying
+ * TTM objects are populated if needed and locked.
+ *
+ * Return: Zero on success. Negative error code on error. If @intr == true,
+ * then it may return -ERESTARTSYS or -EINTR.
+ */
+int i915_gem_obj_copy_ttm(struct drm_i915_gem_object *dst,
+ struct drm_i915_gem_object *src,
+ bool allow_accel, bool intr)
+{
+ struct ttm_buffer_object *dst_bo = i915_gem_to_ttm(dst);
+ struct ttm_buffer_object *src_bo = i915_gem_to_ttm(src);
+ struct ttm_operation_ctx ctx = {
+ .interruptible = intr,
+ };
+ struct sg_table *dst_st;
+ int ret;
+
+ assert_object_held(dst);
+ assert_object_held(src);
+
+ /*
+ * Sync for now. This will change with async moves.
+ */
+ ret = ttm_bo_wait_ctx(dst_bo, &ctx);
+ if (!ret)
+ ret = ttm_bo_wait_ctx(src_bo, &ctx);
+ if (ret)
+ return ret;
+
+ dst_st = gpu_binds_iomem(dst_bo->resource) ?
+ dst->ttm.cached_io_st : i915_ttm_tt_get_st(dst_bo->ttm);
+
+ __i915_ttm_move(src_bo, false, dst_bo->resource, dst_bo->ttm,
+ dst_st, allow_accel);
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.h b/drivers/gpu/drm/i915/gem/i915_gem_ttm.h
index 40927f67b6d9..34ac78d47b0d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.h
@@ -46,4 +46,8 @@ int __i915_gem_ttm_object_init(struct intel_memory_region *mem,
resource_size_t size,
resource_size_t page_size,
unsigned int flags);
+
+int i915_gem_obj_copy_ttm(struct drm_i915_gem_object *dst,
+ struct drm_i915_gem_object *src,
+ bool allow_accel, bool intr);
#endif
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v6 2/9] drm/i915/gem: Implement a function to process all gem objects of a region
2021-09-22 6:25 ` [Intel-gfx] " Thomas Hellström
@ 2021-09-22 6:25 ` Thomas Hellström
-1 siblings, 0 replies; 39+ messages in thread
From: Thomas Hellström @ 2021-09-22 6:25 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: maarten.lankhorst, matthew.auld, Thomas Hellström
An upcoming common pattern is to traverse the region object list and
perform certain actions on all objects in a region. It's a little tricky
to get the list locking right, in particular since a gem object may
change region unless it's pinned or the object lock is held.
Define a function that does this for us and that takes an argument that
defines the action to be performed on each object.
v3:
- Improve structure documentation a bit (Matthew Auld)
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_region.c | 70 ++++++++++++++++++++++
drivers/gpu/drm/i915/gem/i915_gem_region.h | 37 ++++++++++++
2 files changed, 107 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c b/drivers/gpu/drm/i915/gem/i915_gem_region.c
index 1f557b2178ed..a016ccec36f3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
@@ -80,3 +80,73 @@ i915_gem_object_create_region(struct intel_memory_region *mem,
i915_gem_object_free(obj);
return ERR_PTR(err);
}
+
+/**
+ * i915_gem_process_region - Iterate over all objects of a region using ops
+ * to process and optionally skip objects
+ * @mr: The memory region
+ * @apply: ops and private data
+ *
+ * This function can be used to iterate over the regions object list,
+ * checking whether to skip objects, and, if not, lock the objects and
+ * process them using the supplied ops. Note that this function temporarily
+ * removes objects from the region list while iterating, so that if run
+ * concurrently with itself may not iterate over all objects.
+ *
+ * Return: 0 if successful, negative error code on failure.
+ */
+int i915_gem_process_region(struct intel_memory_region *mr,
+ struct i915_gem_apply_to_region *apply)
+{
+ const struct i915_gem_apply_to_region_ops *ops = apply->ops;
+ struct drm_i915_gem_object *obj;
+ struct list_head still_in_list;
+ int ret = 0;
+
+ /*
+ * In the future, a non-NULL apply->ww could mean the caller is
+ * already in a locking transaction and provides its own context.
+ */
+ GEM_WARN_ON(apply->ww);
+
+ INIT_LIST_HEAD(&still_in_list);
+ mutex_lock(&mr->objects.lock);
+ for (;;) {
+ struct i915_gem_ww_ctx ww;
+
+ obj = list_first_entry_or_null(&mr->objects.list, typeof(*obj),
+ mm.region_link);
+ if (!obj)
+ break;
+
+ list_move_tail(&obj->mm.region_link, &still_in_list);
+ if (!kref_get_unless_zero(&obj->base.refcount))
+ continue;
+
+ /*
+ * Note: Someone else might be migrating the object at this
+ * point. The object's region is not stable until we lock
+ * the object.
+ */
+ mutex_unlock(&mr->objects.lock);
+ apply->ww = &ww;
+ for_i915_gem_ww(&ww, ret, apply->interruptible) {
+ ret = i915_gem_object_lock(obj, apply->ww);
+ if (ret)
+ continue;
+
+ if (obj->mm.region == mr)
+ ret = ops->process_obj(apply, obj);
+ /* Implicit object unlock */
+ }
+
+ i915_gem_object_put(obj);
+ mutex_lock(&mr->objects.lock);
+ if (ret)
+ break;
+ }
+ list_splice_tail(&still_in_list, &mr->objects.list);
+ mutex_unlock(&mr->objects.lock);
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.h b/drivers/gpu/drm/i915/gem/i915_gem_region.h
index 1008e580a89a..fcaa12d657d4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.h
@@ -12,6 +12,41 @@ struct intel_memory_region;
struct drm_i915_gem_object;
struct sg_table;
+struct i915_gem_apply_to_region;
+
+/**
+ * struct i915_gem_apply_to_region_ops - ops to use when iterating over all
+ * region objects.
+ */
+struct i915_gem_apply_to_region_ops {
+ /**
+ * process_obj - Process the current object
+ * @apply: Embed this for private data.
+ * @obj: The current object.
+ *
+ * Note that if this function is part of a ww transaction, and
+ * if returns -EDEADLK for one of the objects, it may be
+ * rerun for that same object in the same pass.
+ */
+ int (*process_obj)(struct i915_gem_apply_to_region *apply,
+ struct drm_i915_gem_object *obj);
+};
+
+/**
+ * struct i915_gem_apply_to_region - Argument to the struct
+ * i915_gem_apply_to_region_ops functions.
+ * @ops: The ops for the operation.
+ * @ww: Locking context used for the transaction.
+ * @interruptible: Whether to perform object locking interruptible.
+ *
+ * This structure is intended to be embedded in a private struct if needed
+ */
+struct i915_gem_apply_to_region {
+ const struct i915_gem_apply_to_region_ops *ops;
+ struct i915_gem_ww_ctx *ww;
+ u32 interruptible:1;
+};
+
void i915_gem_object_init_memory_region(struct drm_i915_gem_object *obj,
struct intel_memory_region *mem);
void i915_gem_object_release_memory_region(struct drm_i915_gem_object *obj);
@@ -22,4 +57,6 @@ i915_gem_object_create_region(struct intel_memory_region *mem,
resource_size_t page_size,
unsigned int flags);
+int i915_gem_process_region(struct intel_memory_region *mr,
+ struct i915_gem_apply_to_region *apply);
#endif
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [Intel-gfx] [PATCH v6 2/9] drm/i915/gem: Implement a function to process all gem objects of a region
@ 2021-09-22 6:25 ` Thomas Hellström
0 siblings, 0 replies; 39+ messages in thread
From: Thomas Hellström @ 2021-09-22 6:25 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: maarten.lankhorst, matthew.auld, Thomas Hellström
An upcoming common pattern is to traverse the region object list and
perform certain actions on all objects in a region. It's a little tricky
to get the list locking right, in particular since a gem object may
change region unless it's pinned or the object lock is held.
Define a function that does this for us and that takes an argument that
defines the action to be performed on each object.
v3:
- Improve structure documentation a bit (Matthew Auld)
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_region.c | 70 ++++++++++++++++++++++
drivers/gpu/drm/i915/gem/i915_gem_region.h | 37 ++++++++++++
2 files changed, 107 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c b/drivers/gpu/drm/i915/gem/i915_gem_region.c
index 1f557b2178ed..a016ccec36f3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
@@ -80,3 +80,73 @@ i915_gem_object_create_region(struct intel_memory_region *mem,
i915_gem_object_free(obj);
return ERR_PTR(err);
}
+
+/**
+ * i915_gem_process_region - Iterate over all objects of a region using ops
+ * to process and optionally skip objects
+ * @mr: The memory region
+ * @apply: ops and private data
+ *
+ * This function can be used to iterate over the regions object list,
+ * checking whether to skip objects, and, if not, lock the objects and
+ * process them using the supplied ops. Note that this function temporarily
+ * removes objects from the region list while iterating, so that if run
+ * concurrently with itself may not iterate over all objects.
+ *
+ * Return: 0 if successful, negative error code on failure.
+ */
+int i915_gem_process_region(struct intel_memory_region *mr,
+ struct i915_gem_apply_to_region *apply)
+{
+ const struct i915_gem_apply_to_region_ops *ops = apply->ops;
+ struct drm_i915_gem_object *obj;
+ struct list_head still_in_list;
+ int ret = 0;
+
+ /*
+ * In the future, a non-NULL apply->ww could mean the caller is
+ * already in a locking transaction and provides its own context.
+ */
+ GEM_WARN_ON(apply->ww);
+
+ INIT_LIST_HEAD(&still_in_list);
+ mutex_lock(&mr->objects.lock);
+ for (;;) {
+ struct i915_gem_ww_ctx ww;
+
+ obj = list_first_entry_or_null(&mr->objects.list, typeof(*obj),
+ mm.region_link);
+ if (!obj)
+ break;
+
+ list_move_tail(&obj->mm.region_link, &still_in_list);
+ if (!kref_get_unless_zero(&obj->base.refcount))
+ continue;
+
+ /*
+ * Note: Someone else might be migrating the object at this
+ * point. The object's region is not stable until we lock
+ * the object.
+ */
+ mutex_unlock(&mr->objects.lock);
+ apply->ww = &ww;
+ for_i915_gem_ww(&ww, ret, apply->interruptible) {
+ ret = i915_gem_object_lock(obj, apply->ww);
+ if (ret)
+ continue;
+
+ if (obj->mm.region == mr)
+ ret = ops->process_obj(apply, obj);
+ /* Implicit object unlock */
+ }
+
+ i915_gem_object_put(obj);
+ mutex_lock(&mr->objects.lock);
+ if (ret)
+ break;
+ }
+ list_splice_tail(&still_in_list, &mr->objects.list);
+ mutex_unlock(&mr->objects.lock);
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.h b/drivers/gpu/drm/i915/gem/i915_gem_region.h
index 1008e580a89a..fcaa12d657d4 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.h
@@ -12,6 +12,41 @@ struct intel_memory_region;
struct drm_i915_gem_object;
struct sg_table;
+struct i915_gem_apply_to_region;
+
+/**
+ * struct i915_gem_apply_to_region_ops - ops to use when iterating over all
+ * region objects.
+ */
+struct i915_gem_apply_to_region_ops {
+ /**
+ * process_obj - Process the current object
+ * @apply: Embed this for private data.
+ * @obj: The current object.
+ *
+ * Note that if this function is part of a ww transaction, and
+ * if returns -EDEADLK for one of the objects, it may be
+ * rerun for that same object in the same pass.
+ */
+ int (*process_obj)(struct i915_gem_apply_to_region *apply,
+ struct drm_i915_gem_object *obj);
+};
+
+/**
+ * struct i915_gem_apply_to_region - Argument to the struct
+ * i915_gem_apply_to_region_ops functions.
+ * @ops: The ops for the operation.
+ * @ww: Locking context used for the transaction.
+ * @interruptible: Whether to perform object locking interruptible.
+ *
+ * This structure is intended to be embedded in a private struct if needed
+ */
+struct i915_gem_apply_to_region {
+ const struct i915_gem_apply_to_region_ops *ops;
+ struct i915_gem_ww_ctx *ww;
+ u32 interruptible:1;
+};
+
void i915_gem_object_init_memory_region(struct drm_i915_gem_object *obj,
struct intel_memory_region *mem);
void i915_gem_object_release_memory_region(struct drm_i915_gem_object *obj);
@@ -22,4 +57,6 @@ i915_gem_object_create_region(struct intel_memory_region *mem,
resource_size_t page_size,
unsigned int flags);
+int i915_gem_process_region(struct intel_memory_region *mr,
+ struct i915_gem_apply_to_region *apply);
#endif
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [Intel-gfx] [PATCH v6 3/9] drm/i915/gt: Increase suspend timeout
2021-09-22 6:25 ` [Intel-gfx] " Thomas Hellström
@ 2021-09-22 6:25 ` Thomas Hellström
-1 siblings, 0 replies; 39+ messages in thread
From: Thomas Hellström @ 2021-09-22 6:25 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: maarten.lankhorst, matthew.auld, Thomas Hellström
With GuC submission on DG1, the execution of the requests times out
for the gem_exec_suspend igt test case after executing around 800-900
of 1000 submitted requests.
Given the time we allow elsewhere for fences to signal (in the order of
seconds), increase the timeout before we mark the gt wedged and proceed.
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index dea8e2479897..f84f2bfe2de0 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -19,6 +19,8 @@
#include "intel_rps.h"
#include "intel_wakeref.h"
+#define I915_GT_SUSPEND_IDLE_TIMEOUT (HZ / 2)
+
static void user_forcewake(struct intel_gt *gt, bool suspend)
{
int count = atomic_read(>->user_wakeref);
@@ -279,7 +281,7 @@ static void wait_for_suspend(struct intel_gt *gt)
if (!intel_gt_pm_is_awake(gt))
return;
- if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME) {
+ if (intel_gt_wait_for_idle(gt, I915_GT_SUSPEND_IDLE_TIMEOUT) == -ETIME) {
/*
* Forcibly cancel outstanding work and leave
* the gpu quiet.
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [PATCH v6 3/9] drm/i915/gt: Increase suspend timeout
@ 2021-09-22 6:25 ` Thomas Hellström
0 siblings, 0 replies; 39+ messages in thread
From: Thomas Hellström @ 2021-09-22 6:25 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: maarten.lankhorst, matthew.auld, Thomas Hellström
With GuC submission on DG1, the execution of the requests times out
for the gem_exec_suspend igt test case after executing around 800-900
of 1000 submitted requests.
Given the time we allow elsewhere for fences to signal (in the order of
seconds), increase the timeout before we mark the gt wedged and proceed.
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index dea8e2479897..f84f2bfe2de0 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -19,6 +19,8 @@
#include "intel_rps.h"
#include "intel_wakeref.h"
+#define I915_GT_SUSPEND_IDLE_TIMEOUT (HZ / 2)
+
static void user_forcewake(struct intel_gt *gt, bool suspend)
{
int count = atomic_read(>->user_wakeref);
@@ -279,7 +281,7 @@ static void wait_for_suspend(struct intel_gt *gt)
if (!intel_gt_pm_is_awake(gt))
return;
- if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME) {
+ if (intel_gt_wait_for_idle(gt, I915_GT_SUSPEND_IDLE_TIMEOUT) == -ETIME) {
/*
* Forcibly cancel outstanding work and leave
* the gpu quiet.
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [PATCH v6 3/9] drm/i915/gt: Increase suspend timeout
2021-09-22 6:25 ` Thomas Hellström
@ 2021-09-23 9:18 ` Matthew Auld
-1 siblings, 0 replies; 39+ messages in thread
From: Matthew Auld @ 2021-09-23 9:18 UTC (permalink / raw)
To: Thomas Hellström, intel-gfx, dri-devel; +Cc: maarten.lankhorst
On 22/09/2021 07:25, Thomas Hellström wrote:
> With GuC submission on DG1, the execution of the requests times out
> for the gem_exec_suspend igt test case after executing around 800-900
> of 1000 submitted requests.
>
> Given the time we allow elsewhere for fences to signal (in the order of
> seconds), increase the timeout before we mark the gt wedged and proceed.
>
> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Acked-by: Matthew Auld <matthew.auld@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> index dea8e2479897..f84f2bfe2de0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> @@ -19,6 +19,8 @@
> #include "intel_rps.h"
> #include "intel_wakeref.h"
>
> +#define I915_GT_SUSPEND_IDLE_TIMEOUT (HZ / 2)
> +
> static void user_forcewake(struct intel_gt *gt, bool suspend)
> {
> int count = atomic_read(>->user_wakeref);
> @@ -279,7 +281,7 @@ static void wait_for_suspend(struct intel_gt *gt)
> if (!intel_gt_pm_is_awake(gt))
> return;
>
> - if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME) {
> + if (intel_gt_wait_for_idle(gt, I915_GT_SUSPEND_IDLE_TIMEOUT) == -ETIME) {
> /*
> * Forcibly cancel outstanding work and leave
> * the gpu quiet.
>
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [Intel-gfx] [PATCH v6 3/9] drm/i915/gt: Increase suspend timeout
@ 2021-09-23 9:18 ` Matthew Auld
0 siblings, 0 replies; 39+ messages in thread
From: Matthew Auld @ 2021-09-23 9:18 UTC (permalink / raw)
To: Thomas Hellström, intel-gfx, dri-devel; +Cc: maarten.lankhorst
On 22/09/2021 07:25, Thomas Hellström wrote:
> With GuC submission on DG1, the execution of the requests times out
> for the gem_exec_suspend igt test case after executing around 800-900
> of 1000 submitted requests.
>
> Given the time we allow elsewhere for fences to signal (in the order of
> seconds), increase the timeout before we mark the gt wedged and proceed.
>
> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Acked-by: Matthew Auld <matthew.auld@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> index dea8e2479897..f84f2bfe2de0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> @@ -19,6 +19,8 @@
> #include "intel_rps.h"
> #include "intel_wakeref.h"
>
> +#define I915_GT_SUSPEND_IDLE_TIMEOUT (HZ / 2)
> +
> static void user_forcewake(struct intel_gt *gt, bool suspend)
> {
> int count = atomic_read(>->user_wakeref);
> @@ -279,7 +281,7 @@ static void wait_for_suspend(struct intel_gt *gt)
> if (!intel_gt_pm_is_awake(gt))
> return;
>
> - if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME) {
> + if (intel_gt_wait_for_idle(gt, I915_GT_SUSPEND_IDLE_TIMEOUT) == -ETIME) {
> /*
> * Forcibly cancel outstanding work and leave
> * the gpu quiet.
>
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Intel-gfx] [PATCH v6 3/9] drm/i915/gt: Increase suspend timeout
2021-09-22 6:25 ` Thomas Hellström
(?)
(?)
@ 2021-09-23 10:13 ` Tvrtko Ursulin
2021-09-23 11:47 ` Thomas Hellström
-1 siblings, 1 reply; 39+ messages in thread
From: Tvrtko Ursulin @ 2021-09-23 10:13 UTC (permalink / raw)
To: Thomas Hellström, intel-gfx, dri-devel
Cc: maarten.lankhorst, matthew.auld, Matthew Brost, John Harrison
On 22/09/2021 07:25, Thomas Hellström wrote:
> With GuC submission on DG1, the execution of the requests times out
> for the gem_exec_suspend igt test case after executing around 800-900
> of 1000 submitted requests.
>
> Given the time we allow elsewhere for fences to signal (in the order of
> seconds), increase the timeout before we mark the gt wedged and proceed.
I suspect it is not about requests not retiring in time but about the
intel_guc_wait_for_idle part of intel_gt_wait_for_idle. Although I don't
know which G2H message is the code waiting for at suspend time so
perhaps something to run past the GuC experts.
Anyway, if that turns out to be correct then perhaps it would be better
to split the two timeouts (like if required GuC timeout is perhaps
fundamentally independent) so it's clear who needs how much time. Adding
Matt and John to comment.
To be clear, as timeout is AFAIK an arbitrary value, I don't have
fundamental objections here. Just think it would be good to have
accurate story in the commit message.
Regards,
Tvrtko
>
> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> index dea8e2479897..f84f2bfe2de0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
> @@ -19,6 +19,8 @@
> #include "intel_rps.h"
> #include "intel_wakeref.h"
>
> +#define I915_GT_SUSPEND_IDLE_TIMEOUT (HZ / 2)
> +
> static void user_forcewake(struct intel_gt *gt, bool suspend)
> {
> int count = atomic_read(>->user_wakeref);
> @@ -279,7 +281,7 @@ static void wait_for_suspend(struct intel_gt *gt)
> if (!intel_gt_pm_is_awake(gt))
> return;
>
> - if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) == -ETIME) {
> + if (intel_gt_wait_for_idle(gt, I915_GT_SUSPEND_IDLE_TIMEOUT) == -ETIME) {
> /*
> * Forcibly cancel outstanding work and leave
> * the gpu quiet.
>
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [Intel-gfx] [PATCH v6 3/9] drm/i915/gt: Increase suspend timeout
2021-09-23 10:13 ` Tvrtko Ursulin
@ 2021-09-23 11:47 ` Thomas Hellström
2021-09-23 12:59 ` Tvrtko Ursulin
0 siblings, 1 reply; 39+ messages in thread
From: Thomas Hellström @ 2021-09-23 11:47 UTC (permalink / raw)
To: Tvrtko Ursulin, intel-gfx, dri-devel
Cc: maarten.lankhorst, matthew.auld, Matthew Brost, John Harrison
Hi, Tvrtko,
On 9/23/21 12:13 PM, Tvrtko Ursulin wrote:
>
> On 22/09/2021 07:25, Thomas Hellström wrote:
>> With GuC submission on DG1, the execution of the requests times out
>> for the gem_exec_suspend igt test case after executing around 800-900
>> of 1000 submitted requests.
>>
>> Given the time we allow elsewhere for fences to signal (in the order of
>> seconds), increase the timeout before we mark the gt wedged and proceed.
>
> I suspect it is not about requests not retiring in time but about the
> intel_guc_wait_for_idle part of intel_gt_wait_for_idle. Although I
> don't know which G2H message is the code waiting for at suspend time
> so perhaps something to run past the GuC experts.
So what's happening here is that the tests submits 1000 requests, each
writing a value to an object, and then that object content is checked
after resume. With GuC it turns out that only 800-900 or so values are
actually written before we time out, and the test (basic-S3) fails, but
not on every run.
This is a bit interesting in itself, because I never saw the hang-S3
test fail, which from what I can tell basically is an identical test but
with a spinner submitted after the 1000th request. Could be that the
suspend backup code ends up waiting for something before we end up in
intel_gt_wait_for_idle, giving more requests time to execute.
>
> Anyway, if that turns out to be correct then perhaps it would be
> better to split the two timeouts (like if required GuC timeout is
> perhaps fundamentally independent) so it's clear who needs how much
> time. Adding Matt and John to comment.
You mean we have separate timeouts depending on whether we're using GuC
or execlists submission?
>
> To be clear, as timeout is AFAIK an arbitrary value, I don't have
> fundamental objections here. Just think it would be good to have
> accurate story in the commit message.
Ok. yes. I wonder whether we actually should increase this timeout even
more since now the watchdog times out after 10+ seconds? I guess those
long-running requests could be executing also at suspend time.
/Thomas
>
> Regards,
>
> Tvrtko
>
>>
>> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
>> ---
>> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 +++-
>> 1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
>> b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
>> index dea8e2479897..f84f2bfe2de0 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
>> @@ -19,6 +19,8 @@
>> #include "intel_rps.h"
>> #include "intel_wakeref.h"
>> +#define I915_GT_SUSPEND_IDLE_TIMEOUT (HZ / 2)
>> +
>> static void user_forcewake(struct intel_gt *gt, bool suspend)
>> {
>> int count = atomic_read(>->user_wakeref);
>> @@ -279,7 +281,7 @@ static void wait_for_suspend(struct intel_gt *gt)
>> if (!intel_gt_pm_is_awake(gt))
>> return;
>> - if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) ==
>> -ETIME) {
>> + if (intel_gt_wait_for_idle(gt, I915_GT_SUSPEND_IDLE_TIMEOUT) ==
>> -ETIME) {
>> /*
>> * Forcibly cancel outstanding work and leave
>> * the gpu quiet.
>>
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [Intel-gfx] [PATCH v6 3/9] drm/i915/gt: Increase suspend timeout
2021-09-23 11:47 ` Thomas Hellström
@ 2021-09-23 12:59 ` Tvrtko Ursulin
2021-09-23 13:19 ` Thomas Hellström
0 siblings, 1 reply; 39+ messages in thread
From: Tvrtko Ursulin @ 2021-09-23 12:59 UTC (permalink / raw)
To: Thomas Hellström, intel-gfx, dri-devel
Cc: maarten.lankhorst, matthew.auld, Matthew Brost, John Harrison
On 23/09/2021 12:47, Thomas Hellström wrote:
> Hi, Tvrtko,
>
> On 9/23/21 12:13 PM, Tvrtko Ursulin wrote:
>>
>> On 22/09/2021 07:25, Thomas Hellström wrote:
>>> With GuC submission on DG1, the execution of the requests times out
>>> for the gem_exec_suspend igt test case after executing around 800-900
>>> of 1000 submitted requests.
>>>
>>> Given the time we allow elsewhere for fences to signal (in the order of
>>> seconds), increase the timeout before we mark the gt wedged and proceed.
>>
>> I suspect it is not about requests not retiring in time but about the
>> intel_guc_wait_for_idle part of intel_gt_wait_for_idle. Although I
>> don't know which G2H message is the code waiting for at suspend time
>> so perhaps something to run past the GuC experts.
>
> So what's happening here is that the tests submits 1000 requests, each
> writing a value to an object, and then that object content is checked
> after resume. With GuC it turns out that only 800-900 or so values are
> actually written before we time out, and the test (basic-S3) fails, but
> not on every run.
Yes and that did not make sense to me. It is a single context even so I
did not come up with an explanation why would GuC be slower.
Unless it somehow manages to not even update the ring tail in time and
requests are still only stuck in the software queue? Perhaps you can see
that from context tail and head when it happens.
> This is a bit interesting in itself, because I never saw the hang-S3
> test fail, which from what I can tell basically is an identical test but
> with a spinner submitted after the 1000th request. Could be that the
> suspend backup code ends up waiting for something before we end up in
> intel_gt_wait_for_idle, giving more requests time to execute.
No idea, I don't know the suspend paths that well. For instance before
looking at the code I thought we would preempt what's executing and not
wait for everything that has been submitted to finish. :)
>> Anyway, if that turns out to be correct then perhaps it would be
>> better to split the two timeouts (like if required GuC timeout is
>> perhaps fundamentally independent) so it's clear who needs how much
>> time. Adding Matt and John to comment.
>
> You mean we have separate timeouts depending on whether we're using GuC
> or execlists submission?
No, I don't know yet. First I think we need to figure out what exactly
is happening.
>> To be clear, as timeout is AFAIK an arbitrary value, I don't have
>> fundamental objections here. Just think it would be good to have
>> accurate story in the commit message.
>
> Ok. yes. I wonder whether we actually should increase this timeout even
> more since now the watchdog times out after 10+ seconds? I guess those
> long-running requests could be executing also at suspend time.
We probably should not just increase it hugely. Because watchdog is a
separate story since it applies to unsubmited and unready requests and
suspend can happen fine with those around I think.
Regards,
Tvrtko
> /Thomas
>
>
>
>
>
>>
>> Regards,
>>
>> Tvrtko
>>
>>>
>>> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
>>> ---
>>> drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 +++-
>>> 1 file changed, 3 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
>>> b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
>>> index dea8e2479897..f84f2bfe2de0 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
>>> @@ -19,6 +19,8 @@
>>> #include "intel_rps.h"
>>> #include "intel_wakeref.h"
>>> +#define I915_GT_SUSPEND_IDLE_TIMEOUT (HZ / 2)
>>> +
>>> static void user_forcewake(struct intel_gt *gt, bool suspend)
>>> {
>>> int count = atomic_read(>->user_wakeref);
>>> @@ -279,7 +281,7 @@ static void wait_for_suspend(struct intel_gt *gt)
>>> if (!intel_gt_pm_is_awake(gt))
>>> return;
>>> - if (intel_gt_wait_for_idle(gt, I915_GEM_IDLE_TIMEOUT) ==
>>> -ETIME) {
>>> + if (intel_gt_wait_for_idle(gt, I915_GT_SUSPEND_IDLE_TIMEOUT) ==
>>> -ETIME) {
>>> /*
>>> * Forcibly cancel outstanding work and leave
>>> * the gpu quiet.
>>>
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [Intel-gfx] [PATCH v6 3/9] drm/i915/gt: Increase suspend timeout
2021-09-23 12:59 ` Tvrtko Ursulin
@ 2021-09-23 13:19 ` Thomas Hellström
2021-09-23 14:33 ` Tvrtko Ursulin
0 siblings, 1 reply; 39+ messages in thread
From: Thomas Hellström @ 2021-09-23 13:19 UTC (permalink / raw)
To: Tvrtko Ursulin, intel-gfx, dri-devel
Cc: maarten.lankhorst, matthew.auld, Matthew Brost, John Harrison
On 9/23/21 2:59 PM, Tvrtko Ursulin wrote:
>
> On 23/09/2021 12:47, Thomas Hellström wrote:
>> Hi, Tvrtko,
>>
>> On 9/23/21 12:13 PM, Tvrtko Ursulin wrote:
>>>
>>> On 22/09/2021 07:25, Thomas Hellström wrote:
>>>> With GuC submission on DG1, the execution of the requests times out
>>>> for the gem_exec_suspend igt test case after executing around 800-900
>>>> of 1000 submitted requests.
>>>>
>>>> Given the time we allow elsewhere for fences to signal (in the
>>>> order of
>>>> seconds), increase the timeout before we mark the gt wedged and
>>>> proceed.
>>>
>>> I suspect it is not about requests not retiring in time but about
>>> the intel_guc_wait_for_idle part of intel_gt_wait_for_idle. Although
>>> I don't know which G2H message is the code waiting for at suspend
>>> time so perhaps something to run past the GuC experts.
>>
>> So what's happening here is that the tests submits 1000 requests,
>> each writing a value to an object, and then that object content is
>> checked after resume. With GuC it turns out that only 800-900 or so
>> values are actually written before we time out, and the test
>> (basic-S3) fails, but not on every run.
>
> Yes and that did not make sense to me. It is a single context even so
> I did not come up with an explanation why would GuC be slower.
>
> Unless it somehow manages to not even update the ring tail in time and
> requests are still only stuck in the software queue? Perhaps you can
> see that from context tail and head when it happens.
>
>> This is a bit interesting in itself, because I never saw the hang-S3
>> test fail, which from what I can tell basically is an identical test
>> but with a spinner submitted after the 1000th request. Could be that
>> the suspend backup code ends up waiting for something before we end
>> up in intel_gt_wait_for_idle, giving more requests time to execute.
>
> No idea, I don't know the suspend paths that well. For instance before
> looking at the code I thought we would preempt what's executing and
> not wait for everything that has been submitted to finish. :)
>
>>> Anyway, if that turns out to be correct then perhaps it would be
>>> better to split the two timeouts (like if required GuC timeout is
>>> perhaps fundamentally independent) so it's clear who needs how much
>>> time. Adding Matt and John to comment.
>>
>> You mean we have separate timeouts depending on whether we're using
>> GuC or execlists submission?
>
> No, I don't know yet. First I think we need to figure out what exactly
> is happening.
Well then TBH I will need to file a separate Jira about that. There
might be various things going on here like swiching between the migrate
context for eviction of unrelated LMEM buffers and the context used by
gem_exec_suspend. The gem_exec_suspend failures are blocking DG1 BAT so
it's pretty urgent to get this series merged. If you insist I can leave
this patch out for now, but rather I'd commit it as is and File a Jira
instead.
/Thomas
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Intel-gfx] [PATCH v6 3/9] drm/i915/gt: Increase suspend timeout
2021-09-23 13:19 ` Thomas Hellström
@ 2021-09-23 14:33 ` Tvrtko Ursulin
2021-09-23 15:43 ` Thomas Hellström
0 siblings, 1 reply; 39+ messages in thread
From: Tvrtko Ursulin @ 2021-09-23 14:33 UTC (permalink / raw)
To: Thomas Hellström, intel-gfx, dri-devel
Cc: maarten.lankhorst, matthew.auld, Matthew Brost, John Harrison
On 23/09/2021 14:19, Thomas Hellström wrote:
>
> On 9/23/21 2:59 PM, Tvrtko Ursulin wrote:
>>
>> On 23/09/2021 12:47, Thomas Hellström wrote:
>>> Hi, Tvrtko,
>>>
>>> On 9/23/21 12:13 PM, Tvrtko Ursulin wrote:
>>>>
>>>> On 22/09/2021 07:25, Thomas Hellström wrote:
>>>>> With GuC submission on DG1, the execution of the requests times out
>>>>> for the gem_exec_suspend igt test case after executing around 800-900
>>>>> of 1000 submitted requests.
>>>>>
>>>>> Given the time we allow elsewhere for fences to signal (in the
>>>>> order of
>>>>> seconds), increase the timeout before we mark the gt wedged and
>>>>> proceed.
>>>>
>>>> I suspect it is not about requests not retiring in time but about
>>>> the intel_guc_wait_for_idle part of intel_gt_wait_for_idle. Although
>>>> I don't know which G2H message is the code waiting for at suspend
>>>> time so perhaps something to run past the GuC experts.
>>>
>>> So what's happening here is that the tests submits 1000 requests,
>>> each writing a value to an object, and then that object content is
>>> checked after resume. With GuC it turns out that only 800-900 or so
>>> values are actually written before we time out, and the test
>>> (basic-S3) fails, but not on every run.
>>
>> Yes and that did not make sense to me. It is a single context even so
>> I did not come up with an explanation why would GuC be slower.
>>
>> Unless it somehow manages to not even update the ring tail in time and
>> requests are still only stuck in the software queue? Perhaps you can
>> see that from context tail and head when it happens.
>>
>>> This is a bit interesting in itself, because I never saw the hang-S3
>>> test fail, which from what I can tell basically is an identical test
>>> but with a spinner submitted after the 1000th request. Could be that
>>> the suspend backup code ends up waiting for something before we end
>>> up in intel_gt_wait_for_idle, giving more requests time to execute.
>>
>> No idea, I don't know the suspend paths that well. For instance before
>> looking at the code I thought we would preempt what's executing and
>> not wait for everything that has been submitted to finish. :)
>>
>>>> Anyway, if that turns out to be correct then perhaps it would be
>>>> better to split the two timeouts (like if required GuC timeout is
>>>> perhaps fundamentally independent) so it's clear who needs how much
>>>> time. Adding Matt and John to comment.
>>>
>>> You mean we have separate timeouts depending on whether we're using
>>> GuC or execlists submission?
>>
>> No, I don't know yet. First I think we need to figure out what exactly
>> is happening.
>
> Well then TBH I will need to file a separate Jira about that. There
> might be various things going on here like swiching between the migrate
> context for eviction of unrelated LMEM buffers and the context used by
> gem_exec_suspend. The gem_exec_suspend failures are blocking DG1 BAT so
> it's pretty urgent to get this series merged. If you insist I can leave
> this patch out for now, but rather I'd commit it as is and File a Jira
> instead.
I see now how you have i915_gem_suspend() in between two lmem_suspend()
calls in this series. So first call has the potential of creating a lot
of requests and that you think interferes? Sounds plausible but implies
GuC timeslicing is less efficient if I follow?
IMO it is okay to leave for follow up work but strictly speaking, unless
I am missing something, the approach of bumping the timeout does not
sound valid if the copying is done async.
Because the timeout is then mandated not only as function of GPU
activity (lets say user controlled), but also the amount of
unpinned/idle buffers which happen to be laying around (which is more
i915 controlled, or mixed at least).
So question is, with enough data to copy, any timeout could be too low
and then how long do we want to wait before failing suspend? Is this an
argument to have a separate timeout specifically addressing the suspend
path or not I am not sure. Perhaps there is no choice and simply wait
until buffers are swapped out otherwise nothing will work.
Regards,
Tvrtko
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Intel-gfx] [PATCH v6 3/9] drm/i915/gt: Increase suspend timeout
2021-09-23 14:33 ` Tvrtko Ursulin
@ 2021-09-23 15:43 ` Thomas Hellström
0 siblings, 0 replies; 39+ messages in thread
From: Thomas Hellström @ 2021-09-23 15:43 UTC (permalink / raw)
To: Tvrtko Ursulin, intel-gfx, dri-devel
Cc: maarten.lankhorst, matthew.auld, Matthew Brost, John Harrison
On 9/23/21 4:33 PM, Tvrtko Ursulin wrote:
>
> On 23/09/2021 14:19, Thomas Hellström wrote:
>>
>> On 9/23/21 2:59 PM, Tvrtko Ursulin wrote:
>>>
>>> On 23/09/2021 12:47, Thomas Hellström wrote:
>>>> Hi, Tvrtko,
>>>>
>>>> On 9/23/21 12:13 PM, Tvrtko Ursulin wrote:
>>>>>
>>>>> On 22/09/2021 07:25, Thomas Hellström wrote:
>>>>>> With GuC submission on DG1, the execution of the requests times out
>>>>>> for the gem_exec_suspend igt test case after executing around
>>>>>> 800-900
>>>>>> of 1000 submitted requests.
>>>>>>
>>>>>> Given the time we allow elsewhere for fences to signal (in the
>>>>>> order of
>>>>>> seconds), increase the timeout before we mark the gt wedged and
>>>>>> proceed.
>>>>>
>>>>> I suspect it is not about requests not retiring in time but about
>>>>> the intel_guc_wait_for_idle part of intel_gt_wait_for_idle.
>>>>> Although I don't know which G2H message is the code waiting for at
>>>>> suspend time so perhaps something to run past the GuC experts.
>>>>
>>>> So what's happening here is that the tests submits 1000 requests,
>>>> each writing a value to an object, and then that object content is
>>>> checked after resume. With GuC it turns out that only 800-900 or so
>>>> values are actually written before we time out, and the test
>>>> (basic-S3) fails, but not on every run.
>>>
>>> Yes and that did not make sense to me. It is a single context even
>>> so I did not come up with an explanation why would GuC be slower.
>>>
>>> Unless it somehow manages to not even update the ring tail in time
>>> and requests are still only stuck in the software queue? Perhaps you
>>> can see that from context tail and head when it happens.
>>>
>>>> This is a bit interesting in itself, because I never saw the
>>>> hang-S3 test fail, which from what I can tell basically is an
>>>> identical test but with a spinner submitted after the 1000th
>>>> request. Could be that the suspend backup code ends up waiting for
>>>> something before we end up in intel_gt_wait_for_idle, giving more
>>>> requests time to execute.
>>>
>>> No idea, I don't know the suspend paths that well. For instance
>>> before looking at the code I thought we would preempt what's
>>> executing and not wait for everything that has been submitted to
>>> finish. :)
>>>
>>>>> Anyway, if that turns out to be correct then perhaps it would be
>>>>> better to split the two timeouts (like if required GuC timeout is
>>>>> perhaps fundamentally independent) so it's clear who needs how
>>>>> much time. Adding Matt and John to comment.
>>>>
>>>> You mean we have separate timeouts depending on whether we're using
>>>> GuC or execlists submission?
>>>
>>> No, I don't know yet. First I think we need to figure out what
>>> exactly is happening.
>>
>> Well then TBH I will need to file a separate Jira about that. There
>> might be various things going on here like swiching between the
>> migrate context for eviction of unrelated LMEM buffers and the
>> context used by gem_exec_suspend. The gem_exec_suspend failures are
>> blocking DG1 BAT so it's pretty urgent to get this series merged. If
>> you insist I can leave this patch out for now, but rather I'd commit
>> it as is and File a Jira instead.
>
> I see now how you have i915_gem_suspend() in between two
> lmem_suspend() calls in this series. So first call has the potential
> of creating a lot of requests and that you think interferes? Sounds
> plausible but implies GuC timeslicing is less efficient if I follow?
Yes, I guess so. Not sure exactly what is not performing so well with
the GuC but some tests really take a big performance hit, like
gem_lmem_swapping and gem_exec_whisper, but those may trigger entirely
different situations than what we have here.
>
> IMO it is okay to leave for follow up work but strictly speaking,
> unless I am missing something, the approach of bumping the timeout
> does not sound valid if the copying is done async.
Not async ATM. In any case It will probably make sense to sync before we
start the GT timeout, so that remaining work can be done undisturbed by
the copying. That way copying will always succeed, but depending on how
much and what type of work user-space has queued up, it might be terminated.
>
> Because the timeout is then mandated not only as function of GPU
> activity (lets say user controlled), but also the amount of
> unpinned/idle buffers which happen to be laying around (which is more
> i915 controlled, or mixed at least).
>
> So question is, with enough data to copy, any timeout could be too low
> and then how long do we want to wait before failing suspend? Is this
> an argument to have a separate timeout specifically addressing the
> suspend path or not I am not sure. Perhaps there is no choice and
> simply wait until buffers are swapped out otherwise nothing will work.
>
> Regards,
>
> Tvrtko
Thanks,
Thomas.
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v6 4/9] drm/i915 Implement LMEM backup and restore for suspend / resume
2021-09-22 6:25 ` [Intel-gfx] " Thomas Hellström
@ 2021-09-22 6:25 ` Thomas Hellström
-1 siblings, 0 replies; 39+ messages in thread
From: Thomas Hellström @ 2021-09-22 6:25 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: maarten.lankhorst, matthew.auld, Thomas Hellström
Just evict unpinned objects to system. For pinned LMEM objects,
make a backup system object and blit the contents to that.
Backup is performed in three steps,
1: Opportunistically evict evictable objects using the gpu blitter.
2: After gt idle, evict evictable objects using the gpu blitter. This will
be modified in an upcoming patch to backup pinned objects that are not used
by the blitter itself.
3: Backup remaining pinned objects using memcpy.
Also move uC suspend to after 2) to make sure we have a functional GuC
during 2) if using GuC submission.
v2:
- Major refactor to make sure gem_exec_suspend@hang-SX subtests work, and
suspend / resume works with a slightly modified GuC submission enabling
patch series.
v3:
- Fix a potential use-after-free (Matthew Auld)
- Use i915_gem_object_create_shmem() instead of
i915_gem_object_create_region (Matthew Auld)
- Minor simplifications (Matthew Auld)
- Fix up kerneldoc for i195_ttm_restore_region().
- Final lmem_suspend() call moved to i915_gem_backup_suspend from
i915_gem_suspend_late, since the latter gets called at driver unload
and we don't unnecessarily want to run it at that time.
v4:
- Interface change of ttm- & lmem suspend / resume functions to use
flags rather than bools. (Matthew Auld)
- Completely drop the i915_gem_backup_suspend change (Matthew Auld)
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
.../gpu/drm/i915/gem/i915_gem_object_types.h | 1 +
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 87 ++++++++
drivers/gpu/drm/i915/gem/i915_gem_pm.h | 1 +
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 30 ++-
drivers/gpu/drm/i915/gem/i915_gem_ttm.h | 10 +
drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c | 202 ++++++++++++++++++
drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.h | 26 +++
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 +-
drivers/gpu/drm/i915/i915_drv.c | 4 +-
10 files changed, 353 insertions(+), 13 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 335a8c668848..5c8e022a7383 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -154,6 +154,7 @@ gem-y += \
gem/i915_gem_throttle.o \
gem/i915_gem_tiling.o \
gem/i915_gem_ttm.o \
+ gem/i915_gem_ttm_pm.o \
gem/i915_gem_userptr.o \
gem/i915_gem_wait.o \
gem/i915_gemfs.o
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 2471f36aaff3..734cc8e16481 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -534,6 +534,7 @@ struct drm_i915_gem_object {
struct {
struct sg_table *cached_io_st;
struct i915_gem_object_page_iter get_io_page;
+ struct drm_i915_gem_object *backup;
bool created:1;
} ttm;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
index 8b9d7d14c4bd..12b37b4c1192 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
@@ -5,6 +5,7 @@
*/
#include "gem/i915_gem_pm.h"
+#include "gem/i915_gem_ttm_pm.h"
#include "gt/intel_gt.h"
#include "gt/intel_gt_pm.h"
#include "gt/intel_gt_requests.h"
@@ -39,6 +40,84 @@ void i915_gem_suspend(struct drm_i915_private *i915)
i915_gem_drain_freed_objects(i915);
}
+static int lmem_restore(struct drm_i915_private *i915, u32 flags)
+{
+ struct intel_memory_region *mr;
+ int ret = 0, id;
+
+ for_each_memory_region(mr, i915, id) {
+ if (mr->type == INTEL_MEMORY_LOCAL) {
+ ret = i915_ttm_restore_region(mr, flags);
+ if (ret)
+ break;
+ }
+ }
+
+ return ret;
+}
+
+static int lmem_suspend(struct drm_i915_private *i915, u32 flags)
+{
+ struct intel_memory_region *mr;
+ int ret = 0, id;
+
+ for_each_memory_region(mr, i915, id) {
+ if (mr->type == INTEL_MEMORY_LOCAL) {
+ ret = i915_ttm_backup_region(mr, flags);
+ if (ret)
+ break;
+ }
+ }
+
+ return ret;
+}
+
+static void lmem_recover(struct drm_i915_private *i915)
+{
+ struct intel_memory_region *mr;
+ int id;
+
+ for_each_memory_region(mr, i915, id)
+ if (mr->type == INTEL_MEMORY_LOCAL)
+ i915_ttm_recover_region(mr);
+}
+
+int i915_gem_backup_suspend(struct drm_i915_private *i915)
+{
+ int ret;
+
+ /* Opportunistically try to evict unpinned objects */
+ ret = lmem_suspend(i915, I915_TTM_BACKUP_ALLOW_GPU);
+ if (ret)
+ goto out_recover;
+
+ i915_gem_suspend(i915);
+
+ /*
+ * More objects may have become unpinned as requests were
+ * retired. Now try to evict again. The gt may be wedged here
+ * in which case we automatically fall back to memcpy.
+ */
+ ret = lmem_suspend(i915, I915_TTM_BACKUP_ALLOW_GPU);
+ if (ret)
+ goto out_recover;
+
+ /*
+ * Remaining objects are backed up using memcpy once we've stopped
+ * using the migrate context.
+ */
+ ret = lmem_suspend(i915, I915_TTM_BACKUP_PINNED);
+ if (ret)
+ goto out_recover;
+
+ return 0;
+
+out_recover:
+ lmem_recover(i915);
+
+ return ret;
+}
+
void i915_gem_suspend_late(struct drm_i915_private *i915)
{
struct drm_i915_gem_object *obj;
@@ -128,12 +207,20 @@ int i915_gem_freeze_late(struct drm_i915_private *i915)
void i915_gem_resume(struct drm_i915_private *i915)
{
+ int ret;
+
GEM_TRACE("%s\n", dev_name(i915->drm.dev));
+ ret = lmem_restore(i915, 0);
+ GEM_WARN_ON(ret);
+
/*
* As we didn't flush the kernel context before suspend, we cannot
* guarantee that the context image is complete. So let's just reset
* it and start again.
*/
intel_gt_resume(&i915->gt);
+
+ ret = lmem_restore(i915, I915_TTM_BACKUP_ALLOW_GPU);
+ GEM_WARN_ON(ret);
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.h b/drivers/gpu/drm/i915/gem/i915_gem_pm.h
index c9a66630e92e..bedf1e95941a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.h
@@ -18,6 +18,7 @@ void i915_gem_idle_work_handler(struct work_struct *work);
void i915_gem_suspend(struct drm_i915_private *i915);
void i915_gem_suspend_late(struct drm_i915_private *i915);
+int i915_gem_backup_suspend(struct drm_i915_private *i915);
int i915_gem_freeze(struct drm_i915_private *i915);
int i915_gem_freeze_late(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 22d59510d0c3..b94497989995 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -10,18 +10,16 @@
#include "intel_memory_region.h"
#include "intel_region_ttm.h"
+#include "gem/i915_gem_mman.h"
#include "gem/i915_gem_object.h"
#include "gem/i915_gem_region.h"
#include "gem/i915_gem_ttm.h"
-#include "gem/i915_gem_mman.h"
+#include "gem/i915_gem_ttm_pm.h"
-#include "gt/intel_migrate.h"
-#include "gt/intel_engine_pm.h"
-#define I915_PL_LMEM0 TTM_PL_PRIV
-#define I915_PL_SYSTEM TTM_PL_SYSTEM
-#define I915_PL_STOLEN TTM_PL_VRAM
-#define I915_PL_GGTT TTM_PL_TT
+#include "gt/intel_engine_pm.h"
+#include "gt/intel_gt.h"
+#include "gt/intel_migrate.h"
#define I915_TTM_PRIO_PURGE 0
#define I915_TTM_PRIO_NO_PAGES 1
@@ -64,6 +62,20 @@ static struct ttm_placement i915_sys_placement = {
.busy_placement = &sys_placement_flags,
};
+/**
+ * i915_ttm_sys_placement - Return the struct ttm_placement to be
+ * used for an object in system memory.
+ *
+ * Rather than making the struct extern, use this
+ * function.
+ *
+ * Return: A pointer to a static variable for sys placement.
+ */
+struct ttm_placement *i915_ttm_sys_placement(void)
+{
+ return &i915_sys_placement;
+}
+
static int i915_ttm_err_to_gem(int err)
{
/* Fastpath */
@@ -442,7 +454,7 @@ static int i915_ttm_accel_move(struct ttm_buffer_object *bo,
enum i915_cache_level src_level, dst_level;
int ret;
- if (!i915->gt.migrate.context)
+ if (!i915->gt.migrate.context || intel_gt_is_wedged(&i915->gt))
return -EINVAL;
dst_level = i915_ttm_cache_level(i915, dst_mem, dst_ttm);
@@ -886,6 +898,8 @@ void i915_ttm_bo_destroy(struct ttm_buffer_object *bo)
{
struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo);
+ i915_ttm_backup_free(obj);
+
/* This releases all gem object bindings to the backend. */
__i915_gem_free_object(obj);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.h b/drivers/gpu/drm/i915/gem/i915_gem_ttm.h
index 34ac78d47b0d..0b7291dd897c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.h
@@ -50,4 +50,14 @@ int __i915_gem_ttm_object_init(struct intel_memory_region *mem,
int i915_gem_obj_copy_ttm(struct drm_i915_gem_object *dst,
struct drm_i915_gem_object *src,
bool allow_accel, bool intr);
+
+/* Internal I915 TTM declarations and definitions below. */
+
+#define I915_PL_LMEM0 TTM_PL_PRIV
+#define I915_PL_SYSTEM TTM_PL_SYSTEM
+#define I915_PL_STOLEN TTM_PL_VRAM
+#define I915_PL_GGTT TTM_PL_TT
+
+struct ttm_placement *i915_ttm_sys_placement(void);
+
#endif
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
new file mode 100644
index 000000000000..cb1c46724f70
--- /dev/null
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
@@ -0,0 +1,202 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include <drm/ttm/ttm_placement.h>
+#include <drm/ttm/ttm_tt.h>
+
+#include "i915_drv.h"
+#include "intel_memory_region.h"
+#include "intel_region_ttm.h"
+
+#include "gem/i915_gem_region.h"
+#include "gem/i915_gem_ttm.h"
+#include "gem/i915_gem_ttm_pm.h"
+
+/**
+ * i915_ttm_backup_free - Free any backup attached to this object
+ * @obj: The object whose backup is to be freed.
+ */
+void i915_ttm_backup_free(struct drm_i915_gem_object *obj)
+{
+ if (obj->ttm.backup) {
+ i915_gem_object_put(obj->ttm.backup);
+ obj->ttm.backup = NULL;
+ }
+}
+
+/**
+ * struct i915_gem_ttm_pm_apply - Apply-to-region subclass for restore
+ * @base: The i915_gem_apply_to_region we derive from.
+ * @allow_gpu: Whether using the gpu blitter is allowed.
+ * @backup_pinned: On backup, backup also pinned objects.
+ */
+struct i915_gem_ttm_pm_apply {
+ struct i915_gem_apply_to_region base;
+ bool allow_gpu : 1;
+ bool backup_pinned : 1;
+};
+
+static int i915_ttm_backup(struct i915_gem_apply_to_region *apply,
+ struct drm_i915_gem_object *obj)
+{
+ struct i915_gem_ttm_pm_apply *pm_apply =
+ container_of(apply, typeof(*pm_apply), base);
+ struct ttm_buffer_object *bo = i915_gem_to_ttm(obj);
+ struct ttm_buffer_object *backup_bo;
+ struct drm_i915_private *i915 =
+ container_of(bo->bdev, typeof(*i915), bdev);
+ struct drm_i915_gem_object *backup;
+ struct ttm_operation_ctx ctx = {};
+ int err = 0;
+
+ if (bo->resource->mem_type == I915_PL_SYSTEM || obj->ttm.backup)
+ return 0;
+
+ if (pm_apply->allow_gpu && i915_gem_object_evictable(obj))
+ return ttm_bo_validate(bo, i915_ttm_sys_placement(), &ctx);
+
+ if (!pm_apply->backup_pinned)
+ return 0;
+
+ backup = i915_gem_object_create_shmem(i915, obj->base.size);
+ if (IS_ERR(backup))
+ return PTR_ERR(backup);
+
+ err = i915_gem_object_lock(backup, apply->ww);
+ if (err)
+ goto out_no_lock;
+
+ backup_bo = i915_gem_to_ttm(backup);
+ err = ttm_tt_populate(backup_bo->bdev, backup_bo->ttm, &ctx);
+ if (err)
+ goto out_no_populate;
+
+ err = i915_gem_obj_copy_ttm(backup, obj, pm_apply->allow_gpu, false);
+ GEM_WARN_ON(err);
+
+ obj->ttm.backup = backup;
+ return 0;
+
+out_no_populate:
+ i915_gem_ww_unlock_single(backup);
+out_no_lock:
+ i915_gem_object_put(backup);
+
+ return err;
+}
+
+static int i915_ttm_recover(struct i915_gem_apply_to_region *apply,
+ struct drm_i915_gem_object *obj)
+{
+ i915_ttm_backup_free(obj);
+ return 0;
+}
+
+/**
+ * i915_ttm_recover_region - Free the backup of all objects of a region
+ * @mr: The memory region
+ *
+ * Checks all objects of a region if there is backup attached and if so
+ * frees that backup. Typically this is called to recover after a partially
+ * performed backup.
+ */
+void i915_ttm_recover_region(struct intel_memory_region *mr)
+{
+ static const struct i915_gem_apply_to_region_ops recover_ops = {
+ .process_obj = i915_ttm_recover,
+ };
+ struct i915_gem_apply_to_region apply = {.ops = &recover_ops};
+ int ret;
+
+ ret = i915_gem_process_region(mr, &apply);
+ GEM_WARN_ON(ret);
+}
+
+/**
+ * i915_ttm_backup_region - Back up all objects of a region to smem.
+ * @mr: The memory region
+ * @allow_gpu: Whether to allow the gpu blitter for this backup.
+ * @backup_pinned: Backup also pinned objects.
+ *
+ * Loops over all objects of a region and either evicts them if they are
+ * evictable or backs them up using a backup object if they are pinned.
+ *
+ * Return: Zero on success. Negative error code on error.
+ */
+int i915_ttm_backup_region(struct intel_memory_region *mr, u32 flags)
+{
+ static const struct i915_gem_apply_to_region_ops backup_ops = {
+ .process_obj = i915_ttm_backup,
+ };
+ struct i915_gem_ttm_pm_apply pm_apply = {
+ .base = {.ops = &backup_ops},
+ .allow_gpu = flags & I915_TTM_BACKUP_ALLOW_GPU,
+ .backup_pinned = flags & I915_TTM_BACKUP_PINNED,
+ };
+
+ return i915_gem_process_region(mr, &pm_apply.base);
+}
+
+static int i915_ttm_restore(struct i915_gem_apply_to_region *apply,
+ struct drm_i915_gem_object *obj)
+{
+ struct i915_gem_ttm_pm_apply *pm_apply =
+ container_of(apply, typeof(*pm_apply), base);
+ struct drm_i915_gem_object *backup = obj->ttm.backup;
+ struct ttm_buffer_object *backup_bo = i915_gem_to_ttm(backup);
+ struct ttm_operation_ctx ctx = {};
+ int err;
+
+ if (!backup)
+ return 0;
+
+ if (!pm_apply->allow_gpu && (obj->flags & I915_BO_ALLOC_USER))
+ return 0;
+
+ err = i915_gem_object_lock(backup, apply->ww);
+ if (err)
+ return err;
+
+ /* Content may have been swapped. */
+ err = ttm_tt_populate(backup_bo->bdev, backup_bo->ttm, &ctx);
+ if (!err) {
+ err = i915_gem_obj_copy_ttm(obj, backup, pm_apply->allow_gpu,
+ false);
+ GEM_WARN_ON(err);
+
+ obj->ttm.backup = NULL;
+ err = 0;
+ }
+
+ i915_gem_ww_unlock_single(backup);
+
+ if (!err)
+ i915_gem_object_put(backup);
+
+ return err;
+}
+
+/**
+ * i915_ttm_restore_region - Restore backed-up objects of a region from smem.
+ * @mr: The memory region
+ * @allow_gpu: Whether to allow the gpu blitter to recover.
+ *
+ * Loops over all objects of a region and if they are backed-up, restores
+ * them from smem.
+ *
+ * Return: Zero on success. Negative error code on error.
+ */
+int i915_ttm_restore_region(struct intel_memory_region *mr, u32 flags)
+{
+ static const struct i915_gem_apply_to_region_ops restore_ops = {
+ .process_obj = i915_ttm_restore,
+ };
+ struct i915_gem_ttm_pm_apply pm_apply = {
+ .base = {.ops = &restore_ops},
+ .allow_gpu = flags & I915_TTM_BACKUP_ALLOW_GPU,
+ };
+
+ return i915_gem_process_region(mr, &pm_apply.base);
+}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.h b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.h
new file mode 100644
index 000000000000..25ed67a31571
--- /dev/null
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#ifndef _I915_GEM_TTM_PM_H_
+#define _I915_GEM_TTM_PM_H_
+
+#include <linux/types.h>
+
+struct intel_memory_region;
+struct drm_i915_gem_object;
+
+#define I915_TTM_BACKUP_ALLOW_GPU BIT(0)
+#define I915_TTM_BACKUP_PINNED BIT(1)
+
+int i915_ttm_backup_region(struct intel_memory_region *mr, u32 flags);
+
+void i915_ttm_recover_region(struct intel_memory_region *mr);
+
+int i915_ttm_restore_region(struct intel_memory_region *mr, u32 flags);
+
+/* Internal I915 TTM functions below. */
+void i915_ttm_backup_free(struct drm_i915_gem_object *obj);
+
+#endif
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index f84f2bfe2de0..e9da36530b45 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -297,8 +297,6 @@ void intel_gt_suspend_prepare(struct intel_gt *gt)
{
user_forcewake(gt, true);
wait_for_suspend(gt);
-
- intel_uc_suspend(>->uc);
}
static suspend_state_t pm_suspend_target(void)
@@ -322,6 +320,8 @@ void intel_gt_suspend_late(struct intel_gt *gt)
GEM_BUG_ON(gt->awake);
+ intel_uc_suspend(>->uc);
+
/*
* On disabling the device, we want to turn off HW access to memory
* that we no longer own.
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 3cf61bead2f6..ed7b421cad44 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1094,9 +1094,7 @@ static int i915_drm_prepare(struct drm_device *dev)
* split out that work and pull it forward so that after point,
* the GPU is not woken again.
*/
- i915_gem_suspend(i915);
-
- return 0;
+ return i915_gem_backup_suspend(i915);
}
static int i915_drm_suspend(struct drm_device *dev)
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [Intel-gfx] [PATCH v6 4/9] drm/i915 Implement LMEM backup and restore for suspend / resume
@ 2021-09-22 6:25 ` Thomas Hellström
0 siblings, 0 replies; 39+ messages in thread
From: Thomas Hellström @ 2021-09-22 6:25 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: maarten.lankhorst, matthew.auld, Thomas Hellström
Just evict unpinned objects to system. For pinned LMEM objects,
make a backup system object and blit the contents to that.
Backup is performed in three steps,
1: Opportunistically evict evictable objects using the gpu blitter.
2: After gt idle, evict evictable objects using the gpu blitter. This will
be modified in an upcoming patch to backup pinned objects that are not used
by the blitter itself.
3: Backup remaining pinned objects using memcpy.
Also move uC suspend to after 2) to make sure we have a functional GuC
during 2) if using GuC submission.
v2:
- Major refactor to make sure gem_exec_suspend@hang-SX subtests work, and
suspend / resume works with a slightly modified GuC submission enabling
patch series.
v3:
- Fix a potential use-after-free (Matthew Auld)
- Use i915_gem_object_create_shmem() instead of
i915_gem_object_create_region (Matthew Auld)
- Minor simplifications (Matthew Auld)
- Fix up kerneldoc for i195_ttm_restore_region().
- Final lmem_suspend() call moved to i915_gem_backup_suspend from
i915_gem_suspend_late, since the latter gets called at driver unload
and we don't unnecessarily want to run it at that time.
v4:
- Interface change of ttm- & lmem suspend / resume functions to use
flags rather than bools. (Matthew Auld)
- Completely drop the i915_gem_backup_suspend change (Matthew Auld)
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
.../gpu/drm/i915/gem/i915_gem_object_types.h | 1 +
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 87 ++++++++
drivers/gpu/drm/i915/gem/i915_gem_pm.h | 1 +
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 30 ++-
drivers/gpu/drm/i915/gem/i915_gem_ttm.h | 10 +
drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c | 202 ++++++++++++++++++
drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.h | 26 +++
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 +-
drivers/gpu/drm/i915/i915_drv.c | 4 +-
10 files changed, 353 insertions(+), 13 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
create mode 100644 drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 335a8c668848..5c8e022a7383 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -154,6 +154,7 @@ gem-y += \
gem/i915_gem_throttle.o \
gem/i915_gem_tiling.o \
gem/i915_gem_ttm.o \
+ gem/i915_gem_ttm_pm.o \
gem/i915_gem_userptr.o \
gem/i915_gem_wait.o \
gem/i915_gemfs.o
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 2471f36aaff3..734cc8e16481 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -534,6 +534,7 @@ struct drm_i915_gem_object {
struct {
struct sg_table *cached_io_st;
struct i915_gem_object_page_iter get_io_page;
+ struct drm_i915_gem_object *backup;
bool created:1;
} ttm;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
index 8b9d7d14c4bd..12b37b4c1192 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
@@ -5,6 +5,7 @@
*/
#include "gem/i915_gem_pm.h"
+#include "gem/i915_gem_ttm_pm.h"
#include "gt/intel_gt.h"
#include "gt/intel_gt_pm.h"
#include "gt/intel_gt_requests.h"
@@ -39,6 +40,84 @@ void i915_gem_suspend(struct drm_i915_private *i915)
i915_gem_drain_freed_objects(i915);
}
+static int lmem_restore(struct drm_i915_private *i915, u32 flags)
+{
+ struct intel_memory_region *mr;
+ int ret = 0, id;
+
+ for_each_memory_region(mr, i915, id) {
+ if (mr->type == INTEL_MEMORY_LOCAL) {
+ ret = i915_ttm_restore_region(mr, flags);
+ if (ret)
+ break;
+ }
+ }
+
+ return ret;
+}
+
+static int lmem_suspend(struct drm_i915_private *i915, u32 flags)
+{
+ struct intel_memory_region *mr;
+ int ret = 0, id;
+
+ for_each_memory_region(mr, i915, id) {
+ if (mr->type == INTEL_MEMORY_LOCAL) {
+ ret = i915_ttm_backup_region(mr, flags);
+ if (ret)
+ break;
+ }
+ }
+
+ return ret;
+}
+
+static void lmem_recover(struct drm_i915_private *i915)
+{
+ struct intel_memory_region *mr;
+ int id;
+
+ for_each_memory_region(mr, i915, id)
+ if (mr->type == INTEL_MEMORY_LOCAL)
+ i915_ttm_recover_region(mr);
+}
+
+int i915_gem_backup_suspend(struct drm_i915_private *i915)
+{
+ int ret;
+
+ /* Opportunistically try to evict unpinned objects */
+ ret = lmem_suspend(i915, I915_TTM_BACKUP_ALLOW_GPU);
+ if (ret)
+ goto out_recover;
+
+ i915_gem_suspend(i915);
+
+ /*
+ * More objects may have become unpinned as requests were
+ * retired. Now try to evict again. The gt may be wedged here
+ * in which case we automatically fall back to memcpy.
+ */
+ ret = lmem_suspend(i915, I915_TTM_BACKUP_ALLOW_GPU);
+ if (ret)
+ goto out_recover;
+
+ /*
+ * Remaining objects are backed up using memcpy once we've stopped
+ * using the migrate context.
+ */
+ ret = lmem_suspend(i915, I915_TTM_BACKUP_PINNED);
+ if (ret)
+ goto out_recover;
+
+ return 0;
+
+out_recover:
+ lmem_recover(i915);
+
+ return ret;
+}
+
void i915_gem_suspend_late(struct drm_i915_private *i915)
{
struct drm_i915_gem_object *obj;
@@ -128,12 +207,20 @@ int i915_gem_freeze_late(struct drm_i915_private *i915)
void i915_gem_resume(struct drm_i915_private *i915)
{
+ int ret;
+
GEM_TRACE("%s\n", dev_name(i915->drm.dev));
+ ret = lmem_restore(i915, 0);
+ GEM_WARN_ON(ret);
+
/*
* As we didn't flush the kernel context before suspend, we cannot
* guarantee that the context image is complete. So let's just reset
* it and start again.
*/
intel_gt_resume(&i915->gt);
+
+ ret = lmem_restore(i915, I915_TTM_BACKUP_ALLOW_GPU);
+ GEM_WARN_ON(ret);
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.h b/drivers/gpu/drm/i915/gem/i915_gem_pm.h
index c9a66630e92e..bedf1e95941a 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.h
@@ -18,6 +18,7 @@ void i915_gem_idle_work_handler(struct work_struct *work);
void i915_gem_suspend(struct drm_i915_private *i915);
void i915_gem_suspend_late(struct drm_i915_private *i915);
+int i915_gem_backup_suspend(struct drm_i915_private *i915);
int i915_gem_freeze(struct drm_i915_private *i915);
int i915_gem_freeze_late(struct drm_i915_private *i915);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 22d59510d0c3..b94497989995 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -10,18 +10,16 @@
#include "intel_memory_region.h"
#include "intel_region_ttm.h"
+#include "gem/i915_gem_mman.h"
#include "gem/i915_gem_object.h"
#include "gem/i915_gem_region.h"
#include "gem/i915_gem_ttm.h"
-#include "gem/i915_gem_mman.h"
+#include "gem/i915_gem_ttm_pm.h"
-#include "gt/intel_migrate.h"
-#include "gt/intel_engine_pm.h"
-#define I915_PL_LMEM0 TTM_PL_PRIV
-#define I915_PL_SYSTEM TTM_PL_SYSTEM
-#define I915_PL_STOLEN TTM_PL_VRAM
-#define I915_PL_GGTT TTM_PL_TT
+#include "gt/intel_engine_pm.h"
+#include "gt/intel_gt.h"
+#include "gt/intel_migrate.h"
#define I915_TTM_PRIO_PURGE 0
#define I915_TTM_PRIO_NO_PAGES 1
@@ -64,6 +62,20 @@ static struct ttm_placement i915_sys_placement = {
.busy_placement = &sys_placement_flags,
};
+/**
+ * i915_ttm_sys_placement - Return the struct ttm_placement to be
+ * used for an object in system memory.
+ *
+ * Rather than making the struct extern, use this
+ * function.
+ *
+ * Return: A pointer to a static variable for sys placement.
+ */
+struct ttm_placement *i915_ttm_sys_placement(void)
+{
+ return &i915_sys_placement;
+}
+
static int i915_ttm_err_to_gem(int err)
{
/* Fastpath */
@@ -442,7 +454,7 @@ static int i915_ttm_accel_move(struct ttm_buffer_object *bo,
enum i915_cache_level src_level, dst_level;
int ret;
- if (!i915->gt.migrate.context)
+ if (!i915->gt.migrate.context || intel_gt_is_wedged(&i915->gt))
return -EINVAL;
dst_level = i915_ttm_cache_level(i915, dst_mem, dst_ttm);
@@ -886,6 +898,8 @@ void i915_ttm_bo_destroy(struct ttm_buffer_object *bo)
{
struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo);
+ i915_ttm_backup_free(obj);
+
/* This releases all gem object bindings to the backend. */
__i915_gem_free_object(obj);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.h b/drivers/gpu/drm/i915/gem/i915_gem_ttm.h
index 34ac78d47b0d..0b7291dd897c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.h
@@ -50,4 +50,14 @@ int __i915_gem_ttm_object_init(struct intel_memory_region *mem,
int i915_gem_obj_copy_ttm(struct drm_i915_gem_object *dst,
struct drm_i915_gem_object *src,
bool allow_accel, bool intr);
+
+/* Internal I915 TTM declarations and definitions below. */
+
+#define I915_PL_LMEM0 TTM_PL_PRIV
+#define I915_PL_SYSTEM TTM_PL_SYSTEM
+#define I915_PL_STOLEN TTM_PL_VRAM
+#define I915_PL_GGTT TTM_PL_TT
+
+struct ttm_placement *i915_ttm_sys_placement(void);
+
#endif
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
new file mode 100644
index 000000000000..cb1c46724f70
--- /dev/null
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
@@ -0,0 +1,202 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include <drm/ttm/ttm_placement.h>
+#include <drm/ttm/ttm_tt.h>
+
+#include "i915_drv.h"
+#include "intel_memory_region.h"
+#include "intel_region_ttm.h"
+
+#include "gem/i915_gem_region.h"
+#include "gem/i915_gem_ttm.h"
+#include "gem/i915_gem_ttm_pm.h"
+
+/**
+ * i915_ttm_backup_free - Free any backup attached to this object
+ * @obj: The object whose backup is to be freed.
+ */
+void i915_ttm_backup_free(struct drm_i915_gem_object *obj)
+{
+ if (obj->ttm.backup) {
+ i915_gem_object_put(obj->ttm.backup);
+ obj->ttm.backup = NULL;
+ }
+}
+
+/**
+ * struct i915_gem_ttm_pm_apply - Apply-to-region subclass for restore
+ * @base: The i915_gem_apply_to_region we derive from.
+ * @allow_gpu: Whether using the gpu blitter is allowed.
+ * @backup_pinned: On backup, backup also pinned objects.
+ */
+struct i915_gem_ttm_pm_apply {
+ struct i915_gem_apply_to_region base;
+ bool allow_gpu : 1;
+ bool backup_pinned : 1;
+};
+
+static int i915_ttm_backup(struct i915_gem_apply_to_region *apply,
+ struct drm_i915_gem_object *obj)
+{
+ struct i915_gem_ttm_pm_apply *pm_apply =
+ container_of(apply, typeof(*pm_apply), base);
+ struct ttm_buffer_object *bo = i915_gem_to_ttm(obj);
+ struct ttm_buffer_object *backup_bo;
+ struct drm_i915_private *i915 =
+ container_of(bo->bdev, typeof(*i915), bdev);
+ struct drm_i915_gem_object *backup;
+ struct ttm_operation_ctx ctx = {};
+ int err = 0;
+
+ if (bo->resource->mem_type == I915_PL_SYSTEM || obj->ttm.backup)
+ return 0;
+
+ if (pm_apply->allow_gpu && i915_gem_object_evictable(obj))
+ return ttm_bo_validate(bo, i915_ttm_sys_placement(), &ctx);
+
+ if (!pm_apply->backup_pinned)
+ return 0;
+
+ backup = i915_gem_object_create_shmem(i915, obj->base.size);
+ if (IS_ERR(backup))
+ return PTR_ERR(backup);
+
+ err = i915_gem_object_lock(backup, apply->ww);
+ if (err)
+ goto out_no_lock;
+
+ backup_bo = i915_gem_to_ttm(backup);
+ err = ttm_tt_populate(backup_bo->bdev, backup_bo->ttm, &ctx);
+ if (err)
+ goto out_no_populate;
+
+ err = i915_gem_obj_copy_ttm(backup, obj, pm_apply->allow_gpu, false);
+ GEM_WARN_ON(err);
+
+ obj->ttm.backup = backup;
+ return 0;
+
+out_no_populate:
+ i915_gem_ww_unlock_single(backup);
+out_no_lock:
+ i915_gem_object_put(backup);
+
+ return err;
+}
+
+static int i915_ttm_recover(struct i915_gem_apply_to_region *apply,
+ struct drm_i915_gem_object *obj)
+{
+ i915_ttm_backup_free(obj);
+ return 0;
+}
+
+/**
+ * i915_ttm_recover_region - Free the backup of all objects of a region
+ * @mr: The memory region
+ *
+ * Checks all objects of a region if there is backup attached and if so
+ * frees that backup. Typically this is called to recover after a partially
+ * performed backup.
+ */
+void i915_ttm_recover_region(struct intel_memory_region *mr)
+{
+ static const struct i915_gem_apply_to_region_ops recover_ops = {
+ .process_obj = i915_ttm_recover,
+ };
+ struct i915_gem_apply_to_region apply = {.ops = &recover_ops};
+ int ret;
+
+ ret = i915_gem_process_region(mr, &apply);
+ GEM_WARN_ON(ret);
+}
+
+/**
+ * i915_ttm_backup_region - Back up all objects of a region to smem.
+ * @mr: The memory region
+ * @allow_gpu: Whether to allow the gpu blitter for this backup.
+ * @backup_pinned: Backup also pinned objects.
+ *
+ * Loops over all objects of a region and either evicts them if they are
+ * evictable or backs them up using a backup object if they are pinned.
+ *
+ * Return: Zero on success. Negative error code on error.
+ */
+int i915_ttm_backup_region(struct intel_memory_region *mr, u32 flags)
+{
+ static const struct i915_gem_apply_to_region_ops backup_ops = {
+ .process_obj = i915_ttm_backup,
+ };
+ struct i915_gem_ttm_pm_apply pm_apply = {
+ .base = {.ops = &backup_ops},
+ .allow_gpu = flags & I915_TTM_BACKUP_ALLOW_GPU,
+ .backup_pinned = flags & I915_TTM_BACKUP_PINNED,
+ };
+
+ return i915_gem_process_region(mr, &pm_apply.base);
+}
+
+static int i915_ttm_restore(struct i915_gem_apply_to_region *apply,
+ struct drm_i915_gem_object *obj)
+{
+ struct i915_gem_ttm_pm_apply *pm_apply =
+ container_of(apply, typeof(*pm_apply), base);
+ struct drm_i915_gem_object *backup = obj->ttm.backup;
+ struct ttm_buffer_object *backup_bo = i915_gem_to_ttm(backup);
+ struct ttm_operation_ctx ctx = {};
+ int err;
+
+ if (!backup)
+ return 0;
+
+ if (!pm_apply->allow_gpu && (obj->flags & I915_BO_ALLOC_USER))
+ return 0;
+
+ err = i915_gem_object_lock(backup, apply->ww);
+ if (err)
+ return err;
+
+ /* Content may have been swapped. */
+ err = ttm_tt_populate(backup_bo->bdev, backup_bo->ttm, &ctx);
+ if (!err) {
+ err = i915_gem_obj_copy_ttm(obj, backup, pm_apply->allow_gpu,
+ false);
+ GEM_WARN_ON(err);
+
+ obj->ttm.backup = NULL;
+ err = 0;
+ }
+
+ i915_gem_ww_unlock_single(backup);
+
+ if (!err)
+ i915_gem_object_put(backup);
+
+ return err;
+}
+
+/**
+ * i915_ttm_restore_region - Restore backed-up objects of a region from smem.
+ * @mr: The memory region
+ * @allow_gpu: Whether to allow the gpu blitter to recover.
+ *
+ * Loops over all objects of a region and if they are backed-up, restores
+ * them from smem.
+ *
+ * Return: Zero on success. Negative error code on error.
+ */
+int i915_ttm_restore_region(struct intel_memory_region *mr, u32 flags)
+{
+ static const struct i915_gem_apply_to_region_ops restore_ops = {
+ .process_obj = i915_ttm_restore,
+ };
+ struct i915_gem_ttm_pm_apply pm_apply = {
+ .base = {.ops = &restore_ops},
+ .allow_gpu = flags & I915_TTM_BACKUP_ALLOW_GPU,
+ };
+
+ return i915_gem_process_region(mr, &pm_apply.base);
+}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.h b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.h
new file mode 100644
index 000000000000..25ed67a31571
--- /dev/null
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#ifndef _I915_GEM_TTM_PM_H_
+#define _I915_GEM_TTM_PM_H_
+
+#include <linux/types.h>
+
+struct intel_memory_region;
+struct drm_i915_gem_object;
+
+#define I915_TTM_BACKUP_ALLOW_GPU BIT(0)
+#define I915_TTM_BACKUP_PINNED BIT(1)
+
+int i915_ttm_backup_region(struct intel_memory_region *mr, u32 flags);
+
+void i915_ttm_recover_region(struct intel_memory_region *mr);
+
+int i915_ttm_restore_region(struct intel_memory_region *mr, u32 flags);
+
+/* Internal I915 TTM functions below. */
+void i915_ttm_backup_free(struct drm_i915_gem_object *obj);
+
+#endif
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index f84f2bfe2de0..e9da36530b45 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -297,8 +297,6 @@ void intel_gt_suspend_prepare(struct intel_gt *gt)
{
user_forcewake(gt, true);
wait_for_suspend(gt);
-
- intel_uc_suspend(>->uc);
}
static suspend_state_t pm_suspend_target(void)
@@ -322,6 +320,8 @@ void intel_gt_suspend_late(struct intel_gt *gt)
GEM_BUG_ON(gt->awake);
+ intel_uc_suspend(>->uc);
+
/*
* On disabling the device, we want to turn off HW access to memory
* that we no longer own.
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 3cf61bead2f6..ed7b421cad44 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1094,9 +1094,7 @@ static int i915_drm_prepare(struct drm_device *dev)
* split out that work and pull it forward so that after point,
* the GPU is not woken again.
*/
- i915_gem_suspend(i915);
-
- return 0;
+ return i915_gem_backup_suspend(i915);
}
static int i915_drm_suspend(struct drm_device *dev)
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v6 5/9] drm/i915/gt: Register the migrate contexts with their engines
2021-09-22 6:25 ` [Intel-gfx] " Thomas Hellström
@ 2021-09-22 6:25 ` Thomas Hellström
-1 siblings, 0 replies; 39+ messages in thread
From: Thomas Hellström @ 2021-09-22 6:25 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: maarten.lankhorst, matthew.auld, Tvrtko Ursulin, Brost Matthew,
Chris Wilson, Thomas Hellström
Pinned contexts, like the migrate contexts need reset after resume
since their context image may have been lost. Also the GuC needs to
register pinned contexts.
Add a list to struct intel_engine_cs where we add all pinned contexts on
creation, and traverse that list at resume time to reset the pinned
contexts.
This fixes the kms_pipe_crc_basic@suspend-read-crc-pipe-a selftest for now,
but proper LMEM backup / restore is needed for full suspend functionality.
However, note that even with full LMEM backup / restore it may be
desirable to keep the reset since backing up the migrate context images
must happen using memcpy() after the migrate context has become inactive,
and for performance- and other reasons we want to avoid memcpy() from
LMEM.
Also traverse the list at guc_init_lrc_mapping() calling
guc_kernel_context_pin() for the pinned contexts, like is already done
for the kernel context.
v2:
- Don't reset the contexts on each __engine_unpark() but rather at
resume time (Chris Wilson).
v3:
- Reset contexts in the engine sanitize callback. (Chris Wilson)
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Brost Matthew <matthew.brost@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/gt/intel_context_types.h | 8 +++++++
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 ++++
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 23 +++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_engine_pm.h | 2 ++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 7 ++++++
.../drm/i915/gt/intel_execlists_submission.c | 2 ++
.../gpu/drm/i915/gt/intel_ring_submission.c | 3 +++
drivers/gpu/drm/i915/gt/mock_engine.c | 2 ++
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 12 +++++++---
9 files changed, 60 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 930569a1a01f..12252c411159 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -153,6 +153,14 @@ struct intel_context {
/** sseu: Control eu/slice partitioning */
struct intel_sseu sseu;
+ /**
+ * pinned_contexts_link: List link for the engine's pinned contexts.
+ * This is only used if this is a perma-pinned kernel context and
+ * the list is assumed to only be manipulated during driver load
+ * or unload time so no mutex protection currently.
+ */
+ struct list_head pinned_contexts_link;
+
u8 wa_bb_page; /* if set, page num reserved for context workarounds */
struct {
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 06dfe7f38953..2ae57e4656a3 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -320,6 +320,7 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES);
+ INIT_LIST_HEAD(&engine->pinned_contexts_list);
engine->id = id;
engine->legacy_idx = INVALID_ENGINE;
engine->mask = BIT(id);
@@ -890,6 +891,8 @@ intel_engine_create_pinned_context(struct intel_engine_cs *engine,
return ERR_PTR(err);
}
+ list_add_tail(&ce->pinned_contexts_link, &engine->pinned_contexts_list);
+
/*
* Give our perma-pinned kernel timelines a separate lockdep class,
* so that we can use them from within the normal user timelines
@@ -912,6 +915,7 @@ void intel_engine_destroy_pinned_context(struct intel_context *ce)
list_del(&ce->timeline->engine_link);
mutex_unlock(&hwsp->vm->mutex);
+ list_del(&ce->pinned_contexts_link);
intel_context_unpin(ce);
intel_context_put(ce);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index 1f07ac4e0672..dacd62773735 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -298,6 +298,29 @@ void intel_engine_init__pm(struct intel_engine_cs *engine)
intel_engine_init_heartbeat(engine);
}
+/**
+ * intel_engine_reset_pinned_contexts - Reset the pinned contexts of
+ * an engine.
+ * @engine: The engine whose pinned contexts we want to reset.
+ *
+ * Typically the pinned context LMEM images lose or get their content
+ * corrupted on suspend. This function resets their images.
+ */
+void intel_engine_reset_pinned_contexts(struct intel_engine_cs *engine)
+{
+ struct intel_context *ce;
+
+ list_for_each_entry(ce, &engine->pinned_contexts_list,
+ pinned_contexts_link) {
+ /* kernel context gets reset at __engine_unpark() */
+ if (ce == engine->kernel_context)
+ continue;
+
+ dbg_poison_ce(ce);
+ ce->ops->reset(ce);
+ }
+}
+
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "selftest_engine_pm.c"
#endif
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.h b/drivers/gpu/drm/i915/gt/intel_engine_pm.h
index 70ea46d6cfb0..8520c595f5e1 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.h
@@ -69,4 +69,6 @@ intel_engine_create_kernel_request(struct intel_engine_cs *engine)
void intel_engine_init__pm(struct intel_engine_cs *engine);
+void intel_engine_reset_pinned_contexts(struct intel_engine_cs *engine);
+
#endif /* INTEL_ENGINE_PM_H */
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index bfbfe53c23dd..5ae1207c363b 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -307,6 +307,13 @@ struct intel_engine_cs {
struct intel_context *kernel_context; /* pinned */
+ /**
+ * pinned_contexts_list: List of pinned contexts. This list is only
+ * assumed to be manipulated during driver load- or unload time and
+ * does therefore not have any additional protection.
+ */
+ struct list_head pinned_contexts_list;
+
intel_engine_mask_t saturated; /* submitting semaphores too late? */
struct {
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 87c595e4efe2..7147fe80919e 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2787,6 +2787,8 @@ static void execlists_sanitize(struct intel_engine_cs *engine)
/* And scrub the dirty cachelines for the HWSP */
clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
+
+ intel_engine_reset_pinned_contexts(engine);
}
static void enable_error_interrupt(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 3c65efcb7bed..593524195707 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -17,6 +17,7 @@
#include "intel_ring.h"
#include "shmem_utils.h"
#include "intel_engine_heartbeat.h"
+#include "intel_engine_pm.h"
/* Rough estimate of the typical request size, performing a flush,
* set-context and then emitting the batch.
@@ -292,6 +293,8 @@ static void xcs_sanitize(struct intel_engine_cs *engine)
/* And scrub the dirty cachelines for the HWSP */
clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
+
+ intel_engine_reset_pinned_contexts(engine);
}
static void reset_prepare(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/gt/mock_engine.c b/drivers/gpu/drm/i915/gt/mock_engine.c
index 2c1af030310c..8b89215afe46 100644
--- a/drivers/gpu/drm/i915/gt/mock_engine.c
+++ b/drivers/gpu/drm/i915/gt/mock_engine.c
@@ -376,6 +376,8 @@ int mock_engine_init(struct intel_engine_cs *engine)
{
struct intel_context *ce;
+ INIT_LIST_HEAD(&engine->pinned_contexts_list);
+
engine->sched_engine = i915_sched_engine_create(ENGINE_MOCK);
if (!engine->sched_engine)
return -ENOMEM;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index c7a41802b448..ba0de35f6323 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2477,6 +2477,8 @@ static void guc_sanitize(struct intel_engine_cs *engine)
/* And scrub the dirty cachelines for the HWSP */
clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
+
+ intel_engine_reset_pinned_contexts(engine);
}
static void setup_hwsp(struct intel_engine_cs *engine)
@@ -2552,9 +2554,13 @@ static inline void guc_init_lrc_mapping(struct intel_guc *guc)
* and even it did this code would be run again.
*/
- for_each_engine(engine, gt, id)
- if (engine->kernel_context)
- guc_kernel_context_pin(guc, engine->kernel_context);
+ for_each_engine(engine, gt, id) {
+ struct intel_context *ce;
+
+ list_for_each_entry(ce, &engine->pinned_contexts_list,
+ pinned_contexts_link)
+ guc_kernel_context_pin(guc, ce);
+ }
}
static void guc_release(struct intel_engine_cs *engine)
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [Intel-gfx] [PATCH v6 5/9] drm/i915/gt: Register the migrate contexts with their engines
@ 2021-09-22 6:25 ` Thomas Hellström
0 siblings, 0 replies; 39+ messages in thread
From: Thomas Hellström @ 2021-09-22 6:25 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: maarten.lankhorst, matthew.auld, Tvrtko Ursulin, Brost Matthew,
Chris Wilson, Thomas Hellström
Pinned contexts, like the migrate contexts need reset after resume
since their context image may have been lost. Also the GuC needs to
register pinned contexts.
Add a list to struct intel_engine_cs where we add all pinned contexts on
creation, and traverse that list at resume time to reset the pinned
contexts.
This fixes the kms_pipe_crc_basic@suspend-read-crc-pipe-a selftest for now,
but proper LMEM backup / restore is needed for full suspend functionality.
However, note that even with full LMEM backup / restore it may be
desirable to keep the reset since backing up the migrate context images
must happen using memcpy() after the migrate context has become inactive,
and for performance- and other reasons we want to avoid memcpy() from
LMEM.
Also traverse the list at guc_init_lrc_mapping() calling
guc_kernel_context_pin() for the pinned contexts, like is already done
for the kernel context.
v2:
- Don't reset the contexts on each __engine_unpark() but rather at
resume time (Chris Wilson).
v3:
- Reset contexts in the engine sanitize callback. (Chris Wilson)
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Brost Matthew <matthew.brost@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/gt/intel_context_types.h | 8 +++++++
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 4 ++++
drivers/gpu/drm/i915/gt/intel_engine_pm.c | 23 +++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_engine_pm.h | 2 ++
drivers/gpu/drm/i915/gt/intel_engine_types.h | 7 ++++++
.../drm/i915/gt/intel_execlists_submission.c | 2 ++
.../gpu/drm/i915/gt/intel_ring_submission.c | 3 +++
drivers/gpu/drm/i915/gt/mock_engine.c | 2 ++
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 12 +++++++---
9 files changed, 60 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_context_types.h b/drivers/gpu/drm/i915/gt/intel_context_types.h
index 930569a1a01f..12252c411159 100644
--- a/drivers/gpu/drm/i915/gt/intel_context_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
@@ -153,6 +153,14 @@ struct intel_context {
/** sseu: Control eu/slice partitioning */
struct intel_sseu sseu;
+ /**
+ * pinned_contexts_link: List link for the engine's pinned contexts.
+ * This is only used if this is a perma-pinned kernel context and
+ * the list is assumed to only be manipulated during driver load
+ * or unload time so no mutex protection currently.
+ */
+ struct list_head pinned_contexts_link;
+
u8 wa_bb_page; /* if set, page num reserved for context workarounds */
struct {
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 06dfe7f38953..2ae57e4656a3 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -320,6 +320,7 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES);
+ INIT_LIST_HEAD(&engine->pinned_contexts_list);
engine->id = id;
engine->legacy_idx = INVALID_ENGINE;
engine->mask = BIT(id);
@@ -890,6 +891,8 @@ intel_engine_create_pinned_context(struct intel_engine_cs *engine,
return ERR_PTR(err);
}
+ list_add_tail(&ce->pinned_contexts_link, &engine->pinned_contexts_list);
+
/*
* Give our perma-pinned kernel timelines a separate lockdep class,
* so that we can use them from within the normal user timelines
@@ -912,6 +915,7 @@ void intel_engine_destroy_pinned_context(struct intel_context *ce)
list_del(&ce->timeline->engine_link);
mutex_unlock(&hwsp->vm->mutex);
+ list_del(&ce->pinned_contexts_link);
intel_context_unpin(ce);
intel_context_put(ce);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.c b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
index 1f07ac4e0672..dacd62773735 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.c
@@ -298,6 +298,29 @@ void intel_engine_init__pm(struct intel_engine_cs *engine)
intel_engine_init_heartbeat(engine);
}
+/**
+ * intel_engine_reset_pinned_contexts - Reset the pinned contexts of
+ * an engine.
+ * @engine: The engine whose pinned contexts we want to reset.
+ *
+ * Typically the pinned context LMEM images lose or get their content
+ * corrupted on suspend. This function resets their images.
+ */
+void intel_engine_reset_pinned_contexts(struct intel_engine_cs *engine)
+{
+ struct intel_context *ce;
+
+ list_for_each_entry(ce, &engine->pinned_contexts_list,
+ pinned_contexts_link) {
+ /* kernel context gets reset at __engine_unpark() */
+ if (ce == engine->kernel_context)
+ continue;
+
+ dbg_poison_ce(ce);
+ ce->ops->reset(ce);
+ }
+}
+
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "selftest_engine_pm.c"
#endif
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_pm.h b/drivers/gpu/drm/i915/gt/intel_engine_pm.h
index 70ea46d6cfb0..8520c595f5e1 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_pm.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_pm.h
@@ -69,4 +69,6 @@ intel_engine_create_kernel_request(struct intel_engine_cs *engine)
void intel_engine_init__pm(struct intel_engine_cs *engine);
+void intel_engine_reset_pinned_contexts(struct intel_engine_cs *engine);
+
#endif /* INTEL_ENGINE_PM_H */
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index bfbfe53c23dd..5ae1207c363b 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -307,6 +307,13 @@ struct intel_engine_cs {
struct intel_context *kernel_context; /* pinned */
+ /**
+ * pinned_contexts_list: List of pinned contexts. This list is only
+ * assumed to be manipulated during driver load- or unload time and
+ * does therefore not have any additional protection.
+ */
+ struct list_head pinned_contexts_list;
+
intel_engine_mask_t saturated; /* submitting semaphores too late? */
struct {
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 87c595e4efe2..7147fe80919e 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2787,6 +2787,8 @@ static void execlists_sanitize(struct intel_engine_cs *engine)
/* And scrub the dirty cachelines for the HWSP */
clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
+
+ intel_engine_reset_pinned_contexts(engine);
}
static void enable_error_interrupt(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 3c65efcb7bed..593524195707 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -17,6 +17,7 @@
#include "intel_ring.h"
#include "shmem_utils.h"
#include "intel_engine_heartbeat.h"
+#include "intel_engine_pm.h"
/* Rough estimate of the typical request size, performing a flush,
* set-context and then emitting the batch.
@@ -292,6 +293,8 @@ static void xcs_sanitize(struct intel_engine_cs *engine)
/* And scrub the dirty cachelines for the HWSP */
clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
+
+ intel_engine_reset_pinned_contexts(engine);
}
static void reset_prepare(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/gt/mock_engine.c b/drivers/gpu/drm/i915/gt/mock_engine.c
index 2c1af030310c..8b89215afe46 100644
--- a/drivers/gpu/drm/i915/gt/mock_engine.c
+++ b/drivers/gpu/drm/i915/gt/mock_engine.c
@@ -376,6 +376,8 @@ int mock_engine_init(struct intel_engine_cs *engine)
{
struct intel_context *ce;
+ INIT_LIST_HEAD(&engine->pinned_contexts_list);
+
engine->sched_engine = i915_sched_engine_create(ENGINE_MOCK);
if (!engine->sched_engine)
return -ENOMEM;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index c7a41802b448..ba0de35f6323 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -2477,6 +2477,8 @@ static void guc_sanitize(struct intel_engine_cs *engine)
/* And scrub the dirty cachelines for the HWSP */
clflush_cache_range(engine->status_page.addr, PAGE_SIZE);
+
+ intel_engine_reset_pinned_contexts(engine);
}
static void setup_hwsp(struct intel_engine_cs *engine)
@@ -2552,9 +2554,13 @@ static inline void guc_init_lrc_mapping(struct intel_guc *guc)
* and even it did this code would be run again.
*/
- for_each_engine(engine, gt, id)
- if (engine->kernel_context)
- guc_kernel_context_pin(guc, engine->kernel_context);
+ for_each_engine(engine, gt, id) {
+ struct intel_context *ce;
+
+ list_for_each_entry(ce, &engine->pinned_contexts_list,
+ pinned_contexts_link)
+ guc_kernel_context_pin(guc, ce);
+ }
}
static void guc_release(struct intel_engine_cs *engine)
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v6 6/9] drm/i915: Don't back up pinned LMEM context images and rings during suspend
2021-09-22 6:25 ` [Intel-gfx] " Thomas Hellström
@ 2021-09-22 6:25 ` Thomas Hellström
-1 siblings, 0 replies; 39+ messages in thread
From: Thomas Hellström @ 2021-09-22 6:25 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: maarten.lankhorst, matthew.auld, Thomas Hellström
Pinned context images are now reset during resume. Don't back them up,
and assuming that rings can be assumed empty at suspend, don't back them
up either.
Introduce a new object flag, I915_BO_ALLOC_PM_VOLATILE meaning that an
object is allowed to lose its content on suspend.
v3:
- Slight documentation clarification (Matthew Auld)
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
.../gpu/drm/i915/gem/i915_gem_object_types.h | 17 ++++++++++-------
drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c | 3 +++
drivers/gpu/drm/i915/gt/intel_lrc.c | 3 ++-
drivers/gpu/drm/i915/gt/intel_ring.c | 3 ++-
4 files changed, 17 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 734cc8e16481..118691ce81d7 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -288,16 +288,19 @@ struct drm_i915_gem_object {
I915_SELFTEST_DECLARE(struct list_head st_link);
unsigned long flags;
-#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
-#define I915_BO_ALLOC_VOLATILE BIT(1)
-#define I915_BO_ALLOC_CPU_CLEAR BIT(2)
-#define I915_BO_ALLOC_USER BIT(3)
+#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
+#define I915_BO_ALLOC_VOLATILE BIT(1)
+#define I915_BO_ALLOC_CPU_CLEAR BIT(2)
+#define I915_BO_ALLOC_USER BIT(3)
+/* Object is allowed to lose its contents on suspend / resume, even if pinned */
+#define I915_BO_ALLOC_PM_VOLATILE BIT(4)
#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
I915_BO_ALLOC_VOLATILE | \
I915_BO_ALLOC_CPU_CLEAR | \
- I915_BO_ALLOC_USER)
-#define I915_BO_READONLY BIT(4)
-#define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */
+ I915_BO_ALLOC_USER | \
+ I915_BO_ALLOC_PM_VOLATILE)
+#define I915_BO_READONLY BIT(5)
+#define I915_TILING_QUIRK_BIT 6 /* unknown swizzling; do not release! */
/**
* @mem_flags - Mutable placement-related flags
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
index cb1c46724f70..03a00d193f40 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
@@ -60,6 +60,9 @@ static int i915_ttm_backup(struct i915_gem_apply_to_region *apply,
if (!pm_apply->backup_pinned)
return 0;
+ if (obj->flags & I915_BO_ALLOC_PM_VOLATILE)
+ return 0;
+
backup = i915_gem_object_create_shmem(i915, obj->base.size);
if (IS_ERR(backup))
return PTR_ERR(backup);
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 6ba8daea2f56..3ef9eaf8c50e 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -942,7 +942,8 @@ __lrc_alloc_state(struct intel_context *ce, struct intel_engine_cs *engine)
context_size += PAGE_SIZE;
}
- obj = i915_gem_object_create_lmem(engine->i915, context_size, 0);
+ obj = i915_gem_object_create_lmem(engine->i915, context_size,
+ I915_BO_ALLOC_PM_VOLATILE);
if (IS_ERR(obj))
obj = i915_gem_object_create_shmem(engine->i915, context_size);
if (IS_ERR(obj))
diff --git a/drivers/gpu/drm/i915/gt/intel_ring.c b/drivers/gpu/drm/i915/gt/intel_ring.c
index 7c4d5158e03b..2fdd52b62092 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring.c
@@ -112,7 +112,8 @@ static struct i915_vma *create_ring_vma(struct i915_ggtt *ggtt, int size)
struct drm_i915_gem_object *obj;
struct i915_vma *vma;
- obj = i915_gem_object_create_lmem(i915, size, I915_BO_ALLOC_VOLATILE);
+ obj = i915_gem_object_create_lmem(i915, size, I915_BO_ALLOC_VOLATILE |
+ I915_BO_ALLOC_PM_VOLATILE);
if (IS_ERR(obj) && i915_ggtt_has_aperture(ggtt))
obj = i915_gem_object_create_stolen(i915, size);
if (IS_ERR(obj))
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [Intel-gfx] [PATCH v6 6/9] drm/i915: Don't back up pinned LMEM context images and rings during suspend
@ 2021-09-22 6:25 ` Thomas Hellström
0 siblings, 0 replies; 39+ messages in thread
From: Thomas Hellström @ 2021-09-22 6:25 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: maarten.lankhorst, matthew.auld, Thomas Hellström
Pinned context images are now reset during resume. Don't back them up,
and assuming that rings can be assumed empty at suspend, don't back them
up either.
Introduce a new object flag, I915_BO_ALLOC_PM_VOLATILE meaning that an
object is allowed to lose its content on suspend.
v3:
- Slight documentation clarification (Matthew Auld)
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
.../gpu/drm/i915/gem/i915_gem_object_types.h | 17 ++++++++++-------
drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c | 3 +++
drivers/gpu/drm/i915/gt/intel_lrc.c | 3 ++-
drivers/gpu/drm/i915/gt/intel_ring.c | 3 ++-
4 files changed, 17 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 734cc8e16481..118691ce81d7 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -288,16 +288,19 @@ struct drm_i915_gem_object {
I915_SELFTEST_DECLARE(struct list_head st_link);
unsigned long flags;
-#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
-#define I915_BO_ALLOC_VOLATILE BIT(1)
-#define I915_BO_ALLOC_CPU_CLEAR BIT(2)
-#define I915_BO_ALLOC_USER BIT(3)
+#define I915_BO_ALLOC_CONTIGUOUS BIT(0)
+#define I915_BO_ALLOC_VOLATILE BIT(1)
+#define I915_BO_ALLOC_CPU_CLEAR BIT(2)
+#define I915_BO_ALLOC_USER BIT(3)
+/* Object is allowed to lose its contents on suspend / resume, even if pinned */
+#define I915_BO_ALLOC_PM_VOLATILE BIT(4)
#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
I915_BO_ALLOC_VOLATILE | \
I915_BO_ALLOC_CPU_CLEAR | \
- I915_BO_ALLOC_USER)
-#define I915_BO_READONLY BIT(4)
-#define I915_TILING_QUIRK_BIT 5 /* unknown swizzling; do not release! */
+ I915_BO_ALLOC_USER | \
+ I915_BO_ALLOC_PM_VOLATILE)
+#define I915_BO_READONLY BIT(5)
+#define I915_TILING_QUIRK_BIT 6 /* unknown swizzling; do not release! */
/**
* @mem_flags - Mutable placement-related flags
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
index cb1c46724f70..03a00d193f40 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
@@ -60,6 +60,9 @@ static int i915_ttm_backup(struct i915_gem_apply_to_region *apply,
if (!pm_apply->backup_pinned)
return 0;
+ if (obj->flags & I915_BO_ALLOC_PM_VOLATILE)
+ return 0;
+
backup = i915_gem_object_create_shmem(i915, obj->base.size);
if (IS_ERR(backup))
return PTR_ERR(backup);
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 6ba8daea2f56..3ef9eaf8c50e 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -942,7 +942,8 @@ __lrc_alloc_state(struct intel_context *ce, struct intel_engine_cs *engine)
context_size += PAGE_SIZE;
}
- obj = i915_gem_object_create_lmem(engine->i915, context_size, 0);
+ obj = i915_gem_object_create_lmem(engine->i915, context_size,
+ I915_BO_ALLOC_PM_VOLATILE);
if (IS_ERR(obj))
obj = i915_gem_object_create_shmem(engine->i915, context_size);
if (IS_ERR(obj))
diff --git a/drivers/gpu/drm/i915/gt/intel_ring.c b/drivers/gpu/drm/i915/gt/intel_ring.c
index 7c4d5158e03b..2fdd52b62092 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring.c
@@ -112,7 +112,8 @@ static struct i915_vma *create_ring_vma(struct i915_ggtt *ggtt, int size)
struct drm_i915_gem_object *obj;
struct i915_vma *vma;
- obj = i915_gem_object_create_lmem(i915, size, I915_BO_ALLOC_VOLATILE);
+ obj = i915_gem_object_create_lmem(i915, size, I915_BO_ALLOC_VOLATILE |
+ I915_BO_ALLOC_PM_VOLATILE);
if (IS_ERR(obj) && i915_ggtt_has_aperture(ggtt))
obj = i915_gem_object_create_stolen(i915, size);
if (IS_ERR(obj))
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v6 7/9] drm/i915: Reduce the number of objects subject to memcpy recover
2021-09-22 6:25 ` [Intel-gfx] " Thomas Hellström
@ 2021-09-22 6:25 ` Thomas Hellström
-1 siblings, 0 replies; 39+ messages in thread
From: Thomas Hellström @ 2021-09-22 6:25 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: maarten.lankhorst, matthew.auld, Matthew Brost, Thomas Hellström
We really only need memcpy restore for objects that affect the
operability of the migrate context. That is, primarily the page-table
objects of the migrate VM.
Add an object flag, I915_BO_ALLOC_PM_EARLY for objects that need early
restores using memcpy and a way to assign LMEM page-table object flags
to be used by the vms.
Restore objects without this flag with the gpu blitter and only objects
carrying the flag using TTM memcpy.
Initially mark the migrate, gt, gtt and vgpu vms to use this flag, and
defer for a later audit which vms actually need it. Most importantly, user-
allocated vms with pinned page-table objects can be restored using the
blitter.
Performance-wise memcpy restore is probably as fast as gpu restore if not
faster, but using gpu restore will help tackling future restrictions in
mappable LMEM size.
v4:
- Don't mark the aliasing ppgtt page table flags for early resume, but
rather the ggtt page table flags as intended. (Matthew Auld)
- The check for user buffer objects during early resume is pointless, since
they are never marked I915_BO_ALLOC_PM_EARLY. (Matthew Auld)
v5:
- Mark GuC LMEM objects with I915_BO_ALLOC_PM_EARLY to have them restored
before we fire up the migrate context.
Cc: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 4 ++--
drivers/gpu/drm/i915/gem/i915_gem_object_types.h | 9 ++++++---
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 6 +++++-
drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c | 5 +++--
drivers/gpu/drm/i915/gem/selftests/huge_pages.c | 2 +-
drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 2 +-
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 5 +++--
drivers/gpu/drm/i915/gt/gen8_ppgtt.h | 4 +++-
drivers/gpu/drm/i915/gt/intel_ggtt.c | 3 ++-
drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gtt.c | 3 ++-
drivers/gpu/drm/i915/gt/intel_gtt.h | 9 +++++++--
drivers/gpu/drm/i915/gt/intel_migrate.c | 2 +-
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 13 ++++++++-----
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 3 ++-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 7 +++++--
drivers/gpu/drm/i915/gvt/scheduler.c | 2 +-
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 4 ++--
19 files changed, 56 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index c2ab0e22db0a..8208fd5b72c3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1287,7 +1287,7 @@ i915_gem_create_context(struct drm_i915_private *i915,
} else if (HAS_FULL_PPGTT(i915)) {
struct i915_ppgtt *ppgtt;
- ppgtt = i915_ppgtt_create(&i915->gt);
+ ppgtt = i915_ppgtt_create(&i915->gt, 0);
if (IS_ERR(ppgtt)) {
drm_dbg(&i915->drm, "PPGTT setup failed (%ld)\n",
PTR_ERR(ppgtt));
@@ -1465,7 +1465,7 @@ int i915_gem_vm_create_ioctl(struct drm_device *dev, void *data,
if (args->flags)
return -EINVAL;
- ppgtt = i915_ppgtt_create(&i915->gt);
+ ppgtt = i915_ppgtt_create(&i915->gt, 0);
if (IS_ERR(ppgtt))
return PTR_ERR(ppgtt);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 118691ce81d7..fa2ba9e2a4d0 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -294,13 +294,16 @@ struct drm_i915_gem_object {
#define I915_BO_ALLOC_USER BIT(3)
/* Object is allowed to lose its contents on suspend / resume, even if pinned */
#define I915_BO_ALLOC_PM_VOLATILE BIT(4)
+/* Object needs to be restored early using memcpy during resume */
+#define I915_BO_ALLOC_PM_EARLY BIT(5)
#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
I915_BO_ALLOC_VOLATILE | \
I915_BO_ALLOC_CPU_CLEAR | \
I915_BO_ALLOC_USER | \
- I915_BO_ALLOC_PM_VOLATILE)
-#define I915_BO_READONLY BIT(5)
-#define I915_TILING_QUIRK_BIT 6 /* unknown swizzling; do not release! */
+ I915_BO_ALLOC_PM_VOLATILE | \
+ I915_BO_ALLOC_PM_EARLY)
+#define I915_BO_READONLY BIT(6)
+#define I915_TILING_QUIRK_BIT 7 /* unknown swizzling; do not release! */
/**
* @mem_flags - Mutable placement-related flags
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
index 12b37b4c1192..726b40e1fbb0 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
@@ -97,8 +97,12 @@ int i915_gem_backup_suspend(struct drm_i915_private *i915)
* More objects may have become unpinned as requests were
* retired. Now try to evict again. The gt may be wedged here
* in which case we automatically fall back to memcpy.
+ * We allow also backing up pinned objects that have not been
+ * marked for early recover, and that may contain, for example,
+ * page-tables for the migrate context.
*/
- ret = lmem_suspend(i915, I915_TTM_BACKUP_ALLOW_GPU);
+ ret = lmem_suspend(i915, I915_TTM_BACKUP_ALLOW_GPU |
+ I915_TTM_BACKUP_PINNED);
if (ret)
goto out_recover;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
index 03a00d193f40..3b6d14b5c604 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
@@ -57,7 +57,8 @@ static int i915_ttm_backup(struct i915_gem_apply_to_region *apply,
if (pm_apply->allow_gpu && i915_gem_object_evictable(obj))
return ttm_bo_validate(bo, i915_ttm_sys_placement(), &ctx);
- if (!pm_apply->backup_pinned)
+ if (!pm_apply->backup_pinned ||
+ (pm_apply->allow_gpu && (obj->flags & I915_BO_ALLOC_PM_EARLY)))
return 0;
if (obj->flags & I915_BO_ALLOC_PM_VOLATILE)
@@ -155,7 +156,7 @@ static int i915_ttm_restore(struct i915_gem_apply_to_region *apply,
if (!backup)
return 0;
- if (!pm_apply->allow_gpu && (obj->flags & I915_BO_ALLOC_USER))
+ if (!pm_apply->allow_gpu && !(obj->flags & I915_BO_ALLOC_PM_EARLY))
return 0;
err = i915_gem_object_lock(backup, apply->ww);
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index 0827634c842c..77d84a9e8789 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -1645,7 +1645,7 @@ int i915_gem_huge_page_mock_selftests(void)
mkwrite_device_info(dev_priv)->ppgtt_type = INTEL_PPGTT_FULL;
mkwrite_device_info(dev_priv)->ppgtt_size = 48;
- ppgtt = i915_ppgtt_create(&dev_priv->gt);
+ ppgtt = i915_ppgtt_create(&dev_priv->gt, 0);
if (IS_ERR(ppgtt)) {
err = PTR_ERR(ppgtt);
goto out_unlock;
diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
index 1aee5e6b1b23..890191f286e3 100644
--- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
@@ -429,7 +429,7 @@ struct i915_ppgtt *gen6_ppgtt_create(struct intel_gt *gt)
mutex_init(&ppgtt->flush);
mutex_init(&ppgtt->pin_mutex);
- ppgtt_init(&ppgtt->base, gt);
+ ppgtt_init(&ppgtt->base, gt, 0);
ppgtt->base.vm.pd_shift = ilog2(SZ_4K * SZ_4K / sizeof(gen6_pte_t));
ppgtt->base.vm.top = 1;
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 6a5af995f5b1..037a9a6e4889 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -753,7 +753,8 @@ gen8_alloc_top_pd(struct i915_address_space *vm)
* space.
*
*/
-struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
+struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
+ unsigned long lmem_pt_obj_flags)
{
struct i915_ppgtt *ppgtt;
int err;
@@ -762,7 +763,7 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
if (!ppgtt)
return ERR_PTR(-ENOMEM);
- ppgtt_init(ppgtt, gt);
+ ppgtt_init(ppgtt, gt, lmem_pt_obj_flags);
ppgtt->vm.top = i915_vm_is_4lvl(&ppgtt->vm) ? 3 : 2;
ppgtt->vm.pd_shift = ilog2(SZ_4K * SZ_4K / sizeof(gen8_pte_t));
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.h b/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
index b9028c2ad3c7..f541d19264b4 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
@@ -12,7 +12,9 @@ struct i915_address_space;
struct intel_gt;
enum i915_cache_level;
-struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt);
+struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
+ unsigned long lmem_pt_obj_flags);
+
u64 gen8_ggtt_pte_encode(dma_addr_t addr,
enum i915_cache_level level,
u32 flags);
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 8d71f67926f1..06576fc1310e 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -644,7 +644,7 @@ static int init_aliasing_ppgtt(struct i915_ggtt *ggtt)
struct i915_ppgtt *ppgtt;
int err;
- ppgtt = i915_ppgtt_create(ggtt->vm.gt);
+ ppgtt = i915_ppgtt_create(ggtt->vm.gt, 0);
if (IS_ERR(ppgtt))
return PTR_ERR(ppgtt);
@@ -909,6 +909,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
size = gen8_get_total_gtt_size(snb_gmch_ctl);
ggtt->vm.alloc_pt_dma = alloc_pt_dma;
+ ggtt->vm.lmem_pt_obj_flags = I915_BO_ALLOC_PM_EARLY;
ggtt->vm.total = (size / sizeof(gen8_pte_t)) * I915_GTT_PAGE_SIZE;
ggtt->vm.cleanup = gen6_gmch_remove;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 5753c5943ed9..4037c3778225 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -481,7 +481,7 @@ static void intel_gt_fini_scratch(struct intel_gt *gt)
static struct i915_address_space *kernel_vm(struct intel_gt *gt)
{
if (INTEL_PPGTT(gt->i915) > INTEL_PPGTT_ALIASING)
- return &i915_ppgtt_create(gt)->vm;
+ return &i915_ppgtt_create(gt, I915_BO_ALLOC_PM_EARLY)->vm;
else
return i915_vm_get(>->ggtt->vm);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index a0c2b952aa57..67d14afa6623 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -28,7 +28,8 @@ struct drm_i915_gem_object *alloc_pt_lmem(struct i915_address_space *vm, int sz)
* used the passed in size for the page size, which should ensure it
* also has the same alignment.
*/
- obj = __i915_gem_object_create_lmem_with_ps(vm->i915, sz, sz, 0);
+ obj = __i915_gem_object_create_lmem_with_ps(vm->i915, sz, sz,
+ vm->lmem_pt_obj_flags);
/*
* Ensure all paging structures for this vm share the same dma-resv
* object underneath, with the idea that one object_lock() will lock
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
index 5b539bd7645d..bc6750263359 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -260,6 +260,9 @@ struct i915_address_space {
u8 pd_shift;
u8 scratch_order;
+ /* Flags used when creating page-table objects for this vm */
+ unsigned long lmem_pt_obj_flags;
+
struct drm_i915_gem_object *
(*alloc_pt_dma)(struct i915_address_space *vm, int sz);
@@ -519,7 +522,8 @@ i915_page_dir_dma_addr(const struct i915_ppgtt *ppgtt, const unsigned int n)
return __px_dma(pt ? px_base(pt) : ppgtt->vm.scratch[ppgtt->vm.top]);
}
-void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt);
+void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt,
+ unsigned long lmem_pt_obj_flags);
int i915_ggtt_probe_hw(struct drm_i915_private *i915);
int i915_ggtt_init_hw(struct drm_i915_private *i915);
@@ -537,7 +541,8 @@ static inline bool i915_ggtt_has_aperture(const struct i915_ggtt *ggtt)
int i915_ppgtt_init_hw(struct intel_gt *gt);
-struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt);
+struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt,
+ unsigned long lmem_pt_obj_flags);
void i915_ggtt_suspend(struct i915_ggtt *gtt);
void i915_ggtt_resume(struct i915_ggtt *ggtt);
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
index 1dac21aa7e5c..afb1cce9a352 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -78,7 +78,7 @@ static struct i915_address_space *migrate_vm(struct intel_gt *gt)
* TODO: Add support for huge LMEM PTEs
*/
- vm = i915_ppgtt_create(gt);
+ vm = i915_ppgtt_create(gt, I915_BO_ALLOC_PM_EARLY);
if (IS_ERR(vm))
return ERR_CAST(vm);
diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
index 886060f7e6fc..4396bfd630d8 100644
--- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
@@ -155,19 +155,20 @@ int i915_ppgtt_init_hw(struct intel_gt *gt)
}
static struct i915_ppgtt *
-__ppgtt_create(struct intel_gt *gt)
+__ppgtt_create(struct intel_gt *gt, unsigned long lmem_pt_obj_flags)
{
if (GRAPHICS_VER(gt->i915) < 8)
return gen6_ppgtt_create(gt);
else
- return gen8_ppgtt_create(gt);
+ return gen8_ppgtt_create(gt, lmem_pt_obj_flags);
}
-struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt)
+struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt,
+ unsigned long lmem_pt_obj_flags)
{
struct i915_ppgtt *ppgtt;
- ppgtt = __ppgtt_create(gt);
+ ppgtt = __ppgtt_create(gt, lmem_pt_obj_flags);
if (IS_ERR(ppgtt))
return ppgtt;
@@ -298,7 +299,8 @@ int ppgtt_set_pages(struct i915_vma *vma)
return 0;
}
-void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt)
+void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt,
+ unsigned long lmem_pt_obj_flags)
{
struct drm_i915_private *i915 = gt->i915;
@@ -306,6 +308,7 @@ void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt)
ppgtt->vm.i915 = i915;
ppgtt->vm.dma = i915->drm.dev;
ppgtt->vm.total = BIT_ULL(INTEL_INFO(i915)->ppgtt_size);
+ ppgtt->vm.lmem_pt_obj_flags = lmem_pt_obj_flags;
dma_resv_init(&ppgtt->vm._resv);
i915_address_space_init(&ppgtt->vm, VM_CLASS_PPGTT);
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index 7e6fdabac599..7e2d99dd012d 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -1596,7 +1596,7 @@ static int igt_reset_evict_ppgtt(void *arg)
if (INTEL_PPGTT(gt->i915) < INTEL_PPGTT_FULL)
return 0;
- ppgtt = i915_ppgtt_create(gt);
+ ppgtt = i915_ppgtt_create(gt, 0);
if (IS_ERR(ppgtt))
return PTR_ERR(ppgtt);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 8ffb689066f6..8f8182bf7c11 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -651,7 +651,8 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
if (HAS_LMEM(gt->i915))
obj = i915_gem_object_create_lmem(gt->i915, size,
I915_BO_ALLOC_CPU_CLEAR |
- I915_BO_ALLOC_CONTIGUOUS);
+ I915_BO_ALLOC_CONTIGUOUS |
+ I915_BO_ALLOC_PM_EARLY);
else
obj = i915_gem_object_create_shmem(gt->i915, size);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index a685d563df72..3aa87be4f2e4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -372,10 +372,13 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
if (uc_fw->type == INTEL_UC_FW_TYPE_GUC)
uc_fw->private_data_size = css->private_data_size;
- if (HAS_LMEM(i915))
+ if (HAS_LMEM(i915)) {
obj = i915_gem_object_create_lmem_from_data(i915, fw->data, fw->size);
- else
+ if (!IS_ERR(obj))
+ obj->flags |= I915_BO_ALLOC_PM_EARLY;
+ } else {
obj = i915_gem_object_create_shmem_from_data(i915, fw->data, fw->size);
+ }
if (IS_ERR(obj)) {
err = PTR_ERR(obj);
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
index b56a8e37a3cd..0d18e13e3468 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -1386,7 +1386,7 @@ int intel_vgpu_setup_submission(struct intel_vgpu *vgpu)
enum intel_engine_id i;
int ret;
- ppgtt = i915_ppgtt_create(&i915->gt);
+ ppgtt = i915_ppgtt_create(&i915->gt, I915_BO_ALLOC_PM_EARLY);
if (IS_ERR(ppgtt))
return PTR_ERR(ppgtt);
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 2d60a5a5b065..46f4236039a9 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -155,7 +155,7 @@ static int igt_ppgtt_alloc(void *arg)
if (!HAS_PPGTT(dev_priv))
return 0;
- ppgtt = i915_ppgtt_create(&dev_priv->gt);
+ ppgtt = i915_ppgtt_create(&dev_priv->gt, 0);
if (IS_ERR(ppgtt))
return PTR_ERR(ppgtt);
@@ -1053,7 +1053,7 @@ static int exercise_ppgtt(struct drm_i915_private *dev_priv,
if (IS_ERR(file))
return PTR_ERR(file);
- ppgtt = i915_ppgtt_create(&dev_priv->gt);
+ ppgtt = i915_ppgtt_create(&dev_priv->gt, 0);
if (IS_ERR(ppgtt)) {
err = PTR_ERR(ppgtt);
goto out_free;
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [Intel-gfx] [PATCH v6 7/9] drm/i915: Reduce the number of objects subject to memcpy recover
@ 2021-09-22 6:25 ` Thomas Hellström
0 siblings, 0 replies; 39+ messages in thread
From: Thomas Hellström @ 2021-09-22 6:25 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: maarten.lankhorst, matthew.auld, Matthew Brost, Thomas Hellström
We really only need memcpy restore for objects that affect the
operability of the migrate context. That is, primarily the page-table
objects of the migrate VM.
Add an object flag, I915_BO_ALLOC_PM_EARLY for objects that need early
restores using memcpy and a way to assign LMEM page-table object flags
to be used by the vms.
Restore objects without this flag with the gpu blitter and only objects
carrying the flag using TTM memcpy.
Initially mark the migrate, gt, gtt and vgpu vms to use this flag, and
defer for a later audit which vms actually need it. Most importantly, user-
allocated vms with pinned page-table objects can be restored using the
blitter.
Performance-wise memcpy restore is probably as fast as gpu restore if not
faster, but using gpu restore will help tackling future restrictions in
mappable LMEM size.
v4:
- Don't mark the aliasing ppgtt page table flags for early resume, but
rather the ggtt page table flags as intended. (Matthew Auld)
- The check for user buffer objects during early resume is pointless, since
they are never marked I915_BO_ALLOC_PM_EARLY. (Matthew Auld)
v5:
- Mark GuC LMEM objects with I915_BO_ALLOC_PM_EARLY to have them restored
before we fire up the migrate context.
Cc: Matthew Brost <matthew.brost@intel.com>
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 4 ++--
drivers/gpu/drm/i915/gem/i915_gem_object_types.h | 9 ++++++---
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 6 +++++-
drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c | 5 +++--
drivers/gpu/drm/i915/gem/selftests/huge_pages.c | 2 +-
drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 2 +-
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 5 +++--
drivers/gpu/drm/i915/gt/gen8_ppgtt.h | 4 +++-
drivers/gpu/drm/i915/gt/intel_ggtt.c | 3 ++-
drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gtt.c | 3 ++-
drivers/gpu/drm/i915/gt/intel_gtt.h | 9 +++++++--
drivers/gpu/drm/i915/gt/intel_migrate.c | 2 +-
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 13 ++++++++-----
drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 2 +-
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 3 ++-
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 7 +++++--
drivers/gpu/drm/i915/gvt/scheduler.c | 2 +-
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 4 ++--
19 files changed, 56 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index c2ab0e22db0a..8208fd5b72c3 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -1287,7 +1287,7 @@ i915_gem_create_context(struct drm_i915_private *i915,
} else if (HAS_FULL_PPGTT(i915)) {
struct i915_ppgtt *ppgtt;
- ppgtt = i915_ppgtt_create(&i915->gt);
+ ppgtt = i915_ppgtt_create(&i915->gt, 0);
if (IS_ERR(ppgtt)) {
drm_dbg(&i915->drm, "PPGTT setup failed (%ld)\n",
PTR_ERR(ppgtt));
@@ -1465,7 +1465,7 @@ int i915_gem_vm_create_ioctl(struct drm_device *dev, void *data,
if (args->flags)
return -EINVAL;
- ppgtt = i915_ppgtt_create(&i915->gt);
+ ppgtt = i915_ppgtt_create(&i915->gt, 0);
if (IS_ERR(ppgtt))
return PTR_ERR(ppgtt);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 118691ce81d7..fa2ba9e2a4d0 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -294,13 +294,16 @@ struct drm_i915_gem_object {
#define I915_BO_ALLOC_USER BIT(3)
/* Object is allowed to lose its contents on suspend / resume, even if pinned */
#define I915_BO_ALLOC_PM_VOLATILE BIT(4)
+/* Object needs to be restored early using memcpy during resume */
+#define I915_BO_ALLOC_PM_EARLY BIT(5)
#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
I915_BO_ALLOC_VOLATILE | \
I915_BO_ALLOC_CPU_CLEAR | \
I915_BO_ALLOC_USER | \
- I915_BO_ALLOC_PM_VOLATILE)
-#define I915_BO_READONLY BIT(5)
-#define I915_TILING_QUIRK_BIT 6 /* unknown swizzling; do not release! */
+ I915_BO_ALLOC_PM_VOLATILE | \
+ I915_BO_ALLOC_PM_EARLY)
+#define I915_BO_READONLY BIT(6)
+#define I915_TILING_QUIRK_BIT 7 /* unknown swizzling; do not release! */
/**
* @mem_flags - Mutable placement-related flags
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
index 12b37b4c1192..726b40e1fbb0 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
@@ -97,8 +97,12 @@ int i915_gem_backup_suspend(struct drm_i915_private *i915)
* More objects may have become unpinned as requests were
* retired. Now try to evict again. The gt may be wedged here
* in which case we automatically fall back to memcpy.
+ * We allow also backing up pinned objects that have not been
+ * marked for early recover, and that may contain, for example,
+ * page-tables for the migrate context.
*/
- ret = lmem_suspend(i915, I915_TTM_BACKUP_ALLOW_GPU);
+ ret = lmem_suspend(i915, I915_TTM_BACKUP_ALLOW_GPU |
+ I915_TTM_BACKUP_PINNED);
if (ret)
goto out_recover;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
index 03a00d193f40..3b6d14b5c604 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
@@ -57,7 +57,8 @@ static int i915_ttm_backup(struct i915_gem_apply_to_region *apply,
if (pm_apply->allow_gpu && i915_gem_object_evictable(obj))
return ttm_bo_validate(bo, i915_ttm_sys_placement(), &ctx);
- if (!pm_apply->backup_pinned)
+ if (!pm_apply->backup_pinned ||
+ (pm_apply->allow_gpu && (obj->flags & I915_BO_ALLOC_PM_EARLY)))
return 0;
if (obj->flags & I915_BO_ALLOC_PM_VOLATILE)
@@ -155,7 +156,7 @@ static int i915_ttm_restore(struct i915_gem_apply_to_region *apply,
if (!backup)
return 0;
- if (!pm_apply->allow_gpu && (obj->flags & I915_BO_ALLOC_USER))
+ if (!pm_apply->allow_gpu && !(obj->flags & I915_BO_ALLOC_PM_EARLY))
return 0;
err = i915_gem_object_lock(backup, apply->ww);
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index 0827634c842c..77d84a9e8789 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -1645,7 +1645,7 @@ int i915_gem_huge_page_mock_selftests(void)
mkwrite_device_info(dev_priv)->ppgtt_type = INTEL_PPGTT_FULL;
mkwrite_device_info(dev_priv)->ppgtt_size = 48;
- ppgtt = i915_ppgtt_create(&dev_priv->gt);
+ ppgtt = i915_ppgtt_create(&dev_priv->gt, 0);
if (IS_ERR(ppgtt)) {
err = PTR_ERR(ppgtt);
goto out_unlock;
diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
index 1aee5e6b1b23..890191f286e3 100644
--- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
@@ -429,7 +429,7 @@ struct i915_ppgtt *gen6_ppgtt_create(struct intel_gt *gt)
mutex_init(&ppgtt->flush);
mutex_init(&ppgtt->pin_mutex);
- ppgtt_init(&ppgtt->base, gt);
+ ppgtt_init(&ppgtt->base, gt, 0);
ppgtt->base.vm.pd_shift = ilog2(SZ_4K * SZ_4K / sizeof(gen6_pte_t));
ppgtt->base.vm.top = 1;
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 6a5af995f5b1..037a9a6e4889 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -753,7 +753,8 @@ gen8_alloc_top_pd(struct i915_address_space *vm)
* space.
*
*/
-struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
+struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
+ unsigned long lmem_pt_obj_flags)
{
struct i915_ppgtt *ppgtt;
int err;
@@ -762,7 +763,7 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
if (!ppgtt)
return ERR_PTR(-ENOMEM);
- ppgtt_init(ppgtt, gt);
+ ppgtt_init(ppgtt, gt, lmem_pt_obj_flags);
ppgtt->vm.top = i915_vm_is_4lvl(&ppgtt->vm) ? 3 : 2;
ppgtt->vm.pd_shift = ilog2(SZ_4K * SZ_4K / sizeof(gen8_pte_t));
diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.h b/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
index b9028c2ad3c7..f541d19264b4 100644
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
@@ -12,7 +12,9 @@ struct i915_address_space;
struct intel_gt;
enum i915_cache_level;
-struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt);
+struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
+ unsigned long lmem_pt_obj_flags);
+
u64 gen8_ggtt_pte_encode(dma_addr_t addr,
enum i915_cache_level level,
u32 flags);
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 8d71f67926f1..06576fc1310e 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -644,7 +644,7 @@ static int init_aliasing_ppgtt(struct i915_ggtt *ggtt)
struct i915_ppgtt *ppgtt;
int err;
- ppgtt = i915_ppgtt_create(ggtt->vm.gt);
+ ppgtt = i915_ppgtt_create(ggtt->vm.gt, 0);
if (IS_ERR(ppgtt))
return PTR_ERR(ppgtt);
@@ -909,6 +909,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
size = gen8_get_total_gtt_size(snb_gmch_ctl);
ggtt->vm.alloc_pt_dma = alloc_pt_dma;
+ ggtt->vm.lmem_pt_obj_flags = I915_BO_ALLOC_PM_EARLY;
ggtt->vm.total = (size / sizeof(gen8_pte_t)) * I915_GTT_PAGE_SIZE;
ggtt->vm.cleanup = gen6_gmch_remove;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 5753c5943ed9..4037c3778225 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -481,7 +481,7 @@ static void intel_gt_fini_scratch(struct intel_gt *gt)
static struct i915_address_space *kernel_vm(struct intel_gt *gt)
{
if (INTEL_PPGTT(gt->i915) > INTEL_PPGTT_ALIASING)
- return &i915_ppgtt_create(gt)->vm;
+ return &i915_ppgtt_create(gt, I915_BO_ALLOC_PM_EARLY)->vm;
else
return i915_vm_get(>->ggtt->vm);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index a0c2b952aa57..67d14afa6623 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -28,7 +28,8 @@ struct drm_i915_gem_object *alloc_pt_lmem(struct i915_address_space *vm, int sz)
* used the passed in size for the page size, which should ensure it
* also has the same alignment.
*/
- obj = __i915_gem_object_create_lmem_with_ps(vm->i915, sz, sz, 0);
+ obj = __i915_gem_object_create_lmem_with_ps(vm->i915, sz, sz,
+ vm->lmem_pt_obj_flags);
/*
* Ensure all paging structures for this vm share the same dma-resv
* object underneath, with the idea that one object_lock() will lock
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
index 5b539bd7645d..bc6750263359 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -260,6 +260,9 @@ struct i915_address_space {
u8 pd_shift;
u8 scratch_order;
+ /* Flags used when creating page-table objects for this vm */
+ unsigned long lmem_pt_obj_flags;
+
struct drm_i915_gem_object *
(*alloc_pt_dma)(struct i915_address_space *vm, int sz);
@@ -519,7 +522,8 @@ i915_page_dir_dma_addr(const struct i915_ppgtt *ppgtt, const unsigned int n)
return __px_dma(pt ? px_base(pt) : ppgtt->vm.scratch[ppgtt->vm.top]);
}
-void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt);
+void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt,
+ unsigned long lmem_pt_obj_flags);
int i915_ggtt_probe_hw(struct drm_i915_private *i915);
int i915_ggtt_init_hw(struct drm_i915_private *i915);
@@ -537,7 +541,8 @@ static inline bool i915_ggtt_has_aperture(const struct i915_ggtt *ggtt)
int i915_ppgtt_init_hw(struct intel_gt *gt);
-struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt);
+struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt,
+ unsigned long lmem_pt_obj_flags);
void i915_ggtt_suspend(struct i915_ggtt *gtt);
void i915_ggtt_resume(struct i915_ggtt *ggtt);
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
index 1dac21aa7e5c..afb1cce9a352 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -78,7 +78,7 @@ static struct i915_address_space *migrate_vm(struct intel_gt *gt)
* TODO: Add support for huge LMEM PTEs
*/
- vm = i915_ppgtt_create(gt);
+ vm = i915_ppgtt_create(gt, I915_BO_ALLOC_PM_EARLY);
if (IS_ERR(vm))
return ERR_CAST(vm);
diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
index 886060f7e6fc..4396bfd630d8 100644
--- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
@@ -155,19 +155,20 @@ int i915_ppgtt_init_hw(struct intel_gt *gt)
}
static struct i915_ppgtt *
-__ppgtt_create(struct intel_gt *gt)
+__ppgtt_create(struct intel_gt *gt, unsigned long lmem_pt_obj_flags)
{
if (GRAPHICS_VER(gt->i915) < 8)
return gen6_ppgtt_create(gt);
else
- return gen8_ppgtt_create(gt);
+ return gen8_ppgtt_create(gt, lmem_pt_obj_flags);
}
-struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt)
+struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt,
+ unsigned long lmem_pt_obj_flags)
{
struct i915_ppgtt *ppgtt;
- ppgtt = __ppgtt_create(gt);
+ ppgtt = __ppgtt_create(gt, lmem_pt_obj_flags);
if (IS_ERR(ppgtt))
return ppgtt;
@@ -298,7 +299,8 @@ int ppgtt_set_pages(struct i915_vma *vma)
return 0;
}
-void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt)
+void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt,
+ unsigned long lmem_pt_obj_flags)
{
struct drm_i915_private *i915 = gt->i915;
@@ -306,6 +308,7 @@ void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt)
ppgtt->vm.i915 = i915;
ppgtt->vm.dma = i915->drm.dev;
ppgtt->vm.total = BIT_ULL(INTEL_INFO(i915)->ppgtt_size);
+ ppgtt->vm.lmem_pt_obj_flags = lmem_pt_obj_flags;
dma_resv_init(&ppgtt->vm._resv);
i915_address_space_init(&ppgtt->vm, VM_CLASS_PPGTT);
diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
index 7e6fdabac599..7e2d99dd012d 100644
--- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
+++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
@@ -1596,7 +1596,7 @@ static int igt_reset_evict_ppgtt(void *arg)
if (INTEL_PPGTT(gt->i915) < INTEL_PPGTT_FULL)
return 0;
- ppgtt = i915_ppgtt_create(gt);
+ ppgtt = i915_ppgtt_create(gt, 0);
if (IS_ERR(ppgtt))
return PTR_ERR(ppgtt);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 8ffb689066f6..8f8182bf7c11 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -651,7 +651,8 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
if (HAS_LMEM(gt->i915))
obj = i915_gem_object_create_lmem(gt->i915, size,
I915_BO_ALLOC_CPU_CLEAR |
- I915_BO_ALLOC_CONTIGUOUS);
+ I915_BO_ALLOC_CONTIGUOUS |
+ I915_BO_ALLOC_PM_EARLY);
else
obj = i915_gem_object_create_shmem(gt->i915, size);
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index a685d563df72..3aa87be4f2e4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
@@ -372,10 +372,13 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
if (uc_fw->type == INTEL_UC_FW_TYPE_GUC)
uc_fw->private_data_size = css->private_data_size;
- if (HAS_LMEM(i915))
+ if (HAS_LMEM(i915)) {
obj = i915_gem_object_create_lmem_from_data(i915, fw->data, fw->size);
- else
+ if (!IS_ERR(obj))
+ obj->flags |= I915_BO_ALLOC_PM_EARLY;
+ } else {
obj = i915_gem_object_create_shmem_from_data(i915, fw->data, fw->size);
+ }
if (IS_ERR(obj)) {
err = PTR_ERR(obj);
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
index b56a8e37a3cd..0d18e13e3468 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -1386,7 +1386,7 @@ int intel_vgpu_setup_submission(struct intel_vgpu *vgpu)
enum intel_engine_id i;
int ret;
- ppgtt = i915_ppgtt_create(&i915->gt);
+ ppgtt = i915_ppgtt_create(&i915->gt, I915_BO_ALLOC_PM_EARLY);
if (IS_ERR(ppgtt))
return PTR_ERR(ppgtt);
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index 2d60a5a5b065..46f4236039a9 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -155,7 +155,7 @@ static int igt_ppgtt_alloc(void *arg)
if (!HAS_PPGTT(dev_priv))
return 0;
- ppgtt = i915_ppgtt_create(&dev_priv->gt);
+ ppgtt = i915_ppgtt_create(&dev_priv->gt, 0);
if (IS_ERR(ppgtt))
return PTR_ERR(ppgtt);
@@ -1053,7 +1053,7 @@ static int exercise_ppgtt(struct drm_i915_private *dev_priv,
if (IS_ERR(file))
return PTR_ERR(file);
- ppgtt = i915_ppgtt_create(&dev_priv->gt);
+ ppgtt = i915_ppgtt_create(&dev_priv->gt, 0);
if (IS_ERR(ppgtt)) {
err = PTR_ERR(ppgtt);
goto out_free;
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* Re: [PATCH v6 7/9] drm/i915: Reduce the number of objects subject to memcpy recover
2021-09-22 6:25 ` [Intel-gfx] " Thomas Hellström
@ 2021-09-23 9:44 ` Matthew Auld
-1 siblings, 0 replies; 39+ messages in thread
From: Matthew Auld @ 2021-09-23 9:44 UTC (permalink / raw)
To: Thomas Hellström, intel-gfx, dri-devel
Cc: maarten.lankhorst, Matthew Brost
On 22/09/2021 07:25, Thomas Hellström wrote:
> We really only need memcpy restore for objects that affect the
> operability of the migrate context. That is, primarily the page-table
> objects of the migrate VM.
>
> Add an object flag, I915_BO_ALLOC_PM_EARLY for objects that need early
> restores using memcpy and a way to assign LMEM page-table object flags
> to be used by the vms.
>
> Restore objects without this flag with the gpu blitter and only objects
> carrying the flag using TTM memcpy.
>
> Initially mark the migrate, gt, gtt and vgpu vms to use this flag, and
> defer for a later audit which vms actually need it. Most importantly, user-
> allocated vms with pinned page-table objects can be restored using the
> blitter.
>
> Performance-wise memcpy restore is probably as fast as gpu restore if not
> faster, but using gpu restore will help tackling future restrictions in
> mappable LMEM size.
>
> v4:
> - Don't mark the aliasing ppgtt page table flags for early resume, but
> rather the ggtt page table flags as intended. (Matthew Auld)
> - The check for user buffer objects during early resume is pointless, since
> they are never marked I915_BO_ALLOC_PM_EARLY. (Matthew Auld)
> v5:
> - Mark GuC LMEM objects with I915_BO_ALLOC_PM_EARLY to have them restored
> before we fire up the migrate context.
>
> Cc: Matthew Brost <matthew.brost@intel.com>
> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 4 ++--
> drivers/gpu/drm/i915/gem/i915_gem_object_types.h | 9 ++++++---
> drivers/gpu/drm/i915/gem/i915_gem_pm.c | 6 +++++-
> drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c | 5 +++--
> drivers/gpu/drm/i915/gem/selftests/huge_pages.c | 2 +-
> drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 2 +-
> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 5 +++--
> drivers/gpu/drm/i915/gt/gen8_ppgtt.h | 4 +++-
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 3 ++-
> drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_gtt.c | 3 ++-
> drivers/gpu/drm/i915/gt/intel_gtt.h | 9 +++++++--
> drivers/gpu/drm/i915/gt/intel_migrate.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_ppgtt.c | 13 ++++++++-----
> drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 2 +-
> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 3 ++-
> drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 7 +++++--
> drivers/gpu/drm/i915/gvt/scheduler.c | 2 +-
> drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 4 ++--
> 19 files changed, 56 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index c2ab0e22db0a..8208fd5b72c3 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -1287,7 +1287,7 @@ i915_gem_create_context(struct drm_i915_private *i915,
> } else if (HAS_FULL_PPGTT(i915)) {
> struct i915_ppgtt *ppgtt;
>
> - ppgtt = i915_ppgtt_create(&i915->gt);
> + ppgtt = i915_ppgtt_create(&i915->gt, 0);
> if (IS_ERR(ppgtt)) {
> drm_dbg(&i915->drm, "PPGTT setup failed (%ld)\n",
> PTR_ERR(ppgtt));
> @@ -1465,7 +1465,7 @@ int i915_gem_vm_create_ioctl(struct drm_device *dev, void *data,
> if (args->flags)
> return -EINVAL;
>
> - ppgtt = i915_ppgtt_create(&i915->gt);
> + ppgtt = i915_ppgtt_create(&i915->gt, 0);
> if (IS_ERR(ppgtt))
> return PTR_ERR(ppgtt);
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> index 118691ce81d7..fa2ba9e2a4d0 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> @@ -294,13 +294,16 @@ struct drm_i915_gem_object {
> #define I915_BO_ALLOC_USER BIT(3)
> /* Object is allowed to lose its contents on suspend / resume, even if pinned */
> #define I915_BO_ALLOC_PM_VOLATILE BIT(4)
> +/* Object needs to be restored early using memcpy during resume */
> +#define I915_BO_ALLOC_PM_EARLY BIT(5)
> #define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
> I915_BO_ALLOC_VOLATILE | \
> I915_BO_ALLOC_CPU_CLEAR | \
> I915_BO_ALLOC_USER | \
> - I915_BO_ALLOC_PM_VOLATILE)
> -#define I915_BO_READONLY BIT(5)
> -#define I915_TILING_QUIRK_BIT 6 /* unknown swizzling; do not release! */
> + I915_BO_ALLOC_PM_VOLATILE | \
> + I915_BO_ALLOC_PM_EARLY)
> +#define I915_BO_READONLY BIT(6)
> +#define I915_TILING_QUIRK_BIT 7 /* unknown swizzling; do not release! */
>
> /**
> * @mem_flags - Mutable placement-related flags
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
> index 12b37b4c1192..726b40e1fbb0 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
> @@ -97,8 +97,12 @@ int i915_gem_backup_suspend(struct drm_i915_private *i915)
> * More objects may have become unpinned as requests were
> * retired. Now try to evict again. The gt may be wedged here
> * in which case we automatically fall back to memcpy.
> + * We allow also backing up pinned objects that have not been
> + * marked for early recover, and that may contain, for example,
> + * page-tables for the migrate context.
> */
> - ret = lmem_suspend(i915, I915_TTM_BACKUP_ALLOW_GPU);
> + ret = lmem_suspend(i915, I915_TTM_BACKUP_ALLOW_GPU |
> + I915_TTM_BACKUP_PINNED);
> if (ret)
> goto out_recover;
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
> index 03a00d193f40..3b6d14b5c604 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
> @@ -57,7 +57,8 @@ static int i915_ttm_backup(struct i915_gem_apply_to_region *apply,
> if (pm_apply->allow_gpu && i915_gem_object_evictable(obj))
> return ttm_bo_validate(bo, i915_ttm_sys_placement(), &ctx);
>
> - if (!pm_apply->backup_pinned)
> + if (!pm_apply->backup_pinned ||
> + (pm_apply->allow_gpu && (obj->flags & I915_BO_ALLOC_PM_EARLY)))
> return 0;
>
> if (obj->flags & I915_BO_ALLOC_PM_VOLATILE)
> @@ -155,7 +156,7 @@ static int i915_ttm_restore(struct i915_gem_apply_to_region *apply,
> if (!backup)
> return 0;
>
> - if (!pm_apply->allow_gpu && (obj->flags & I915_BO_ALLOC_USER))
> + if (!pm_apply->allow_gpu && !(obj->flags & I915_BO_ALLOC_PM_EARLY))
> return 0;
>
> err = i915_gem_object_lock(backup, apply->ww);
> diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> index 0827634c842c..77d84a9e8789 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> @@ -1645,7 +1645,7 @@ int i915_gem_huge_page_mock_selftests(void)
> mkwrite_device_info(dev_priv)->ppgtt_type = INTEL_PPGTT_FULL;
> mkwrite_device_info(dev_priv)->ppgtt_size = 48;
>
> - ppgtt = i915_ppgtt_create(&dev_priv->gt);
> + ppgtt = i915_ppgtt_create(&dev_priv->gt, 0);
> if (IS_ERR(ppgtt)) {
> err = PTR_ERR(ppgtt);
> goto out_unlock;
> diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
> index 1aee5e6b1b23..890191f286e3 100644
> --- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
> @@ -429,7 +429,7 @@ struct i915_ppgtt *gen6_ppgtt_create(struct intel_gt *gt)
> mutex_init(&ppgtt->flush);
> mutex_init(&ppgtt->pin_mutex);
>
> - ppgtt_init(&ppgtt->base, gt);
> + ppgtt_init(&ppgtt->base, gt, 0);
> ppgtt->base.vm.pd_shift = ilog2(SZ_4K * SZ_4K / sizeof(gen6_pte_t));
> ppgtt->base.vm.top = 1;
>
> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> index 6a5af995f5b1..037a9a6e4889 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> @@ -753,7 +753,8 @@ gen8_alloc_top_pd(struct i915_address_space *vm)
> * space.
> *
> */
> -struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
> +struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
> + unsigned long lmem_pt_obj_flags)
> {
> struct i915_ppgtt *ppgtt;
> int err;
> @@ -762,7 +763,7 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
> if (!ppgtt)
> return ERR_PTR(-ENOMEM);
>
> - ppgtt_init(ppgtt, gt);
> + ppgtt_init(ppgtt, gt, lmem_pt_obj_flags);
> ppgtt->vm.top = i915_vm_is_4lvl(&ppgtt->vm) ? 3 : 2;
> ppgtt->vm.pd_shift = ilog2(SZ_4K * SZ_4K / sizeof(gen8_pte_t));
>
> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.h b/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
> index b9028c2ad3c7..f541d19264b4 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
> @@ -12,7 +12,9 @@ struct i915_address_space;
> struct intel_gt;
> enum i915_cache_level;
>
> -struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt);
> +struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
> + unsigned long lmem_pt_obj_flags);
> +
> u64 gen8_ggtt_pte_encode(dma_addr_t addr,
> enum i915_cache_level level,
> u32 flags);
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> index 8d71f67926f1..06576fc1310e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> @@ -644,7 +644,7 @@ static int init_aliasing_ppgtt(struct i915_ggtt *ggtt)
> struct i915_ppgtt *ppgtt;
> int err;
>
> - ppgtt = i915_ppgtt_create(ggtt->vm.gt);
> + ppgtt = i915_ppgtt_create(ggtt->vm.gt, 0);
> if (IS_ERR(ppgtt))
> return PTR_ERR(ppgtt);
>
> @@ -909,6 +909,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
> size = gen8_get_total_gtt_size(snb_gmch_ctl);
>
> ggtt->vm.alloc_pt_dma = alloc_pt_dma;
> + ggtt->vm.lmem_pt_obj_flags = I915_BO_ALLOC_PM_EARLY;
The scratch page is still in system memory for the ggtt, so I guess this
is not needed? Although maybe that will change, so probably good to keep?
>
> ggtt->vm.total = (size / sizeof(gen8_pte_t)) * I915_GTT_PAGE_SIZE;
> ggtt->vm.cleanup = gen6_gmch_remove;
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 5753c5943ed9..4037c3778225 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -481,7 +481,7 @@ static void intel_gt_fini_scratch(struct intel_gt *gt)
> static struct i915_address_space *kernel_vm(struct intel_gt *gt)
> {
> if (INTEL_PPGTT(gt->i915) > INTEL_PPGTT_ALIASING)
> - return &i915_ppgtt_create(gt)->vm;
> + return &i915_ppgtt_create(gt, I915_BO_ALLOC_PM_EARLY)->vm;
> else
> return i915_vm_get(>->ggtt->vm);
> }
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
> index a0c2b952aa57..67d14afa6623 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
> @@ -28,7 +28,8 @@ struct drm_i915_gem_object *alloc_pt_lmem(struct i915_address_space *vm, int sz)
> * used the passed in size for the page size, which should ensure it
> * also has the same alignment.
> */
> - obj = __i915_gem_object_create_lmem_with_ps(vm->i915, sz, sz, 0);
> + obj = __i915_gem_object_create_lmem_with_ps(vm->i915, sz, sz,
> + vm->lmem_pt_obj_flags);
> /*
> * Ensure all paging structures for this vm share the same dma-resv
> * object underneath, with the idea that one object_lock() will lock
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
> index 5b539bd7645d..bc6750263359 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
> @@ -260,6 +260,9 @@ struct i915_address_space {
> u8 pd_shift;
> u8 scratch_order;
>
> + /* Flags used when creating page-table objects for this vm */
> + unsigned long lmem_pt_obj_flags;
> +
> struct drm_i915_gem_object *
> (*alloc_pt_dma)(struct i915_address_space *vm, int sz);
>
> @@ -519,7 +522,8 @@ i915_page_dir_dma_addr(const struct i915_ppgtt *ppgtt, const unsigned int n)
> return __px_dma(pt ? px_base(pt) : ppgtt->vm.scratch[ppgtt->vm.top]);
> }
>
> -void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt);
> +void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt,
> + unsigned long lmem_pt_obj_flags);
>
> int i915_ggtt_probe_hw(struct drm_i915_private *i915);
> int i915_ggtt_init_hw(struct drm_i915_private *i915);
> @@ -537,7 +541,8 @@ static inline bool i915_ggtt_has_aperture(const struct i915_ggtt *ggtt)
>
> int i915_ppgtt_init_hw(struct intel_gt *gt);
>
> -struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt);
> +struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt,
> + unsigned long lmem_pt_obj_flags);
>
> void i915_ggtt_suspend(struct i915_ggtt *gtt);
> void i915_ggtt_resume(struct i915_ggtt *ggtt);
> diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
> index 1dac21aa7e5c..afb1cce9a352 100644
> --- a/drivers/gpu/drm/i915/gt/intel_migrate.c
> +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
> @@ -78,7 +78,7 @@ static struct i915_address_space *migrate_vm(struct intel_gt *gt)
> * TODO: Add support for huge LMEM PTEs
> */
>
> - vm = i915_ppgtt_create(gt);
> + vm = i915_ppgtt_create(gt, I915_BO_ALLOC_PM_EARLY);
> if (IS_ERR(vm))
> return ERR_CAST(vm);
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> index 886060f7e6fc..4396bfd630d8 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> @@ -155,19 +155,20 @@ int i915_ppgtt_init_hw(struct intel_gt *gt)
> }
>
> static struct i915_ppgtt *
> -__ppgtt_create(struct intel_gt *gt)
> +__ppgtt_create(struct intel_gt *gt, unsigned long lmem_pt_obj_flags)
> {
> if (GRAPHICS_VER(gt->i915) < 8)
> return gen6_ppgtt_create(gt);
> else
> - return gen8_ppgtt_create(gt);
> + return gen8_ppgtt_create(gt, lmem_pt_obj_flags);
> }
>
> -struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt)
> +struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt,
> + unsigned long lmem_pt_obj_flags)
> {
> struct i915_ppgtt *ppgtt;
>
> - ppgtt = __ppgtt_create(gt);
> + ppgtt = __ppgtt_create(gt, lmem_pt_obj_flags);
> if (IS_ERR(ppgtt))
> return ppgtt;
>
> @@ -298,7 +299,8 @@ int ppgtt_set_pages(struct i915_vma *vma)
> return 0;
> }
>
> -void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt)
> +void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt,
> + unsigned long lmem_pt_obj_flags)
> {
> struct drm_i915_private *i915 = gt->i915;
>
> @@ -306,6 +308,7 @@ void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt)
> ppgtt->vm.i915 = i915;
> ppgtt->vm.dma = i915->drm.dev;
> ppgtt->vm.total = BIT_ULL(INTEL_INFO(i915)->ppgtt_size);
> + ppgtt->vm.lmem_pt_obj_flags = lmem_pt_obj_flags;
>
> dma_resv_init(&ppgtt->vm._resv);
> i915_address_space_init(&ppgtt->vm, VM_CLASS_PPGTT);
> diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> index 7e6fdabac599..7e2d99dd012d 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> @@ -1596,7 +1596,7 @@ static int igt_reset_evict_ppgtt(void *arg)
> if (INTEL_PPGTT(gt->i915) < INTEL_PPGTT_FULL)
> return 0;
>
> - ppgtt = i915_ppgtt_create(gt);
> + ppgtt = i915_ppgtt_create(gt, 0);
> if (IS_ERR(ppgtt))
> return PTR_ERR(ppgtt);
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index 8ffb689066f6..8f8182bf7c11 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -651,7 +651,8 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
> if (HAS_LMEM(gt->i915))
> obj = i915_gem_object_create_lmem(gt->i915, size,
> I915_BO_ALLOC_CPU_CLEAR |
> - I915_BO_ALLOC_CONTIGUOUS);
> + I915_BO_ALLOC_CONTIGUOUS |
> + I915_BO_ALLOC_PM_EARLY);
> else
> obj = i915_gem_object_create_shmem(gt->i915, size);
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> index a685d563df72..3aa87be4f2e4 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> @@ -372,10 +372,13 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
> if (uc_fw->type == INTEL_UC_FW_TYPE_GUC)
> uc_fw->private_data_size = css->private_data_size;
>
> - if (HAS_LMEM(i915))
> + if (HAS_LMEM(i915)) {
> obj = i915_gem_object_create_lmem_from_data(i915, fw->data, fw->size);
> - else
> + if (!IS_ERR(obj))
> + obj->flags |= I915_BO_ALLOC_PM_EARLY;
Another reason why lmem_from_data should maybe just have a flags param,
since it also forcing ALLOC_CONTIG, which should really be up to the
caller? Can be improved as a follow up though. R-b still stands.
> + } else {
> obj = i915_gem_object_create_shmem_from_data(i915, fw->data, fw->size);
> + }
>
> if (IS_ERR(obj)) {
> err = PTR_ERR(obj);
> diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
> index b56a8e37a3cd..0d18e13e3468 100644
> --- a/drivers/gpu/drm/i915/gvt/scheduler.c
> +++ b/drivers/gpu/drm/i915/gvt/scheduler.c
> @@ -1386,7 +1386,7 @@ int intel_vgpu_setup_submission(struct intel_vgpu *vgpu)
> enum intel_engine_id i;
> int ret;
>
> - ppgtt = i915_ppgtt_create(&i915->gt);
> + ppgtt = i915_ppgtt_create(&i915->gt, I915_BO_ALLOC_PM_EARLY);
> if (IS_ERR(ppgtt))
> return PTR_ERR(ppgtt);
>
> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> index 2d60a5a5b065..46f4236039a9 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> @@ -155,7 +155,7 @@ static int igt_ppgtt_alloc(void *arg)
> if (!HAS_PPGTT(dev_priv))
> return 0;
>
> - ppgtt = i915_ppgtt_create(&dev_priv->gt);
> + ppgtt = i915_ppgtt_create(&dev_priv->gt, 0);
> if (IS_ERR(ppgtt))
> return PTR_ERR(ppgtt);
>
> @@ -1053,7 +1053,7 @@ static int exercise_ppgtt(struct drm_i915_private *dev_priv,
> if (IS_ERR(file))
> return PTR_ERR(file);
>
> - ppgtt = i915_ppgtt_create(&dev_priv->gt);
> + ppgtt = i915_ppgtt_create(&dev_priv->gt, 0);
> if (IS_ERR(ppgtt)) {
> err = PTR_ERR(ppgtt);
> goto out_free;
>
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [Intel-gfx] [PATCH v6 7/9] drm/i915: Reduce the number of objects subject to memcpy recover
@ 2021-09-23 9:44 ` Matthew Auld
0 siblings, 0 replies; 39+ messages in thread
From: Matthew Auld @ 2021-09-23 9:44 UTC (permalink / raw)
To: Thomas Hellström, intel-gfx, dri-devel
Cc: maarten.lankhorst, Matthew Brost
On 22/09/2021 07:25, Thomas Hellström wrote:
> We really only need memcpy restore for objects that affect the
> operability of the migrate context. That is, primarily the page-table
> objects of the migrate VM.
>
> Add an object flag, I915_BO_ALLOC_PM_EARLY for objects that need early
> restores using memcpy and a way to assign LMEM page-table object flags
> to be used by the vms.
>
> Restore objects without this flag with the gpu blitter and only objects
> carrying the flag using TTM memcpy.
>
> Initially mark the migrate, gt, gtt and vgpu vms to use this flag, and
> defer for a later audit which vms actually need it. Most importantly, user-
> allocated vms with pinned page-table objects can be restored using the
> blitter.
>
> Performance-wise memcpy restore is probably as fast as gpu restore if not
> faster, but using gpu restore will help tackling future restrictions in
> mappable LMEM size.
>
> v4:
> - Don't mark the aliasing ppgtt page table flags for early resume, but
> rather the ggtt page table flags as intended. (Matthew Auld)
> - The check for user buffer objects during early resume is pointless, since
> they are never marked I915_BO_ALLOC_PM_EARLY. (Matthew Auld)
> v5:
> - Mark GuC LMEM objects with I915_BO_ALLOC_PM_EARLY to have them restored
> before we fire up the migrate context.
>
> Cc: Matthew Brost <matthew.brost@intel.com>
> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_context.c | 4 ++--
> drivers/gpu/drm/i915/gem/i915_gem_object_types.h | 9 ++++++---
> drivers/gpu/drm/i915/gem/i915_gem_pm.c | 6 +++++-
> drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c | 5 +++--
> drivers/gpu/drm/i915/gem/selftests/huge_pages.c | 2 +-
> drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 2 +-
> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 5 +++--
> drivers/gpu/drm/i915/gt/gen8_ppgtt.h | 4 +++-
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 3 ++-
> drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_gtt.c | 3 ++-
> drivers/gpu/drm/i915/gt/intel_gtt.h | 9 +++++++--
> drivers/gpu/drm/i915/gt/intel_migrate.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_ppgtt.c | 13 ++++++++-----
> drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 2 +-
> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 3 ++-
> drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 7 +++++--
> drivers/gpu/drm/i915/gvt/scheduler.c | 2 +-
> drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 4 ++--
> 19 files changed, 56 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index c2ab0e22db0a..8208fd5b72c3 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -1287,7 +1287,7 @@ i915_gem_create_context(struct drm_i915_private *i915,
> } else if (HAS_FULL_PPGTT(i915)) {
> struct i915_ppgtt *ppgtt;
>
> - ppgtt = i915_ppgtt_create(&i915->gt);
> + ppgtt = i915_ppgtt_create(&i915->gt, 0);
> if (IS_ERR(ppgtt)) {
> drm_dbg(&i915->drm, "PPGTT setup failed (%ld)\n",
> PTR_ERR(ppgtt));
> @@ -1465,7 +1465,7 @@ int i915_gem_vm_create_ioctl(struct drm_device *dev, void *data,
> if (args->flags)
> return -EINVAL;
>
> - ppgtt = i915_ppgtt_create(&i915->gt);
> + ppgtt = i915_ppgtt_create(&i915->gt, 0);
> if (IS_ERR(ppgtt))
> return PTR_ERR(ppgtt);
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> index 118691ce81d7..fa2ba9e2a4d0 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
> @@ -294,13 +294,16 @@ struct drm_i915_gem_object {
> #define I915_BO_ALLOC_USER BIT(3)
> /* Object is allowed to lose its contents on suspend / resume, even if pinned */
> #define I915_BO_ALLOC_PM_VOLATILE BIT(4)
> +/* Object needs to be restored early using memcpy during resume */
> +#define I915_BO_ALLOC_PM_EARLY BIT(5)
> #define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
> I915_BO_ALLOC_VOLATILE | \
> I915_BO_ALLOC_CPU_CLEAR | \
> I915_BO_ALLOC_USER | \
> - I915_BO_ALLOC_PM_VOLATILE)
> -#define I915_BO_READONLY BIT(5)
> -#define I915_TILING_QUIRK_BIT 6 /* unknown swizzling; do not release! */
> + I915_BO_ALLOC_PM_VOLATILE | \
> + I915_BO_ALLOC_PM_EARLY)
> +#define I915_BO_READONLY BIT(6)
> +#define I915_TILING_QUIRK_BIT 7 /* unknown swizzling; do not release! */
>
> /**
> * @mem_flags - Mutable placement-related flags
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
> index 12b37b4c1192..726b40e1fbb0 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
> @@ -97,8 +97,12 @@ int i915_gem_backup_suspend(struct drm_i915_private *i915)
> * More objects may have become unpinned as requests were
> * retired. Now try to evict again. The gt may be wedged here
> * in which case we automatically fall back to memcpy.
> + * We allow also backing up pinned objects that have not been
> + * marked for early recover, and that may contain, for example,
> + * page-tables for the migrate context.
> */
> - ret = lmem_suspend(i915, I915_TTM_BACKUP_ALLOW_GPU);
> + ret = lmem_suspend(i915, I915_TTM_BACKUP_ALLOW_GPU |
> + I915_TTM_BACKUP_PINNED);
> if (ret)
> goto out_recover;
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
> index 03a00d193f40..3b6d14b5c604 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
> @@ -57,7 +57,8 @@ static int i915_ttm_backup(struct i915_gem_apply_to_region *apply,
> if (pm_apply->allow_gpu && i915_gem_object_evictable(obj))
> return ttm_bo_validate(bo, i915_ttm_sys_placement(), &ctx);
>
> - if (!pm_apply->backup_pinned)
> + if (!pm_apply->backup_pinned ||
> + (pm_apply->allow_gpu && (obj->flags & I915_BO_ALLOC_PM_EARLY)))
> return 0;
>
> if (obj->flags & I915_BO_ALLOC_PM_VOLATILE)
> @@ -155,7 +156,7 @@ static int i915_ttm_restore(struct i915_gem_apply_to_region *apply,
> if (!backup)
> return 0;
>
> - if (!pm_apply->allow_gpu && (obj->flags & I915_BO_ALLOC_USER))
> + if (!pm_apply->allow_gpu && !(obj->flags & I915_BO_ALLOC_PM_EARLY))
> return 0;
>
> err = i915_gem_object_lock(backup, apply->ww);
> diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> index 0827634c842c..77d84a9e8789 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
> @@ -1645,7 +1645,7 @@ int i915_gem_huge_page_mock_selftests(void)
> mkwrite_device_info(dev_priv)->ppgtt_type = INTEL_PPGTT_FULL;
> mkwrite_device_info(dev_priv)->ppgtt_size = 48;
>
> - ppgtt = i915_ppgtt_create(&dev_priv->gt);
> + ppgtt = i915_ppgtt_create(&dev_priv->gt, 0);
> if (IS_ERR(ppgtt)) {
> err = PTR_ERR(ppgtt);
> goto out_unlock;
> diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
> index 1aee5e6b1b23..890191f286e3 100644
> --- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
> @@ -429,7 +429,7 @@ struct i915_ppgtt *gen6_ppgtt_create(struct intel_gt *gt)
> mutex_init(&ppgtt->flush);
> mutex_init(&ppgtt->pin_mutex);
>
> - ppgtt_init(&ppgtt->base, gt);
> + ppgtt_init(&ppgtt->base, gt, 0);
> ppgtt->base.vm.pd_shift = ilog2(SZ_4K * SZ_4K / sizeof(gen6_pte_t));
> ppgtt->base.vm.top = 1;
>
> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> index 6a5af995f5b1..037a9a6e4889 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
> @@ -753,7 +753,8 @@ gen8_alloc_top_pd(struct i915_address_space *vm)
> * space.
> *
> */
> -struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
> +struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
> + unsigned long lmem_pt_obj_flags)
> {
> struct i915_ppgtt *ppgtt;
> int err;
> @@ -762,7 +763,7 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
> if (!ppgtt)
> return ERR_PTR(-ENOMEM);
>
> - ppgtt_init(ppgtt, gt);
> + ppgtt_init(ppgtt, gt, lmem_pt_obj_flags);
> ppgtt->vm.top = i915_vm_is_4lvl(&ppgtt->vm) ? 3 : 2;
> ppgtt->vm.pd_shift = ilog2(SZ_4K * SZ_4K / sizeof(gen8_pte_t));
>
> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.h b/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
> index b9028c2ad3c7..f541d19264b4 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
> @@ -12,7 +12,9 @@ struct i915_address_space;
> struct intel_gt;
> enum i915_cache_level;
>
> -struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt);
> +struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
> + unsigned long lmem_pt_obj_flags);
> +
> u64 gen8_ggtt_pte_encode(dma_addr_t addr,
> enum i915_cache_level level,
> u32 flags);
> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> index 8d71f67926f1..06576fc1310e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
> @@ -644,7 +644,7 @@ static int init_aliasing_ppgtt(struct i915_ggtt *ggtt)
> struct i915_ppgtt *ppgtt;
> int err;
>
> - ppgtt = i915_ppgtt_create(ggtt->vm.gt);
> + ppgtt = i915_ppgtt_create(ggtt->vm.gt, 0);
> if (IS_ERR(ppgtt))
> return PTR_ERR(ppgtt);
>
> @@ -909,6 +909,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
> size = gen8_get_total_gtt_size(snb_gmch_ctl);
>
> ggtt->vm.alloc_pt_dma = alloc_pt_dma;
> + ggtt->vm.lmem_pt_obj_flags = I915_BO_ALLOC_PM_EARLY;
The scratch page is still in system memory for the ggtt, so I guess this
is not needed? Although maybe that will change, so probably good to keep?
>
> ggtt->vm.total = (size / sizeof(gen8_pte_t)) * I915_GTT_PAGE_SIZE;
> ggtt->vm.cleanup = gen6_gmch_remove;
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 5753c5943ed9..4037c3778225 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -481,7 +481,7 @@ static void intel_gt_fini_scratch(struct intel_gt *gt)
> static struct i915_address_space *kernel_vm(struct intel_gt *gt)
> {
> if (INTEL_PPGTT(gt->i915) > INTEL_PPGTT_ALIASING)
> - return &i915_ppgtt_create(gt)->vm;
> + return &i915_ppgtt_create(gt, I915_BO_ALLOC_PM_EARLY)->vm;
> else
> return i915_vm_get(>->ggtt->vm);
> }
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
> index a0c2b952aa57..67d14afa6623 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
> @@ -28,7 +28,8 @@ struct drm_i915_gem_object *alloc_pt_lmem(struct i915_address_space *vm, int sz)
> * used the passed in size for the page size, which should ensure it
> * also has the same alignment.
> */
> - obj = __i915_gem_object_create_lmem_with_ps(vm->i915, sz, sz, 0);
> + obj = __i915_gem_object_create_lmem_with_ps(vm->i915, sz, sz,
> + vm->lmem_pt_obj_flags);
> /*
> * Ensure all paging structures for this vm share the same dma-resv
> * object underneath, with the idea that one object_lock() will lock
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
> index 5b539bd7645d..bc6750263359 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
> @@ -260,6 +260,9 @@ struct i915_address_space {
> u8 pd_shift;
> u8 scratch_order;
>
> + /* Flags used when creating page-table objects for this vm */
> + unsigned long lmem_pt_obj_flags;
> +
> struct drm_i915_gem_object *
> (*alloc_pt_dma)(struct i915_address_space *vm, int sz);
>
> @@ -519,7 +522,8 @@ i915_page_dir_dma_addr(const struct i915_ppgtt *ppgtt, const unsigned int n)
> return __px_dma(pt ? px_base(pt) : ppgtt->vm.scratch[ppgtt->vm.top]);
> }
>
> -void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt);
> +void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt,
> + unsigned long lmem_pt_obj_flags);
>
> int i915_ggtt_probe_hw(struct drm_i915_private *i915);
> int i915_ggtt_init_hw(struct drm_i915_private *i915);
> @@ -537,7 +541,8 @@ static inline bool i915_ggtt_has_aperture(const struct i915_ggtt *ggtt)
>
> int i915_ppgtt_init_hw(struct intel_gt *gt);
>
> -struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt);
> +struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt,
> + unsigned long lmem_pt_obj_flags);
>
> void i915_ggtt_suspend(struct i915_ggtt *gtt);
> void i915_ggtt_resume(struct i915_ggtt *ggtt);
> diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
> index 1dac21aa7e5c..afb1cce9a352 100644
> --- a/drivers/gpu/drm/i915/gt/intel_migrate.c
> +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
> @@ -78,7 +78,7 @@ static struct i915_address_space *migrate_vm(struct intel_gt *gt)
> * TODO: Add support for huge LMEM PTEs
> */
>
> - vm = i915_ppgtt_create(gt);
> + vm = i915_ppgtt_create(gt, I915_BO_ALLOC_PM_EARLY);
> if (IS_ERR(vm))
> return ERR_CAST(vm);
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> index 886060f7e6fc..4396bfd630d8 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
> @@ -155,19 +155,20 @@ int i915_ppgtt_init_hw(struct intel_gt *gt)
> }
>
> static struct i915_ppgtt *
> -__ppgtt_create(struct intel_gt *gt)
> +__ppgtt_create(struct intel_gt *gt, unsigned long lmem_pt_obj_flags)
> {
> if (GRAPHICS_VER(gt->i915) < 8)
> return gen6_ppgtt_create(gt);
> else
> - return gen8_ppgtt_create(gt);
> + return gen8_ppgtt_create(gt, lmem_pt_obj_flags);
> }
>
> -struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt)
> +struct i915_ppgtt *i915_ppgtt_create(struct intel_gt *gt,
> + unsigned long lmem_pt_obj_flags)
> {
> struct i915_ppgtt *ppgtt;
>
> - ppgtt = __ppgtt_create(gt);
> + ppgtt = __ppgtt_create(gt, lmem_pt_obj_flags);
> if (IS_ERR(ppgtt))
> return ppgtt;
>
> @@ -298,7 +299,8 @@ int ppgtt_set_pages(struct i915_vma *vma)
> return 0;
> }
>
> -void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt)
> +void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt,
> + unsigned long lmem_pt_obj_flags)
> {
> struct drm_i915_private *i915 = gt->i915;
>
> @@ -306,6 +308,7 @@ void ppgtt_init(struct i915_ppgtt *ppgtt, struct intel_gt *gt)
> ppgtt->vm.i915 = i915;
> ppgtt->vm.dma = i915->drm.dev;
> ppgtt->vm.total = BIT_ULL(INTEL_INFO(i915)->ppgtt_size);
> + ppgtt->vm.lmem_pt_obj_flags = lmem_pt_obj_flags;
>
> dma_resv_init(&ppgtt->vm._resv);
> i915_address_space_init(&ppgtt->vm, VM_CLASS_PPGTT);
> diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> index 7e6fdabac599..7e2d99dd012d 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_hangcheck.c
> @@ -1596,7 +1596,7 @@ static int igt_reset_evict_ppgtt(void *arg)
> if (INTEL_PPGTT(gt->i915) < INTEL_PPGTT_FULL)
> return 0;
>
> - ppgtt = i915_ppgtt_create(gt);
> + ppgtt = i915_ppgtt_create(gt, 0);
> if (IS_ERR(ppgtt))
> return PTR_ERR(ppgtt);
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index 8ffb689066f6..8f8182bf7c11 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -651,7 +651,8 @@ struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
> if (HAS_LMEM(gt->i915))
> obj = i915_gem_object_create_lmem(gt->i915, size,
> I915_BO_ALLOC_CPU_CLEAR |
> - I915_BO_ALLOC_CONTIGUOUS);
> + I915_BO_ALLOC_CONTIGUOUS |
> + I915_BO_ALLOC_PM_EARLY);
> else
> obj = i915_gem_object_create_shmem(gt->i915, size);
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> index a685d563df72..3aa87be4f2e4 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> @@ -372,10 +372,13 @@ int intel_uc_fw_fetch(struct intel_uc_fw *uc_fw)
> if (uc_fw->type == INTEL_UC_FW_TYPE_GUC)
> uc_fw->private_data_size = css->private_data_size;
>
> - if (HAS_LMEM(i915))
> + if (HAS_LMEM(i915)) {
> obj = i915_gem_object_create_lmem_from_data(i915, fw->data, fw->size);
> - else
> + if (!IS_ERR(obj))
> + obj->flags |= I915_BO_ALLOC_PM_EARLY;
Another reason why lmem_from_data should maybe just have a flags param,
since it also forcing ALLOC_CONTIG, which should really be up to the
caller? Can be improved as a follow up though. R-b still stands.
> + } else {
> obj = i915_gem_object_create_shmem_from_data(i915, fw->data, fw->size);
> + }
>
> if (IS_ERR(obj)) {
> err = PTR_ERR(obj);
> diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
> index b56a8e37a3cd..0d18e13e3468 100644
> --- a/drivers/gpu/drm/i915/gvt/scheduler.c
> +++ b/drivers/gpu/drm/i915/gvt/scheduler.c
> @@ -1386,7 +1386,7 @@ int intel_vgpu_setup_submission(struct intel_vgpu *vgpu)
> enum intel_engine_id i;
> int ret;
>
> - ppgtt = i915_ppgtt_create(&i915->gt);
> + ppgtt = i915_ppgtt_create(&i915->gt, I915_BO_ALLOC_PM_EARLY);
> if (IS_ERR(ppgtt))
> return PTR_ERR(ppgtt);
>
> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> index 2d60a5a5b065..46f4236039a9 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
> @@ -155,7 +155,7 @@ static int igt_ppgtt_alloc(void *arg)
> if (!HAS_PPGTT(dev_priv))
> return 0;
>
> - ppgtt = i915_ppgtt_create(&dev_priv->gt);
> + ppgtt = i915_ppgtt_create(&dev_priv->gt, 0);
> if (IS_ERR(ppgtt))
> return PTR_ERR(ppgtt);
>
> @@ -1053,7 +1053,7 @@ static int exercise_ppgtt(struct drm_i915_private *dev_priv,
> if (IS_ERR(file))
> return PTR_ERR(file);
>
> - ppgtt = i915_ppgtt_create(&dev_priv->gt);
> + ppgtt = i915_ppgtt_create(&dev_priv->gt, 0);
> if (IS_ERR(ppgtt)) {
> err = PTR_ERR(ppgtt);
> goto out_free;
>
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [PATCH v6 7/9] drm/i915: Reduce the number of objects subject to memcpy recover
2021-09-23 9:44 ` [Intel-gfx] " Matthew Auld
@ 2021-09-23 9:58 ` Thomas Hellström
-1 siblings, 0 replies; 39+ messages in thread
From: Thomas Hellström @ 2021-09-23 9:58 UTC (permalink / raw)
To: Matthew Auld, intel-gfx, dri-devel; +Cc: maarten.lankhorst, Matthew Brost
On 9/23/21 11:44 AM, Matthew Auld wrote:
> On 22/09/2021 07:25, Thomas Hellström wrote:
>> We really only need memcpy restore for objects that affect the
>> operability of the migrate context. That is, primarily the page-table
>> objects of the migrate VM.
>>
>> Add an object flag, I915_BO_ALLOC_PM_EARLY for objects that need early
>> restores using memcpy and a way to assign LMEM page-table object flags
>> to be used by the vms.
>>
>> Restore objects without this flag with the gpu blitter and only objects
>> carrying the flag using TTM memcpy.
>>
>> Initially mark the migrate, gt, gtt and vgpu vms to use this flag, and
>> defer for a later audit which vms actually need it. Most importantly,
>> user-
>> allocated vms with pinned page-table objects can be restored using the
>> blitter.
>>
>> Performance-wise memcpy restore is probably as fast as gpu restore if
>> not
>> faster, but using gpu restore will help tackling future restrictions in
>> mappable LMEM size.
>>
>> v4:
>> - Don't mark the aliasing ppgtt page table flags for early resume, but
>> rather the ggtt page table flags as intended. (Matthew Auld)
>> - The check for user buffer objects during early resume is pointless,
>> since
>> they are never marked I915_BO_ALLOC_PM_EARLY. (Matthew Auld)
>> v5:
>> - Mark GuC LMEM objects with I915_BO_ALLOC_PM_EARLY to have them
>> restored
>> before we fire up the migrate context.
>>
>> Cc: Matthew Brost <matthew.brost@intel.com>
>> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
>> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
>> ---
>> drivers/gpu/drm/i915/gem/i915_gem_context.c | 4 ++--
>> drivers/gpu/drm/i915/gem/i915_gem_object_types.h | 9 ++++++---
>> drivers/gpu/drm/i915/gem/i915_gem_pm.c | 6 +++++-
>> drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c | 5 +++--
>> drivers/gpu/drm/i915/gem/selftests/huge_pages.c | 2 +-
>> drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 2 +-
>> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 5 +++--
>> drivers/gpu/drm/i915/gt/gen8_ppgtt.h | 4 +++-
>> drivers/gpu/drm/i915/gt/intel_ggtt.c | 3 ++-
>> drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
>> drivers/gpu/drm/i915/gt/intel_gtt.c | 3 ++-
>> drivers/gpu/drm/i915/gt/intel_gtt.h | 9 +++++++--
>> drivers/gpu/drm/i915/gt/intel_migrate.c | 2 +-
>> drivers/gpu/drm/i915/gt/intel_ppgtt.c | 13 ++++++++-----
>> drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 2 +-
>> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 3 ++-
>> drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 7 +++++--
>> drivers/gpu/drm/i915/gvt/scheduler.c | 2 +-
>> drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 4 ++--
>> 19 files changed, 56 insertions(+), 31 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
>> b/drivers/gpu/drm/i915/gem/i915_gem_context.c
>> index c2ab0e22db0a..8208fd5b72c3 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
>> @@ -1287,7 +1287,7 @@ i915_gem_create_context(struct drm_i915_private
>> *i915,
>> } else if (HAS_FULL_PPGTT(i915)) {
>> struct i915_ppgtt *ppgtt;
>> - ppgtt = i915_ppgtt_create(&i915->gt);
>> + ppgtt = i915_ppgtt_create(&i915->gt, 0);
>> if (IS_ERR(ppgtt)) {
>> drm_dbg(&i915->drm, "PPGTT setup failed (%ld)\n",
>> PTR_ERR(ppgtt));
>> @@ -1465,7 +1465,7 @@ int i915_gem_vm_create_ioctl(struct drm_device
>> *dev, void *data,
>> if (args->flags)
>> return -EINVAL;
>> - ppgtt = i915_ppgtt_create(&i915->gt);
>> + ppgtt = i915_ppgtt_create(&i915->gt, 0);
>> if (IS_ERR(ppgtt))
>> return PTR_ERR(ppgtt);
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
>> b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
>> index 118691ce81d7..fa2ba9e2a4d0 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
>> @@ -294,13 +294,16 @@ struct drm_i915_gem_object {
>> #define I915_BO_ALLOC_USER BIT(3)
>> /* Object is allowed to lose its contents on suspend / resume, even
>> if pinned */
>> #define I915_BO_ALLOC_PM_VOLATILE BIT(4)
>> +/* Object needs to be restored early using memcpy during resume */
>> +#define I915_BO_ALLOC_PM_EARLY BIT(5)
>> #define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
>> I915_BO_ALLOC_VOLATILE | \
>> I915_BO_ALLOC_CPU_CLEAR | \
>> I915_BO_ALLOC_USER | \
>> - I915_BO_ALLOC_PM_VOLATILE)
>> -#define I915_BO_READONLY BIT(5)
>> -#define I915_TILING_QUIRK_BIT 6 /* unknown swizzling; do not
>> release! */
>> + I915_BO_ALLOC_PM_VOLATILE | \
>> + I915_BO_ALLOC_PM_EARLY)
>> +#define I915_BO_READONLY BIT(6)
>> +#define I915_TILING_QUIRK_BIT 7 /* unknown swizzling; do not
>> release! */
>> /**
>> * @mem_flags - Mutable placement-related flags
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
>> b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
>> index 12b37b4c1192..726b40e1fbb0 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
>> @@ -97,8 +97,12 @@ int i915_gem_backup_suspend(struct
>> drm_i915_private *i915)
>> * More objects may have become unpinned as requests were
>> * retired. Now try to evict again. The gt may be wedged here
>> * in which case we automatically fall back to memcpy.
>> + * We allow also backing up pinned objects that have not been
>> + * marked for early recover, and that may contain, for example,
>> + * page-tables for the migrate context.
>> */
>> - ret = lmem_suspend(i915, I915_TTM_BACKUP_ALLOW_GPU);
>> + ret = lmem_suspend(i915, I915_TTM_BACKUP_ALLOW_GPU |
>> + I915_TTM_BACKUP_PINNED);
>> if (ret)
>> goto out_recover;
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
>> b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
>> index 03a00d193f40..3b6d14b5c604 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
>> @@ -57,7 +57,8 @@ static int i915_ttm_backup(struct
>> i915_gem_apply_to_region *apply,
>> if (pm_apply->allow_gpu && i915_gem_object_evictable(obj))
>> return ttm_bo_validate(bo, i915_ttm_sys_placement(), &ctx);
>> - if (!pm_apply->backup_pinned)
>> + if (!pm_apply->backup_pinned ||
>> + (pm_apply->allow_gpu && (obj->flags & I915_BO_ALLOC_PM_EARLY)))
>> return 0;
>> if (obj->flags & I915_BO_ALLOC_PM_VOLATILE)
>> @@ -155,7 +156,7 @@ static int i915_ttm_restore(struct
>> i915_gem_apply_to_region *apply,
>> if (!backup)
>> return 0;
>> - if (!pm_apply->allow_gpu && (obj->flags & I915_BO_ALLOC_USER))
>> + if (!pm_apply->allow_gpu && !(obj->flags & I915_BO_ALLOC_PM_EARLY))
>> return 0;
>> err = i915_gem_object_lock(backup, apply->ww);
>> diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
>> b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
>> index 0827634c842c..77d84a9e8789 100644
>> --- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
>> +++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
>> @@ -1645,7 +1645,7 @@ int i915_gem_huge_page_mock_selftests(void)
>> mkwrite_device_info(dev_priv)->ppgtt_type = INTEL_PPGTT_FULL;
>> mkwrite_device_info(dev_priv)->ppgtt_size = 48;
>> - ppgtt = i915_ppgtt_create(&dev_priv->gt);
>> + ppgtt = i915_ppgtt_create(&dev_priv->gt, 0);
>> if (IS_ERR(ppgtt)) {
>> err = PTR_ERR(ppgtt);
>> goto out_unlock;
>> diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
>> b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
>> index 1aee5e6b1b23..890191f286e3 100644
>> --- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
>> +++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
>> @@ -429,7 +429,7 @@ struct i915_ppgtt *gen6_ppgtt_create(struct
>> intel_gt *gt)
>> mutex_init(&ppgtt->flush);
>> mutex_init(&ppgtt->pin_mutex);
>> - ppgtt_init(&ppgtt->base, gt);
>> + ppgtt_init(&ppgtt->base, gt, 0);
>> ppgtt->base.vm.pd_shift = ilog2(SZ_4K * SZ_4K /
>> sizeof(gen6_pte_t));
>> ppgtt->base.vm.top = 1;
>> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> index 6a5af995f5b1..037a9a6e4889 100644
>> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> @@ -753,7 +753,8 @@ gen8_alloc_top_pd(struct i915_address_space *vm)
>> * space.
>> *
>> */
>> -struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
>> +struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
>> + unsigned long lmem_pt_obj_flags)
>> {
>> struct i915_ppgtt *ppgtt;
>> int err;
>> @@ -762,7 +763,7 @@ struct i915_ppgtt *gen8_ppgtt_create(struct
>> intel_gt *gt)
>> if (!ppgtt)
>> return ERR_PTR(-ENOMEM);
>> - ppgtt_init(ppgtt, gt);
>> + ppgtt_init(ppgtt, gt, lmem_pt_obj_flags);
>> ppgtt->vm.top = i915_vm_is_4lvl(&ppgtt->vm) ? 3 : 2;
>> ppgtt->vm.pd_shift = ilog2(SZ_4K * SZ_4K / sizeof(gen8_pte_t));
>> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
>> b/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
>> index b9028c2ad3c7..f541d19264b4 100644
>> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
>> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
>> @@ -12,7 +12,9 @@ struct i915_address_space;
>> struct intel_gt;
>> enum i915_cache_level;
>> -struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt);
>> +struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
>> + unsigned long lmem_pt_obj_flags);
>> +
>> u64 gen8_ggtt_pte_encode(dma_addr_t addr,
>> enum i915_cache_level level,
>> u32 flags);
>> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> b/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> index 8d71f67926f1..06576fc1310e 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> @@ -644,7 +644,7 @@ static int init_aliasing_ppgtt(struct i915_ggtt
>> *ggtt)
>> struct i915_ppgtt *ppgtt;
>> int err;
>> - ppgtt = i915_ppgtt_create(ggtt->vm.gt);
>> + ppgtt = i915_ppgtt_create(ggtt->vm.gt, 0);
>> if (IS_ERR(ppgtt))
>> return PTR_ERR(ppgtt);
>> @@ -909,6 +909,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
>> size = gen8_get_total_gtt_size(snb_gmch_ctl);
>> ggtt->vm.alloc_pt_dma = alloc_pt_dma;
>> + ggtt->vm.lmem_pt_obj_flags = I915_BO_ALLOC_PM_EARLY;
>
> The scratch page is still in system memory for the ggtt, so I guess
> this is not needed? Although maybe that will change, so probably good
> to keep?
Hmm, yes, I guess lets keep this for a possible future audit for now. I
think there are other vms that may not need this flag either.
Thanks for reviewing!
/Thomas
^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [Intel-gfx] [PATCH v6 7/9] drm/i915: Reduce the number of objects subject to memcpy recover
@ 2021-09-23 9:58 ` Thomas Hellström
0 siblings, 0 replies; 39+ messages in thread
From: Thomas Hellström @ 2021-09-23 9:58 UTC (permalink / raw)
To: Matthew Auld, intel-gfx, dri-devel; +Cc: maarten.lankhorst, Matthew Brost
On 9/23/21 11:44 AM, Matthew Auld wrote:
> On 22/09/2021 07:25, Thomas Hellström wrote:
>> We really only need memcpy restore for objects that affect the
>> operability of the migrate context. That is, primarily the page-table
>> objects of the migrate VM.
>>
>> Add an object flag, I915_BO_ALLOC_PM_EARLY for objects that need early
>> restores using memcpy and a way to assign LMEM page-table object flags
>> to be used by the vms.
>>
>> Restore objects without this flag with the gpu blitter and only objects
>> carrying the flag using TTM memcpy.
>>
>> Initially mark the migrate, gt, gtt and vgpu vms to use this flag, and
>> defer for a later audit which vms actually need it. Most importantly,
>> user-
>> allocated vms with pinned page-table objects can be restored using the
>> blitter.
>>
>> Performance-wise memcpy restore is probably as fast as gpu restore if
>> not
>> faster, but using gpu restore will help tackling future restrictions in
>> mappable LMEM size.
>>
>> v4:
>> - Don't mark the aliasing ppgtt page table flags for early resume, but
>> rather the ggtt page table flags as intended. (Matthew Auld)
>> - The check for user buffer objects during early resume is pointless,
>> since
>> they are never marked I915_BO_ALLOC_PM_EARLY. (Matthew Auld)
>> v5:
>> - Mark GuC LMEM objects with I915_BO_ALLOC_PM_EARLY to have them
>> restored
>> before we fire up the migrate context.
>>
>> Cc: Matthew Brost <matthew.brost@intel.com>
>> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
>> Reviewed-by: Matthew Auld <matthew.auld@intel.com>
>> ---
>> drivers/gpu/drm/i915/gem/i915_gem_context.c | 4 ++--
>> drivers/gpu/drm/i915/gem/i915_gem_object_types.h | 9 ++++++---
>> drivers/gpu/drm/i915/gem/i915_gem_pm.c | 6 +++++-
>> drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c | 5 +++--
>> drivers/gpu/drm/i915/gem/selftests/huge_pages.c | 2 +-
>> drivers/gpu/drm/i915/gt/gen6_ppgtt.c | 2 +-
>> drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 5 +++--
>> drivers/gpu/drm/i915/gt/gen8_ppgtt.h | 4 +++-
>> drivers/gpu/drm/i915/gt/intel_ggtt.c | 3 ++-
>> drivers/gpu/drm/i915/gt/intel_gt.c | 2 +-
>> drivers/gpu/drm/i915/gt/intel_gtt.c | 3 ++-
>> drivers/gpu/drm/i915/gt/intel_gtt.h | 9 +++++++--
>> drivers/gpu/drm/i915/gt/intel_migrate.c | 2 +-
>> drivers/gpu/drm/i915/gt/intel_ppgtt.c | 13 ++++++++-----
>> drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 2 +-
>> drivers/gpu/drm/i915/gt/uc/intel_guc.c | 3 ++-
>> drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 7 +++++--
>> drivers/gpu/drm/i915/gvt/scheduler.c | 2 +-
>> drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 4 ++--
>> 19 files changed, 56 insertions(+), 31 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
>> b/drivers/gpu/drm/i915/gem/i915_gem_context.c
>> index c2ab0e22db0a..8208fd5b72c3 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
>> @@ -1287,7 +1287,7 @@ i915_gem_create_context(struct drm_i915_private
>> *i915,
>> } else if (HAS_FULL_PPGTT(i915)) {
>> struct i915_ppgtt *ppgtt;
>> - ppgtt = i915_ppgtt_create(&i915->gt);
>> + ppgtt = i915_ppgtt_create(&i915->gt, 0);
>> if (IS_ERR(ppgtt)) {
>> drm_dbg(&i915->drm, "PPGTT setup failed (%ld)\n",
>> PTR_ERR(ppgtt));
>> @@ -1465,7 +1465,7 @@ int i915_gem_vm_create_ioctl(struct drm_device
>> *dev, void *data,
>> if (args->flags)
>> return -EINVAL;
>> - ppgtt = i915_ppgtt_create(&i915->gt);
>> + ppgtt = i915_ppgtt_create(&i915->gt, 0);
>> if (IS_ERR(ppgtt))
>> return PTR_ERR(ppgtt);
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
>> b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
>> index 118691ce81d7..fa2ba9e2a4d0 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
>> @@ -294,13 +294,16 @@ struct drm_i915_gem_object {
>> #define I915_BO_ALLOC_USER BIT(3)
>> /* Object is allowed to lose its contents on suspend / resume, even
>> if pinned */
>> #define I915_BO_ALLOC_PM_VOLATILE BIT(4)
>> +/* Object needs to be restored early using memcpy during resume */
>> +#define I915_BO_ALLOC_PM_EARLY BIT(5)
>> #define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
>> I915_BO_ALLOC_VOLATILE | \
>> I915_BO_ALLOC_CPU_CLEAR | \
>> I915_BO_ALLOC_USER | \
>> - I915_BO_ALLOC_PM_VOLATILE)
>> -#define I915_BO_READONLY BIT(5)
>> -#define I915_TILING_QUIRK_BIT 6 /* unknown swizzling; do not
>> release! */
>> + I915_BO_ALLOC_PM_VOLATILE | \
>> + I915_BO_ALLOC_PM_EARLY)
>> +#define I915_BO_READONLY BIT(6)
>> +#define I915_TILING_QUIRK_BIT 7 /* unknown swizzling; do not
>> release! */
>> /**
>> * @mem_flags - Mutable placement-related flags
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
>> b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
>> index 12b37b4c1192..726b40e1fbb0 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_pm.c
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_pm.c
>> @@ -97,8 +97,12 @@ int i915_gem_backup_suspend(struct
>> drm_i915_private *i915)
>> * More objects may have become unpinned as requests were
>> * retired. Now try to evict again. The gt may be wedged here
>> * in which case we automatically fall back to memcpy.
>> + * We allow also backing up pinned objects that have not been
>> + * marked for early recover, and that may contain, for example,
>> + * page-tables for the migrate context.
>> */
>> - ret = lmem_suspend(i915, I915_TTM_BACKUP_ALLOW_GPU);
>> + ret = lmem_suspend(i915, I915_TTM_BACKUP_ALLOW_GPU |
>> + I915_TTM_BACKUP_PINNED);
>> if (ret)
>> goto out_recover;
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
>> b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
>> index 03a00d193f40..3b6d14b5c604 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.c
>> @@ -57,7 +57,8 @@ static int i915_ttm_backup(struct
>> i915_gem_apply_to_region *apply,
>> if (pm_apply->allow_gpu && i915_gem_object_evictable(obj))
>> return ttm_bo_validate(bo, i915_ttm_sys_placement(), &ctx);
>> - if (!pm_apply->backup_pinned)
>> + if (!pm_apply->backup_pinned ||
>> + (pm_apply->allow_gpu && (obj->flags & I915_BO_ALLOC_PM_EARLY)))
>> return 0;
>> if (obj->flags & I915_BO_ALLOC_PM_VOLATILE)
>> @@ -155,7 +156,7 @@ static int i915_ttm_restore(struct
>> i915_gem_apply_to_region *apply,
>> if (!backup)
>> return 0;
>> - if (!pm_apply->allow_gpu && (obj->flags & I915_BO_ALLOC_USER))
>> + if (!pm_apply->allow_gpu && !(obj->flags & I915_BO_ALLOC_PM_EARLY))
>> return 0;
>> err = i915_gem_object_lock(backup, apply->ww);
>> diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
>> b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
>> index 0827634c842c..77d84a9e8789 100644
>> --- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
>> +++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
>> @@ -1645,7 +1645,7 @@ int i915_gem_huge_page_mock_selftests(void)
>> mkwrite_device_info(dev_priv)->ppgtt_type = INTEL_PPGTT_FULL;
>> mkwrite_device_info(dev_priv)->ppgtt_size = 48;
>> - ppgtt = i915_ppgtt_create(&dev_priv->gt);
>> + ppgtt = i915_ppgtt_create(&dev_priv->gt, 0);
>> if (IS_ERR(ppgtt)) {
>> err = PTR_ERR(ppgtt);
>> goto out_unlock;
>> diff --git a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
>> b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
>> index 1aee5e6b1b23..890191f286e3 100644
>> --- a/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
>> +++ b/drivers/gpu/drm/i915/gt/gen6_ppgtt.c
>> @@ -429,7 +429,7 @@ struct i915_ppgtt *gen6_ppgtt_create(struct
>> intel_gt *gt)
>> mutex_init(&ppgtt->flush);
>> mutex_init(&ppgtt->pin_mutex);
>> - ppgtt_init(&ppgtt->base, gt);
>> + ppgtt_init(&ppgtt->base, gt, 0);
>> ppgtt->base.vm.pd_shift = ilog2(SZ_4K * SZ_4K /
>> sizeof(gen6_pte_t));
>> ppgtt->base.vm.top = 1;
>> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> index 6a5af995f5b1..037a9a6e4889 100644
>> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
>> @@ -753,7 +753,8 @@ gen8_alloc_top_pd(struct i915_address_space *vm)
>> * space.
>> *
>> */
>> -struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
>> +struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
>> + unsigned long lmem_pt_obj_flags)
>> {
>> struct i915_ppgtt *ppgtt;
>> int err;
>> @@ -762,7 +763,7 @@ struct i915_ppgtt *gen8_ppgtt_create(struct
>> intel_gt *gt)
>> if (!ppgtt)
>> return ERR_PTR(-ENOMEM);
>> - ppgtt_init(ppgtt, gt);
>> + ppgtt_init(ppgtt, gt, lmem_pt_obj_flags);
>> ppgtt->vm.top = i915_vm_is_4lvl(&ppgtt->vm) ? 3 : 2;
>> ppgtt->vm.pd_shift = ilog2(SZ_4K * SZ_4K / sizeof(gen8_pte_t));
>> diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
>> b/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
>> index b9028c2ad3c7..f541d19264b4 100644
>> --- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
>> +++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.h
>> @@ -12,7 +12,9 @@ struct i915_address_space;
>> struct intel_gt;
>> enum i915_cache_level;
>> -struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt);
>> +struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt,
>> + unsigned long lmem_pt_obj_flags);
>> +
>> u64 gen8_ggtt_pte_encode(dma_addr_t addr,
>> enum i915_cache_level level,
>> u32 flags);
>> diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> b/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> index 8d71f67926f1..06576fc1310e 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
>> @@ -644,7 +644,7 @@ static int init_aliasing_ppgtt(struct i915_ggtt
>> *ggtt)
>> struct i915_ppgtt *ppgtt;
>> int err;
>> - ppgtt = i915_ppgtt_create(ggtt->vm.gt);
>> + ppgtt = i915_ppgtt_create(ggtt->vm.gt, 0);
>> if (IS_ERR(ppgtt))
>> return PTR_ERR(ppgtt);
>> @@ -909,6 +909,7 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
>> size = gen8_get_total_gtt_size(snb_gmch_ctl);
>> ggtt->vm.alloc_pt_dma = alloc_pt_dma;
>> + ggtt->vm.lmem_pt_obj_flags = I915_BO_ALLOC_PM_EARLY;
>
> The scratch page is still in system memory for the ggtt, so I guess
> this is not needed? Although maybe that will change, so probably good
> to keep?
Hmm, yes, I guess lets keep this for a possible future audit for now. I
think there are other vms that may not need this flag either.
Thanks for reviewing!
/Thomas
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v6 8/9] HAX: component: do not leave master devres group open after bind
2021-09-22 6:25 ` [Intel-gfx] " Thomas Hellström
@ 2021-09-22 6:25 ` Thomas Hellström
-1 siblings, 0 replies; 39+ messages in thread
From: Thomas Hellström @ 2021-09-22 6:25 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: maarten.lankhorst, matthew.auld, Kai Vehmanen, Imre Deak, Russell King
From: Kai Vehmanen <kai.vehmanen@linux.intel.com>
In current code, the devres group for aggregate master is left open
after call to component_master_add_*(). This leads to problems when the
master does further managed allocations on its own. When any
participating driver calls component_del(), this leads to immediate
release of resources.
This came up when investigating a page fault occurring with i915 DRM
driver unbind with 5.15-rc1 kernel. The following sequence occurs:
i915_pci_remove()
-> intel_display_driver_unregister()
-> i915_audio_component_cleanup()
-> component_del()
-> component.c:take_down_master()
-> hdac_component_master_unbind() [via master->ops->unbind()]
-> devres_release_group(master->parent, NULL)
With older kernels this has not caused issues, but with audio driver
moving to use managed interfaces for more of its allocations, this no
longer works. Devres log shows following to occur:
component_master_add_with_match()
[ 126.886032] snd_hda_intel 0000:00:1f.3: DEVRES ADD 00000000323ccdc5 devm_component_match_release (24 bytes)
[ 126.886045] snd_hda_intel 0000:00:1f.3: DEVRES ADD 00000000865cdb29 grp< (0 bytes)
[ 126.886049] snd_hda_intel 0000:00:1f.3: DEVRES ADD 000000001b480725 grp< (0 bytes)
audio driver completes its PCI probe()
[ 126.892238] snd_hda_intel 0000:00:1f.3: DEVRES ADD 000000001b480725 pcim_iomap_release (48 bytes)
component_del() called() at DRM/i915 unbind()
[ 137.579422] i915 0000:00:02.0: DEVRES REL 00000000ef44c293 grp< (0 bytes)
[ 137.579445] snd_hda_intel 0000:00:1f.3: DEVRES REL 00000000865cdb29 grp< (0 bytes)
[ 137.579458] snd_hda_intel 0000:00:1f.3: DEVRES REL 000000001b480725 pcim_iomap_release (48 bytes)
So the "devres_release_group(master->parent, NULL)" ends up freeing the
pcim_iomap allocation. Upon next runtime resume, the audio driver will
cause a page fault as the iomap alloc was released without the driver
knowing about it.
Fix this issue by using the "struct master" pointer as identifier for
the devres group, and by closing the devres group after the master->ops->bind()
call is done. This allows devres allocations done by the driver acting as
master to be isolated from the binding state of the aggregate driver. This
modifies the logic originally introduced in commit 9e1ccb4a7700
("drivers/base: fix devres handling for master device").
BugLink: https://gitlab.freedesktop.org/drm/intel/-/issues/4136
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Acked-by: Imre Deak <imre.deak@intel.com>
Acked-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
drivers/base/component.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/base/component.c b/drivers/base/component.c
index 5e79299f6c3f..870485cbbb87 100644
--- a/drivers/base/component.c
+++ b/drivers/base/component.c
@@ -246,7 +246,7 @@ static int try_to_bring_up_master(struct master *master,
return 0;
}
- if (!devres_open_group(master->parent, NULL, GFP_KERNEL))
+ if (!devres_open_group(master->parent, master, GFP_KERNEL))
return -ENOMEM;
/* Found all components */
@@ -258,6 +258,7 @@ static int try_to_bring_up_master(struct master *master,
return ret;
}
+ devres_close_group(master->parent, NULL);
master->bound = true;
return 1;
}
@@ -282,7 +283,7 @@ static void take_down_master(struct master *master)
{
if (master->bound) {
master->ops->unbind(master->parent);
- devres_release_group(master->parent, NULL);
+ devres_release_group(master->parent, master);
master->bound = false;
}
}
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread* [Intel-gfx] [PATCH v6 8/9] HAX: component: do not leave master devres group open after bind
@ 2021-09-22 6:25 ` Thomas Hellström
0 siblings, 0 replies; 39+ messages in thread
From: Thomas Hellström @ 2021-09-22 6:25 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: maarten.lankhorst, matthew.auld, Kai Vehmanen, Imre Deak, Russell King
From: Kai Vehmanen <kai.vehmanen@linux.intel.com>
In current code, the devres group for aggregate master is left open
after call to component_master_add_*(). This leads to problems when the
master does further managed allocations on its own. When any
participating driver calls component_del(), this leads to immediate
release of resources.
This came up when investigating a page fault occurring with i915 DRM
driver unbind with 5.15-rc1 kernel. The following sequence occurs:
i915_pci_remove()
-> intel_display_driver_unregister()
-> i915_audio_component_cleanup()
-> component_del()
-> component.c:take_down_master()
-> hdac_component_master_unbind() [via master->ops->unbind()]
-> devres_release_group(master->parent, NULL)
With older kernels this has not caused issues, but with audio driver
moving to use managed interfaces for more of its allocations, this no
longer works. Devres log shows following to occur:
component_master_add_with_match()
[ 126.886032] snd_hda_intel 0000:00:1f.3: DEVRES ADD 00000000323ccdc5 devm_component_match_release (24 bytes)
[ 126.886045] snd_hda_intel 0000:00:1f.3: DEVRES ADD 00000000865cdb29 grp< (0 bytes)
[ 126.886049] snd_hda_intel 0000:00:1f.3: DEVRES ADD 000000001b480725 grp< (0 bytes)
audio driver completes its PCI probe()
[ 126.892238] snd_hda_intel 0000:00:1f.3: DEVRES ADD 000000001b480725 pcim_iomap_release (48 bytes)
component_del() called() at DRM/i915 unbind()
[ 137.579422] i915 0000:00:02.0: DEVRES REL 00000000ef44c293 grp< (0 bytes)
[ 137.579445] snd_hda_intel 0000:00:1f.3: DEVRES REL 00000000865cdb29 grp< (0 bytes)
[ 137.579458] snd_hda_intel 0000:00:1f.3: DEVRES REL 000000001b480725 pcim_iomap_release (48 bytes)
So the "devres_release_group(master->parent, NULL)" ends up freeing the
pcim_iomap allocation. Upon next runtime resume, the audio driver will
cause a page fault as the iomap alloc was released without the driver
knowing about it.
Fix this issue by using the "struct master" pointer as identifier for
the devres group, and by closing the devres group after the master->ops->bind()
call is done. This allows devres allocations done by the driver acting as
master to be isolated from the binding state of the aggregate driver. This
modifies the logic originally introduced in commit 9e1ccb4a7700
("drivers/base: fix devres handling for master device").
BugLink: https://gitlab.freedesktop.org/drm/intel/-/issues/4136
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Acked-by: Imre Deak <imre.deak@intel.com>
Acked-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
drivers/base/component.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/base/component.c b/drivers/base/component.c
index 5e79299f6c3f..870485cbbb87 100644
--- a/drivers/base/component.c
+++ b/drivers/base/component.c
@@ -246,7 +246,7 @@ static int try_to_bring_up_master(struct master *master,
return 0;
}
- if (!devres_open_group(master->parent, NULL, GFP_KERNEL))
+ if (!devres_open_group(master->parent, master, GFP_KERNEL))
return -ENOMEM;
/* Found all components */
@@ -258,6 +258,7 @@ static int try_to_bring_up_master(struct master *master,
return ret;
}
+ devres_close_group(master->parent, NULL);
master->bound = true;
return 1;
}
@@ -282,7 +283,7 @@ static void take_down_master(struct master *master)
{
if (master->bound) {
master->ops->unbind(master->parent);
- devres_release_group(master->parent, NULL);
+ devres_release_group(master->parent, master);
master->bound = false;
}
}
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v6 9/9] HAX: drm/i915/gem: Fix the __i915_gem_is_lmem() function
2021-09-22 6:25 ` [Intel-gfx] " Thomas Hellström
@ 2021-09-22 6:25 ` Thomas Hellström
-1 siblings, 0 replies; 39+ messages in thread
From: Thomas Hellström @ 2021-09-22 6:25 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: maarten.lankhorst, matthew.auld, Thomas Hellström
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
index d659239fcbcc..444f8268b9c5 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
@@ -67,7 +67,7 @@ bool __i915_gem_object_is_lmem(struct drm_i915_gem_object *obj)
#ifdef CONFIG_LOCKDEP
GEM_WARN_ON(dma_resv_test_signaled(obj->base.resv, true) &&
- !i915_gem_object_evictable(obj));
+ i915_gem_object_evictable(obj));
#endif
return mr && (mr->type == INTEL_MEMORY_LOCAL ||
mr->type == INTEL_MEMORY_STOLEN_LOCAL);
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [Intel-gfx] [PATCH v6 9/9] HAX: drm/i915/gem: Fix the __i915_gem_is_lmem() function
@ 2021-09-22 6:25 ` Thomas Hellström
0 siblings, 0 replies; 39+ messages in thread
From: Thomas Hellström @ 2021-09-22 6:25 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: maarten.lankhorst, matthew.auld, Thomas Hellström
Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
index d659239fcbcc..444f8268b9c5 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_lmem.c
@@ -67,7 +67,7 @@ bool __i915_gem_object_is_lmem(struct drm_i915_gem_object *obj)
#ifdef CONFIG_LOCKDEP
GEM_WARN_ON(dma_resv_test_signaled(obj->base.resv, true) &&
- !i915_gem_object_evictable(obj));
+ i915_gem_object_evictable(obj));
#endif
return mr && (mr->type == INTEL_MEMORY_LOCAL ||
mr->type == INTEL_MEMORY_STOLEN_LOCAL);
--
2.31.1
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Suspend / resume backup- and restore of LMEM. (rev9)
2021-09-22 6:25 ` [Intel-gfx] " Thomas Hellström
` (9 preceding siblings ...)
(?)
@ 2021-09-22 7:23 ` Patchwork
-1 siblings, 0 replies; 39+ messages in thread
From: Patchwork @ 2021-09-22 7:23 UTC (permalink / raw)
To: Thomas Hellström; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Suspend / resume backup- and restore of LMEM. (rev9)
URL : https://patchwork.freedesktop.org/series/94278/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e8b189cb9e01 drm/i915/ttm: Implement a function to copy the contents of two TTM-based objects
09e0ddae5bb8 drm/i915/gem: Implement a function to process all gem objects of a region
fdabedd0192a drm/i915/gt: Increase suspend timeout
a985db037d67 drm/i915 Implement LMEM backup and restore for suspend / resume
-:287: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#287:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 459 lines checked
d0431e05a63c drm/i915/gt: Register the migrate contexts with their engines
2142fe4d8210 drm/i915: Don't back up pinned LMEM context images and rings during suspend
62ebddd959d3 drm/i915: Reduce the number of objects subject to memcpy recover
15d4f42667e0 HAX: component: do not leave master devres group open after bind
-:47: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#47:
the devres group, and by closing the devres group after the master->ops->bind()
total: 0 errors, 1 warnings, 0 checks, 23 lines checked
557bb3a815fd HAX: drm/i915/gem: Fix the __i915_gem_is_lmem() function
-:10: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
total: 0 errors, 1 warnings, 0 checks, 8 lines checked
^ permalink raw reply [flat|nested] 39+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Suspend / resume backup- and restore of LMEM. (rev9)
2021-09-22 6:25 ` [Intel-gfx] " Thomas Hellström
` (10 preceding siblings ...)
(?)
@ 2021-09-22 7:25 ` Patchwork
-1 siblings, 0 replies; 39+ messages in thread
From: Patchwork @ 2021-09-22 7:25 UTC (permalink / raw)
To: Thomas Hellström; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Suspend / resume backup- and restore of LMEM. (rev9)
URL : https://patchwork.freedesktop.org/series/94278/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216
+./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080)
+./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080)
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
^ permalink raw reply [flat|nested] 39+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Suspend / resume backup- and restore of LMEM. (rev9)
2021-09-22 6:25 ` [Intel-gfx] " Thomas Hellström
` (11 preceding siblings ...)
(?)
@ 2021-09-22 7:52 ` Patchwork
-1 siblings, 0 replies; 39+ messages in thread
From: Patchwork @ 2021-09-22 7:52 UTC (permalink / raw)
To: Thomas Hellström; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 12073 bytes --]
== Series Details ==
Series: drm/i915: Suspend / resume backup- and restore of LMEM. (rev9)
URL : https://patchwork.freedesktop.org/series/94278/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10622 -> Patchwork_21124
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/index.html
Known issues
------------
Here are the changes found in Patchwork_21124 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@cs-compute:
- fi-cfl-guc: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/fi-cfl-guc/igt@amdgpu/amd_basic@cs-compute.html
* igt@amdgpu/amd_basic@cs-sdma:
- fi-cfl-8109u: NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/fi-cfl-8109u/igt@amdgpu/amd_basic@cs-sdma.html
* igt@amdgpu/amd_basic@memory-alloc:
- fi-cml-u2: NOTRUN -> [SKIP][3] ([fdo#109315]) +17 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/fi-cml-u2/igt@amdgpu/amd_basic@memory-alloc.html
* igt@amdgpu/amd_basic@query-info:
- fi-tgl-1115g4: NOTRUN -> [SKIP][4] ([fdo#109315])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/fi-tgl-1115g4/igt@amdgpu/amd_basic@query-info.html
- fi-kbl-8809g: NOTRUN -> [SKIP][5] ([fdo#109271])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/fi-kbl-8809g/igt@amdgpu/amd_basic@query-info.html
* igt@amdgpu/amd_cs_nop@fork-compute0:
- fi-ivb-3770: NOTRUN -> [SKIP][6] ([fdo#109271]) +18 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/fi-ivb-3770/igt@amdgpu/amd_cs_nop@fork-compute0.html
* igt@amdgpu/amd_cs_nop@fork-gfx0:
- fi-icl-u2: NOTRUN -> [SKIP][7] ([fdo#109315]) +17 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/fi-icl-u2/igt@amdgpu/amd_cs_nop@fork-gfx0.html
* igt@amdgpu/amd_cs_nop@nop-gfx0:
- fi-tgl-1115g4: NOTRUN -> [SKIP][8] ([fdo#109315] / [i915#2575]) +16 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/fi-tgl-1115g4/igt@amdgpu/amd_cs_nop@nop-gfx0.html
* igt@gem_huc_copy@huc-copy:
- fi-tgl-1115g4: NOTRUN -> [SKIP][9] ([i915#2190])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/fi-tgl-1115g4/igt@gem_huc_copy@huc-copy.html
* igt@i915_pm_backlight@basic-brightness:
- fi-tgl-1115g4: NOTRUN -> [SKIP][10] ([i915#1155])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/fi-tgl-1115g4/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_pm_rpm@module-reload:
- fi-kbl-r: NOTRUN -> [INCOMPLETE][11] ([i915#151] / [i915#92])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/fi-kbl-r/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][12] ([i915#1886] / [i915#2291])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-tgl-1115g4: NOTRUN -> [SKIP][13] ([fdo#111827]) +8 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/fi-tgl-1115g4/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-1115g4: NOTRUN -> [SKIP][14] ([i915#4103]) +1 similar issue
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/fi-tgl-1115g4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-1115g4: NOTRUN -> [SKIP][15] ([fdo#109285])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/fi-tgl-1115g4/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_psr@primary_mmap_gtt:
- fi-tgl-1115g4: NOTRUN -> [SKIP][16] ([i915#1072]) +3 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/fi-tgl-1115g4/igt@kms_psr@primary_mmap_gtt.html
* igt@prime_vgem@basic-userptr:
- fi-tgl-1115g4: NOTRUN -> [SKIP][17] ([i915#3301])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/fi-tgl-1115g4/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-kbl-r: NOTRUN -> [FAIL][18] ([fdo#109271] / [i915#1814] / [i915#2722] / [i915#3363])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/fi-kbl-r/igt@runner@aborted.html
#### Possible fixes ####
* igt@core_hotunplug@unbind-rebind:
- fi-cfl-guc: [INCOMPLETE][19] ([i915#4130] / [i915#4136]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/fi-cfl-guc/igt@core_hotunplug@unbind-rebind.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/fi-cfl-guc/igt@core_hotunplug@unbind-rebind.html
- fi-icl-u2: [INCOMPLETE][21] ([i915#4130]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/fi-icl-u2/igt@core_hotunplug@unbind-rebind.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/fi-icl-u2/igt@core_hotunplug@unbind-rebind.html
- fi-cfl-8109u: [INCOMPLETE][23] ([i915#4130]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/fi-cfl-8109u/igt@core_hotunplug@unbind-rebind.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/fi-cfl-8109u/igt@core_hotunplug@unbind-rebind.html
* igt@i915_module_load@reload:
- fi-kbl-8809g: [INCOMPLETE][25] ([i915#4136]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/fi-kbl-8809g/igt@i915_module_load@reload.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/fi-kbl-8809g/igt@i915_module_load@reload.html
- fi-cml-u2: [INCOMPLETE][27] ([i915#4130] / [i915#4136]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/fi-cml-u2/igt@i915_module_load@reload.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/fi-cml-u2/igt@i915_module_load@reload.html
- {fi-tgl-dsi}: [INCOMPLETE][29] ([i915#4130] / [i915#4136]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/fi-tgl-dsi/igt@i915_module_load@reload.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/fi-tgl-dsi/igt@i915_module_load@reload.html
- {fi-ehl-2}: [INCOMPLETE][31] ([i915#4136]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/fi-ehl-2/igt@i915_module_load@reload.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/fi-ehl-2/igt@i915_module_load@reload.html
- fi-kbl-r: [INCOMPLETE][33] ([i915#4136]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/fi-kbl-r/igt@i915_module_load@reload.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/fi-kbl-r/igt@i915_module_load@reload.html
- fi-kbl-soraka: [INCOMPLETE][35] ([i915#4136]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/fi-kbl-soraka/igt@i915_module_load@reload.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/fi-kbl-soraka/igt@i915_module_load@reload.html
- fi-ivb-3770: [INCOMPLETE][37] ([i915#4179]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/fi-ivb-3770/igt@i915_module_load@reload.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/fi-ivb-3770/igt@i915_module_load@reload.html
- {fi-jsl-1}: [TIMEOUT][39] ([i915#4136]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/fi-jsl-1/igt@i915_module_load@reload.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/fi-jsl-1/igt@i915_module_load@reload.html
* igt@kms_flip@basic-plain-flip@c-dp1:
- fi-cfl-8109u: [FAIL][41] ([i915#4165]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/fi-cfl-8109u/igt@kms_flip@basic-plain-flip@c-dp1.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/fi-cfl-8109u/igt@kms_flip@basic-plain-flip@c-dp1.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-cfl-8109u: [DMESG-WARN][43] ([i915#295]) -> [PASS][44] +14 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151
[i915#1759]: https://gitlab.freedesktop.org/drm/intel/issues/1759
[i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2291]: https://gitlab.freedesktop.org/drm/intel/issues/2291
[i915#2373]: https://gitlab.freedesktop.org/drm/intel/issues/2373
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4130]: https://gitlab.freedesktop.org/drm/intel/issues/4130
[i915#4136]: https://gitlab.freedesktop.org/drm/intel/issues/4136
[i915#4165]: https://gitlab.freedesktop.org/drm/intel/issues/4165
[i915#4179]: https://gitlab.freedesktop.org/drm/intel/issues/4179
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
Participating hosts (33 -> 25)
------------------------------
Additional (1): fi-tgl-1115g4
Missing (9): fi-bdw-5557u bat-dg1-6 fi-glk-dsi fi-bsw-cyan fi-bwr-2160 fi-pnv-d510 fi-bsw-kefka fi-bsw-nick fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_10622 -> Patchwork_21124
CI-20190529: 20190529
CI_DRM_10622: 525a2117194d1c06200adb49678fe56fd1641591 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6214: 13550e92c6c7bd825abb6c9b087d12a524b4674c @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21124: 557bb3a815fd1f4068842a0cd73c6e03a079f3c1 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
557bb3a815fd HAX: drm/i915/gem: Fix the __i915_gem_is_lmem() function
15d4f42667e0 HAX: component: do not leave master devres group open after bind
62ebddd959d3 drm/i915: Reduce the number of objects subject to memcpy recover
2142fe4d8210 drm/i915: Don't back up pinned LMEM context images and rings during suspend
d0431e05a63c drm/i915/gt: Register the migrate contexts with their engines
a985db037d67 drm/i915 Implement LMEM backup and restore for suspend / resume
fdabedd0192a drm/i915/gt: Increase suspend timeout
09e0ddae5bb8 drm/i915/gem: Implement a function to process all gem objects of a region
e8b189cb9e01 drm/i915/ttm: Implement a function to copy the contents of two TTM-based objects
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/index.html
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^ permalink raw reply [flat|nested] 39+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Suspend / resume backup- and restore of LMEM. (rev9)
2021-09-22 6:25 ` [Intel-gfx] " Thomas Hellström
` (12 preceding siblings ...)
(?)
@ 2021-09-22 9:05 ` Patchwork
2021-09-22 18:06 ` Thomas Hellström
-1 siblings, 1 reply; 39+ messages in thread
From: Patchwork @ 2021-09-22 9:05 UTC (permalink / raw)
To: Thomas Hellström; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30285 bytes --]
== Series Details ==
Series: drm/i915: Suspend / resume backup- and restore of LMEM. (rev9)
URL : https://patchwork.freedesktop.org/series/94278/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10622_full -> Patchwork_21124_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_21124_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21124_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_21124_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_schedule@u-submit-golden-slice@rcs0:
- shard-tglb: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-tglb3/igt@gem_exec_schedule@u-submit-golden-slice@rcs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb6/igt@gem_exec_schedule@u-submit-golden-slice@rcs0.html
Known issues
------------
Here are the changes found in Patchwork_21124_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_create@create-massive:
- shard-apl: NOTRUN -> [DMESG-WARN][3] ([i915#3002])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-apl1/igt@gem_create@create-massive.html
* igt@gem_ctx_isolation@preservation-s3@vecs0:
- shard-skl: [PASS][4] -> [INCOMPLETE][5] ([i915#146] / [i915#198])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-skl1/igt@gem_ctx_isolation@preservation-s3@vecs0.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-skl10/igt@gem_ctx_isolation@preservation-s3@vecs0.html
* igt@gem_ctx_persistence@engines-mixed:
- shard-snb: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1099]) +4 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-snb2/igt@gem_ctx_persistence@engines-mixed.html
* igt@gem_eio@in-flight-1us:
- shard-skl: [PASS][7] -> [TIMEOUT][8] ([i915#3063])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-skl1/igt@gem_eio@in-flight-1us.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-skl9/igt@gem_eio@in-flight-1us.html
* igt@gem_eio@unwedge-stress:
- shard-iclb: [PASS][9] -> [TIMEOUT][10] ([i915#2369] / [i915#2481] / [i915#3070])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-iclb4/igt@gem_eio@unwedge-stress.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb3/igt@gem_eio@unwedge-stress.html
- shard-snb: NOTRUN -> [FAIL][11] ([i915#3354])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-snb6/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-none@rcs0:
- shard-glk: NOTRUN -> [FAIL][12] ([i915#2842])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-glk9/igt@gem_exec_fair@basic-none@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-tglb: NOTRUN -> [FAIL][13] ([i915#2842]) +4 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb8/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-iclb: NOTRUN -> [FAIL][14] ([i915#2842]) +3 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb5/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][15] -> [FAIL][16] ([i915#2842])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-glk9/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][17] -> [FAIL][18] ([i915#2849])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-iclb2/igt@gem_exec_fair@basic-throttle@rcs0.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb7/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_params@no-blt:
- shard-tglb: NOTRUN -> [SKIP][19] ([fdo#109283])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb6/igt@gem_exec_params@no-blt.html
* igt@gem_huc_copy@huc-copy:
- shard-iclb: NOTRUN -> [SKIP][20] ([i915#2190])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb4/igt@gem_huc_copy@huc-copy.html
* igt@gem_pread@exhaustion:
- shard-apl: NOTRUN -> [WARN][21] ([i915#2658])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-apl1/igt@gem_pread@exhaustion.html
* igt@gem_pwrite@basic-exhaustion:
- shard-tglb: NOTRUN -> [WARN][22] ([i915#2658])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb3/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_softpin@evict-snoop:
- shard-tglb: NOTRUN -> [SKIP][23] ([fdo#109312])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb8/igt@gem_softpin@evict-snoop.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-kbl: NOTRUN -> [SKIP][24] ([fdo#109271] / [i915#3323])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-kbl3/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@unsync-unmap-after-close:
- shard-tglb: NOTRUN -> [SKIP][25] ([i915#3297]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb8/igt@gem_userptr_blits@unsync-unmap-after-close.html
* igt@gen7_exec_parse@basic-allowed:
- shard-tglb: NOTRUN -> [SKIP][26] ([fdo#109289]) +1 similar issue
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb3/igt@gen7_exec_parse@basic-allowed.html
* igt@gen9_exec_parse@cmd-crossing-page:
- shard-tglb: NOTRUN -> [SKIP][27] ([i915#2856]) +2 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb1/igt@gen9_exec_parse@cmd-crossing-page.html
- shard-iclb: NOTRUN -> [SKIP][28] ([i915#2856])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb8/igt@gen9_exec_parse@cmd-crossing-page.html
* igt@i915_pm_rc6_residency@media-rc6-accuracy:
- shard-iclb: NOTRUN -> [SKIP][29] ([fdo#109289])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb8/igt@i915_pm_rc6_residency@media-rc6-accuracy.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-tglb: NOTRUN -> [WARN][30] ([i915#2681])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb8/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-tglb: NOTRUN -> [SKIP][31] ([fdo#111644] / [i915#1397] / [i915#2411]) +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb8/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@i915_pm_rpm@pc8-residency:
- shard-iclb: NOTRUN -> [SKIP][32] ([fdo#109293] / [fdo#109506])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb4/igt@i915_pm_rpm@pc8-residency.html
* igt@i915_selftest@live@gt_lrc:
- shard-tglb: NOTRUN -> [DMESG-FAIL][33] ([i915#2373])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb6/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@gt_pm:
- shard-tglb: NOTRUN -> [DMESG-FAIL][34] ([i915#1759] / [i915#2291])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb6/igt@i915_selftest@live@gt_pm.html
* igt@kms_big_fb@linear-32bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][35] ([fdo#110725] / [fdo#111614])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb8/igt@kms_big_fb@linear-32bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-8bpp-rotate-90:
- shard-tglb: NOTRUN -> [SKIP][36] ([fdo#111614]) +2 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb3/igt@kms_big_fb@x-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-apl: NOTRUN -> [SKIP][37] ([fdo#109271] / [i915#3777]) +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-apl8/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-kbl: NOTRUN -> [SKIP][38] ([fdo#109271] / [i915#3777]) +1 similar issue
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-kbl7/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-270:
- shard-tglb: NOTRUN -> [SKIP][39] ([fdo#111615]) +7 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb8/igt@kms_big_fb@yf-tiled-64bpp-rotate-270.html
* igt@kms_big_joiner@2x-modeset:
- shard-iclb: NOTRUN -> [SKIP][40] ([i915#2705])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb8/igt@kms_big_joiner@2x-modeset.html
* igt@kms_big_joiner@basic:
- shard-tglb: NOTRUN -> [SKIP][41] ([i915#2705]) +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb8/igt@kms_big_joiner@basic.html
* igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][42] ([i915#3689] / [i915#3886]) +7 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb8/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs:
- shard-iclb: NOTRUN -> [SKIP][43] ([fdo#109278] / [i915#3886]) +2 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb8/igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][44] ([fdo#109271] / [i915#3886]) +8 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-kbl6/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
- shard-apl: NOTRUN -> [SKIP][45] ([fdo#109271] / [i915#3886]) +3 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-apl8/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-d-crc-primary-basic-y_tiled_gen12_mc_ccs:
- shard-iclb: NOTRUN -> [SKIP][46] ([fdo#109278]) +11 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb8/igt@kms_ccs@pipe-d-crc-primary-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-d-crc-primary-rotation-180-yf_tiled_ccs:
- shard-apl: NOTRUN -> [SKIP][47] ([fdo#109271]) +181 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-apl2/igt@kms_ccs@pipe-d-crc-primary-rotation-180-yf_tiled_ccs.html
* igt@kms_ccs@pipe-d-crc-sprite-planes-basic-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][48] ([i915#3689]) +15 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb6/igt@kms_ccs@pipe-d-crc-sprite-planes-basic-y_tiled_ccs.html
* igt@kms_cdclk@mode-transition:
- shard-tglb: NOTRUN -> [SKIP][49] ([i915#3742])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb8/igt@kms_cdclk@mode-transition.html
* igt@kms_chamelium@hdmi-audio-edid:
- shard-kbl: NOTRUN -> [SKIP][50] ([fdo#109271] / [fdo#111827]) +18 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-kbl2/igt@kms_chamelium@hdmi-audio-edid.html
* igt@kms_chamelium@hdmi-crc-fast:
- shard-iclb: NOTRUN -> [SKIP][51] ([fdo#109284] / [fdo#111827]) +1 similar issue
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb8/igt@kms_chamelium@hdmi-crc-fast.html
- shard-skl: NOTRUN -> [SKIP][52] ([fdo#109271] / [fdo#111827]) +1 similar issue
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-skl1/igt@kms_chamelium@hdmi-crc-fast.html
* igt@kms_chamelium@hdmi-edid-read:
- shard-tglb: NOTRUN -> [SKIP][53] ([fdo#109284] / [fdo#111827]) +16 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb6/igt@kms_chamelium@hdmi-edid-read.html
* igt@kms_chamelium@vga-hpd-for-each-pipe:
- shard-apl: NOTRUN -> [SKIP][54] ([fdo#109271] / [fdo#111827]) +9 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-apl8/igt@kms_chamelium@vga-hpd-for-each-pipe.html
* igt@kms_color_chamelium@pipe-a-ctm-blue-to-red:
- shard-snb: NOTRUN -> [SKIP][55] ([fdo#109271] / [fdo#111827]) +23 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-snb6/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html
* igt@kms_content_protection@atomic:
- shard-kbl: NOTRUN -> [TIMEOUT][56] ([i915#1319]) +1 similar issue
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-kbl2/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@dp-mst-type-0:
- shard-tglb: NOTRUN -> [SKIP][57] ([i915#3116]) +2 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb8/igt@kms_content_protection@dp-mst-type-0.html
* igt@kms_content_protection@legacy:
- shard-tglb: NOTRUN -> [SKIP][58] ([fdo#111828]) +1 similar issue
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb8/igt@kms_content_protection@legacy.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-tglb: [PASS][59] -> [INCOMPLETE][60] ([i915#2828] / [i915#456])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-tglb1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-b-cursor-128x128-random:
- shard-skl: NOTRUN -> [SKIP][61] ([fdo#109271]) +44 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-skl1/igt@kms_cursor_crc@pipe-b-cursor-128x128-random.html
* igt@kms_cursor_crc@pipe-b-cursor-32x32-sliding:
- shard-tglb: NOTRUN -> [SKIP][62] ([i915#3319]) +1 similar issue
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb6/igt@kms_cursor_crc@pipe-b-cursor-32x32-sliding.html
* igt@kms_cursor_crc@pipe-c-cursor-512x170-offscreen:
- shard-iclb: NOTRUN -> [SKIP][63] ([fdo#109278] / [fdo#109279]) +1 similar issue
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb5/igt@kms_cursor_crc@pipe-c-cursor-512x170-offscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-max-size-onscreen:
- shard-tglb: NOTRUN -> [SKIP][64] ([i915#3359]) +6 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb6/igt@kms_cursor_crc@pipe-c-cursor-max-size-onscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-256x256-onscreen:
- shard-kbl: NOTRUN -> [SKIP][65] ([fdo#109271]) +224 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-kbl3/igt@kms_cursor_crc@pipe-d-cursor-256x256-onscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-512x512-offscreen:
- shard-tglb: NOTRUN -> [SKIP][66] ([fdo#109279] / [i915#3359]) +5 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb3/igt@kms_cursor_crc@pipe-d-cursor-512x512-offscreen.html
* igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic:
- shard-iclb: NOTRUN -> [SKIP][67] ([fdo#109274] / [fdo#109278]) +2 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb4/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@pipe-d-torture-bo:
- shard-apl: NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#533]) +1 similar issue
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-apl1/igt@kms_cursor_legacy@pipe-d-torture-bo.html
* igt@kms_dp_tiled_display@basic-test-pattern-with-chamelium:
- shard-tglb: NOTRUN -> [SKIP][69] ([i915#3528])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb6/igt@kms_dp_tiled_display@basic-test-pattern-with-chamelium.html
* igt@kms_flip@2x-flip-vs-panning-interruptible:
- shard-iclb: NOTRUN -> [SKIP][70] ([fdo#109274]) +2 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb8/igt@kms_flip@2x-flip-vs-panning-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-skl: [PASS][71] -> [FAIL][72] ([i915#79]) +1 similar issue
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-skl3/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_flip@flip-vs-suspend@c-dp1:
- shard-kbl: NOTRUN -> [DMESG-WARN][73] ([i915#180]) +2 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-kbl7/igt@kms_flip@flip-vs-suspend@c-dp1.html
* igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1:
- shard-skl: [PASS][74] -> [FAIL][75] ([i915#2122])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-skl4/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-skl6/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
- shard-apl: NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#2672])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-apl8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile:
- shard-snb: NOTRUN -> [SKIP][77] ([fdo#109271]) +445 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-snb7/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc:
- shard-tglb: NOTRUN -> [SKIP][78] ([fdo#111825]) +44 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-iclb: NOTRUN -> [SKIP][79] ([fdo#109280]) +11 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-cpu.html
* igt@kms_hdr@static-toggle-dpms:
- shard-tglb: NOTRUN -> [SKIP][80] ([i915#1187])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb3/igt@kms_hdr@static-toggle-dpms.html
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence:
- shard-kbl: NOTRUN -> [SKIP][81] ([fdo#109271] / [i915#533]) +2 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-kbl4/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
- shard-apl: NOTRUN -> [FAIL][82] ([fdo#108145] / [i915#265])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-apl8/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-kbl: NOTRUN -> [FAIL][83] ([fdo#108145] / [i915#265]) +3 similar issues
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-kbl3/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-kbl: NOTRUN -> [FAIL][84] ([i915#265]) +1 similar issue
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-kbl2/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_plane_lowres@pipe-c-tiling-y:
- shard-tglb: NOTRUN -> [SKIP][85] ([i915#3536])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb8/igt@kms_plane_lowres@pipe-c-tiling-y.html
* igt@kms_plane_multiple@atomic-pipe-d-tiling-yf:
- shard-tglb: NOTRUN -> [SKIP][86] ([fdo#112054]) +1 similar issue
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb8/igt@kms_plane_multiple@atomic-pipe-d-tiling-yf.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1:
- shard-apl: NOTRUN -> [SKIP][87] ([fdo#109271] / [i915#658]) +1 similar issue
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-apl1/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3:
- shard-glk: NOTRUN -> [SKIP][88] ([fdo#109271] / [i915#658]) +1 similar issue
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-glk9/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-0:
- shard-tglb: NOTRUN -> [SKIP][89] ([i915#2920]) +4 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb8/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1:
- shard-kbl: NOTRUN -> [SKIP][90] ([fdo#109271] / [i915#658]) +2 similar issues
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-kbl2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2:
- shard-iclb: NOTRUN -> [SKIP][91] ([i915#658]) +1 similar issue
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb5/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][92] -> [SKIP][93] ([fdo#109441]) +2 similar issues
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb8/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_psr@psr2_sprite_render:
- shard-tglb: NOTRUN -> [FAIL][94] ([i915#132] / [i915#3467]) +2 similar issues
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb8/igt@kms_psr@psr2_sprite_render.html
* igt@kms_psr@sprite_mmap_cpu:
- shard-glk: NOTRUN -> [SKIP][95] ([fdo#109271]) +13 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-glk9/igt@kms_psr@sprite_mmap_cpu.html
* igt@kms_sysfs_edid_timing:
- shard-kbl: NOTRUN -> [FAIL][96] ([IGT#2])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-kbl2/igt@kms_sysfs_edid_timing.html
* igt@kms_vrr@flip-dpms:
- shard-tglb: NOTRUN -> [SKIP][97] ([fdo#109502])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb8/igt@kms_vrr@flip-dpms.html
* igt@kms_writeback@writeback-check-output:
- shard-apl: NOTRUN -> [SKIP][98] ([fdo#109271] / [i915#2437]) +2 similar issues
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-apl2/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-kbl: NOTRUN -> [SKIP][99] ([fdo#109271] / [i915#2437])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-kbl6/igt@kms_writeback@writeback-pixel-formats.html
* igt@nouveau_crc@pipe-a-ctx-flip-skip-current-frame:
- shard-iclb: NOTRUN -> [SKIP][100] ([i915#2530])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb5/igt@nouveau_crc@pipe-a-ctx-flip-skip-current-frame.html
* igt@nouveau_crc@pipe-d-ctx-flip-detection:
- shard-tglb: NOTRUN -> [SKIP][101] ([i915#2530]) +5 similar issues
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb6/igt@nouveau_crc@pipe-d-ctx-flip-detection.html
* igt@nouveau_crc@pipe-d-source-rg:
- shard-iclb: NOTRUN -> [SKIP][102] ([fdo#109278] / [i915#2530])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb8/igt@nouveau_crc@pipe-d-source-rg.html
* igt@prime_nv_api@nv_i915_reimport_twice_check_flink_name:
- shard-iclb: NOTRUN -> [SKIP][103] ([fdo#109291]) +1 similar issue
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb8/igt@prime_nv_api@nv_i915_reimport_twice_check_flink_name.html
* igt@prime_nv_pcopy@test1_macro:
- shard-tglb: NOTRUN -> [SKIP][104] ([fdo#109291]) +8 similar issues
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb8/igt@prime_nv_pcopy@test1_macro.html
* igt@prime_vgem@fence-flip-hang:
- shard-iclb: NOTRUN -> [SKIP][105] ([fdo#109295])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb8/igt@prime_vgem@fence-flip-hang.html
- shard-tglb: NOTRUN -> [SKIP][106] ([fdo#109295])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb1/igt@prime_vgem@fence-flip-hang.html
* igt@sysfs_clients@fair-3:
- shard-apl: NOTRUN -> [SKIP][107] ([fdo#109271] / [i915#2994])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-apl1/igt@sysfs_clients@fair-3.html
* igt@sysfs_clients@recycle-many:
- shard-kbl: NOTRUN -> [SKIP][108] ([fdo#109271] / [i915#2994])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-kbl2/igt@sysfs_clients@recycle-many.html
* igt@sysfs_clients@sema-10:
- shard-tglb: NOTRUN -> [SKIP][109] ([i915#2994]) +3 similar issues
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb8/igt@sysfs_clients@sema-10.html
#### Possible fixes ####
* igt@core_hotunplug@unbind-rebind:
- shard-glk: [INCOMPLETE][110] ([i915#4130] / [i915#4136]) -> [PASS][111]
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-glk1/igt@core_hotunplug@unbind-rebind.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-glk9/igt@core_hotunplug@unbind-rebind.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-glk: [FAIL][112] ([i915#2842]) -> [PASS][113]
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-glk3/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-glk2/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fence@basic-await@bcs0:
- shard-tglb: [INCOMPLETE][114] -> [PASS][115]
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-tglb1/igt@gem_exec_fence@basic-await@bcs0.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb1/igt@gem_exec_fence@basic-await@bcs0.html
* igt@gem_exec_suspend@basic-s3:
- shard-apl: [INCOMPLETE][116] -> [PASS][117]
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-apl3/igt@gem_exec_suspend@basic-s3.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-apl3/igt@gem_exec_suspend@basic-s3.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-apl: [DMESG-WARN][118] ([i915#180]) -> [PASS][119]
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-apl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-apl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-tglb: [INCOMPLETE][120] ([i915#456]) -> [PASS][121]
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-tglb7/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb8/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_flip@bo-too-big-interruptible@b-edp1:
- shard-iclb: [INCOMPLETE][122] -> [PASS][123]
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-iclb7/igt@kms_flip@bo-too-big-interruptible@b-edp1.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb5/igt@kms_flip@bo-too-big-interruptible@b-edp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile:
- shard-iclb: [SKIP][124] ([i915#3701]) -> [PASS][125]
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb8/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile.html
* igt@kms_frontbuffer_tracking@fbcpsr-suspend:
- shard-tglb: [INCOMPLETE][126] ([i915#2411] / [i915#456]) -> [PASS][127] +1 similar issue
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [FAIL][128] ([i915#1188]) -> [PASS][129]
[128]
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/index.html
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^ permalink raw reply [flat|nested] 39+ messages in thread* Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Suspend / resume backup- and restore of LMEM. (rev9)
2021-09-22 9:05 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2021-09-22 18:06 ` Thomas Hellström
2021-09-23 2:11 ` Vudum, Lakshminarayana
0 siblings, 1 reply; 39+ messages in thread
From: Thomas Hellström @ 2021-09-22 18:06 UTC (permalink / raw)
To: intel-gfx, , Lakshminarayana Vudum
[-- Attachment #1: Type: text/plain, Size: 1809 bytes --]
On 9/22/21 11:05 AM, Patchwork wrote:
> Project List - Patchwork *Patch Details*
> *Series:* drm/i915: Suspend / resume backup- and restore of LMEM. (rev9)
> *URL:* https://patchwork.freedesktop.org/series/94278/
> <https://patchwork.freedesktop.org/series/94278/>
> *State:* failure
> *Details:*
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/index.html
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/index.html>
>
>
> CI Bug Log - changes from CI_DRM_10622_full -> Patchwork_21124_full
>
>
> Summary
>
> *FAILURE*
>
> Serious unknown changes coming with Patchwork_21124_full absolutely
> need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_21124_full, please notify your bug team to
> allow them
> to document this new failure mode, which will reduce false positives
> in CI.
>
>
> Possible new issues
>
> Here are the unknown changes that may have been introduced in
> Patchwork_21124_full:
>
>
> IGT changes
>
>
> Possible regressions
>
> * igt@gem_exec_schedule@u-submit-golden-slice@rcs0:
> o shard-tglb: PASS
> <https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-tglb3/igt@gem_exec_schedule@u-submit-golden-slice@rcs0.html>
> -> INCOMPLETE
> <https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb6/igt@gem_exec_schedule@u-submit-golden-slice@rcs0.html>
>
>
Lakshmi, this failure is unrelated.
The igt@gem_exec_schedule@u-submit-golden-slice plus some other subtests
have been broken since igt commit
a9987a8d tests/i915/gem_exec_schedule: Convert to intel_ctx_t (v3)
Although the tests typically says SUCCESS, it's because they typically
are interrupted by the watchdog and move on.
Thanks,
Thomas
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^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Suspend / resume backup- and restore of LMEM. (rev9)
2021-09-22 18:06 ` Thomas Hellström
@ 2021-09-23 2:11 ` Vudum, Lakshminarayana
0 siblings, 0 replies; 39+ messages in thread
From: Vudum, Lakshminarayana @ 2021-09-23 2:11 UTC (permalink / raw)
To: Thomas Hellström, intel-gfx
[-- Attachment #1: Type: text/plain, Size: 2045 bytes --]
Failure is related to https://gitlab.freedesktop.org/drm/intel/-/issues/3797. I have re-reported the results after updating the CI bug log filters.
Lakshmi.
From: Thomas Hellström <thomas.hellstrom@linux.intel.com>
Sent: Wednesday, September 22, 2021 11:07 AM
To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana <lakshminarayana.vudum@intel.com>
Subject: Re: ✗ Fi.CI.IGT: failure for drm/i915: Suspend / resume backup- and restore of LMEM. (rev9)
On 9/22/21 11:05 AM, Patchwork wrote:
Patch Details
Series:
drm/i915: Suspend / resume backup- and restore of LMEM. (rev9)
URL:
https://patchwork.freedesktop.org/series/94278/
State:
failure
Details:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/index.html
CI Bug Log - changes from CI_DRM_10622_full -> Patchwork_21124_full
Summary
FAILURE
Serious unknown changes coming with Patchwork_21124_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_21124_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
Here are the unknown changes that may have been introduced in Patchwork_21124_full:
IGT changes
Possible regressions
* igt@gem_exec_schedule@u-submit-golden-slice@rcs0:
* shard-tglb: PASS<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-tglb3/igt@gem_exec_schedule@u-submit-golden-slice@rcs0.html> -> INCOMPLETE<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb6/igt@gem_exec_schedule@u-submit-golden-slice@rcs0.html>
Lakshmi, this failure is unrelated.
The igt@gem_exec_schedule@u-submit-golden-slice plus some other subtests have been broken since igt commit
a9987a8d tests/i915/gem_exec_schedule: Convert to intel_ctx_t (v3)
Although the tests typically says SUCCESS, it's because they typically are interrupted by the watchdog and move on.
Thanks,
Thomas
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^ permalink raw reply [flat|nested] 39+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Suspend / resume backup- and restore of LMEM. (rev9)
2021-09-22 6:25 ` [Intel-gfx] " Thomas Hellström
` (13 preceding siblings ...)
(?)
@ 2021-09-23 0:27 ` Patchwork
-1 siblings, 0 replies; 39+ messages in thread
From: Patchwork @ 2021-09-23 0:27 UTC (permalink / raw)
To: Thomas Hellström; +Cc: intel-gfx
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== Series Details ==
Series: drm/i915: Suspend / resume backup- and restore of LMEM. (rev9)
URL : https://patchwork.freedesktop.org/series/94278/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10622_full -> Patchwork_21124_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_21124_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- {shard-rkl}: NOTRUN -> [SKIP][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-rkl-6/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
Known issues
------------
Here are the changes found in Patchwork_21124_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_create@create-massive:
- shard-apl: NOTRUN -> [DMESG-WARN][2] ([i915#3002])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-apl1/igt@gem_create@create-massive.html
* igt@gem_ctx_isolation@preservation-s3@vecs0:
- shard-skl: [PASS][3] -> [INCOMPLETE][4] ([i915#146] / [i915#198])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-skl1/igt@gem_ctx_isolation@preservation-s3@vecs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-skl10/igt@gem_ctx_isolation@preservation-s3@vecs0.html
* igt@gem_ctx_persistence@engines-mixed:
- shard-snb: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#1099]) +4 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-snb2/igt@gem_ctx_persistence@engines-mixed.html
* igt@gem_eio@in-flight-1us:
- shard-skl: [PASS][6] -> [TIMEOUT][7] ([i915#3063])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-skl1/igt@gem_eio@in-flight-1us.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-skl9/igt@gem_eio@in-flight-1us.html
* igt@gem_eio@unwedge-stress:
- shard-iclb: [PASS][8] -> [TIMEOUT][9] ([i915#2369] / [i915#2481] / [i915#3070])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-iclb4/igt@gem_eio@unwedge-stress.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb3/igt@gem_eio@unwedge-stress.html
- shard-snb: NOTRUN -> [FAIL][10] ([i915#3354])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-snb6/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-none@rcs0:
- shard-glk: NOTRUN -> [FAIL][11] ([i915#2842])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-glk9/igt@gem_exec_fair@basic-none@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-tglb: NOTRUN -> [FAIL][12] ([i915#2842]) +4 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb8/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-iclb: NOTRUN -> [FAIL][13] ([i915#2842]) +3 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb5/igt@gem_exec_fair@basic-none@vecs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][14] -> [FAIL][15] ([i915#2842])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-glk9/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][16] -> [FAIL][17] ([i915#2849])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-iclb2/igt@gem_exec_fair@basic-throttle@rcs0.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb7/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_params@no-blt:
- shard-tglb: NOTRUN -> [SKIP][18] ([fdo#109283])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb6/igt@gem_exec_params@no-blt.html
* igt@gem_exec_schedule@u-submit-golden-slice@rcs0:
- shard-tglb: [PASS][19] -> [INCOMPLETE][20] ([i915#3797])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-tglb3/igt@gem_exec_schedule@u-submit-golden-slice@rcs0.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb6/igt@gem_exec_schedule@u-submit-golden-slice@rcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-iclb: NOTRUN -> [SKIP][21] ([i915#2190])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb4/igt@gem_huc_copy@huc-copy.html
* igt@gem_pread@exhaustion:
- shard-apl: NOTRUN -> [WARN][22] ([i915#2658])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-apl1/igt@gem_pread@exhaustion.html
* igt@gem_pwrite@basic-exhaustion:
- shard-tglb: NOTRUN -> [WARN][23] ([i915#2658])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb3/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_softpin@evict-snoop:
- shard-tglb: NOTRUN -> [SKIP][24] ([fdo#109312])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb8/igt@gem_softpin@evict-snoop.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-kbl: NOTRUN -> [SKIP][25] ([fdo#109271] / [i915#3323])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-kbl3/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@unsync-unmap-after-close:
- shard-tglb: NOTRUN -> [SKIP][26] ([i915#3297]) +1 similar issue
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb8/igt@gem_userptr_blits@unsync-unmap-after-close.html
* igt@gen7_exec_parse@basic-allowed:
- shard-tglb: NOTRUN -> [SKIP][27] ([fdo#109289]) +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb3/igt@gen7_exec_parse@basic-allowed.html
* igt@gen9_exec_parse@cmd-crossing-page:
- shard-tglb: NOTRUN -> [SKIP][28] ([i915#2856]) +2 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb1/igt@gen9_exec_parse@cmd-crossing-page.html
- shard-iclb: NOTRUN -> [SKIP][29] ([i915#2856])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb8/igt@gen9_exec_parse@cmd-crossing-page.html
* igt@i915_pm_rc6_residency@media-rc6-accuracy:
- shard-iclb: NOTRUN -> [SKIP][30] ([fdo#109289])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb8/igt@i915_pm_rc6_residency@media-rc6-accuracy.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-tglb: NOTRUN -> [WARN][31] ([i915#2681])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb8/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-tglb: NOTRUN -> [SKIP][32] ([fdo#111644] / [i915#1397] / [i915#2411]) +1 similar issue
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb8/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@i915_pm_rpm@pc8-residency:
- shard-iclb: NOTRUN -> [SKIP][33] ([fdo#109293] / [fdo#109506])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb4/igt@i915_pm_rpm@pc8-residency.html
* igt@i915_selftest@live@gt_lrc:
- shard-tglb: NOTRUN -> [DMESG-FAIL][34] ([i915#2373])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb6/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@gt_pm:
- shard-tglb: NOTRUN -> [DMESG-FAIL][35] ([i915#1759] / [i915#2291])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb6/igt@i915_selftest@live@gt_pm.html
* igt@kms_big_fb@linear-32bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][36] ([fdo#110725] / [fdo#111614])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb8/igt@kms_big_fb@linear-32bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-8bpp-rotate-90:
- shard-tglb: NOTRUN -> [SKIP][37] ([fdo#111614]) +2 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb3/igt@kms_big_fb@x-tiled-8bpp-rotate-90.html
* igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip:
- shard-apl: NOTRUN -> [SKIP][38] ([fdo#109271] / [i915#3777]) +1 similar issue
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-apl8/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-kbl: NOTRUN -> [SKIP][39] ([fdo#109271] / [i915#3777]) +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-kbl7/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-270:
- shard-tglb: NOTRUN -> [SKIP][40] ([fdo#111615]) +7 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb8/igt@kms_big_fb@yf-tiled-64bpp-rotate-270.html
* igt@kms_big_joiner@2x-modeset:
- shard-iclb: NOTRUN -> [SKIP][41] ([i915#2705])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb8/igt@kms_big_joiner@2x-modeset.html
* igt@kms_big_joiner@basic:
- shard-tglb: NOTRUN -> [SKIP][42] ([i915#2705]) +1 similar issue
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb8/igt@kms_big_joiner@basic.html
* igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][43] ([i915#3689] / [i915#3886]) +7 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb8/igt@kms_ccs@pipe-b-bad-rotation-90-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs:
- shard-iclb: NOTRUN -> [SKIP][44] ([fdo#109278] / [i915#3886]) +2 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb8/igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
- shard-kbl: NOTRUN -> [SKIP][45] ([fdo#109271] / [i915#3886]) +8 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-kbl6/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
- shard-apl: NOTRUN -> [SKIP][46] ([fdo#109271] / [i915#3886]) +3 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-apl8/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-d-crc-primary-basic-y_tiled_gen12_mc_ccs:
- shard-iclb: NOTRUN -> [SKIP][47] ([fdo#109278]) +11 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb8/igt@kms_ccs@pipe-d-crc-primary-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-d-crc-primary-rotation-180-yf_tiled_ccs:
- shard-apl: NOTRUN -> [SKIP][48] ([fdo#109271]) +181 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-apl2/igt@kms_ccs@pipe-d-crc-primary-rotation-180-yf_tiled_ccs.html
* igt@kms_ccs@pipe-d-crc-sprite-planes-basic-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][49] ([i915#3689]) +15 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb6/igt@kms_ccs@pipe-d-crc-sprite-planes-basic-y_tiled_ccs.html
* igt@kms_cdclk@mode-transition:
- shard-tglb: NOTRUN -> [SKIP][50] ([i915#3742])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb8/igt@kms_cdclk@mode-transition.html
* igt@kms_chamelium@hdmi-audio-edid:
- shard-kbl: NOTRUN -> [SKIP][51] ([fdo#109271] / [fdo#111827]) +18 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-kbl2/igt@kms_chamelium@hdmi-audio-edid.html
* igt@kms_chamelium@hdmi-crc-fast:
- shard-iclb: NOTRUN -> [SKIP][52] ([fdo#109284] / [fdo#111827]) +1 similar issue
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb8/igt@kms_chamelium@hdmi-crc-fast.html
- shard-skl: NOTRUN -> [SKIP][53] ([fdo#109271] / [fdo#111827]) +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-skl1/igt@kms_chamelium@hdmi-crc-fast.html
* igt@kms_chamelium@hdmi-edid-read:
- shard-tglb: NOTRUN -> [SKIP][54] ([fdo#109284] / [fdo#111827]) +16 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb6/igt@kms_chamelium@hdmi-edid-read.html
* igt@kms_chamelium@vga-hpd-for-each-pipe:
- shard-apl: NOTRUN -> [SKIP][55] ([fdo#109271] / [fdo#111827]) +9 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-apl8/igt@kms_chamelium@vga-hpd-for-each-pipe.html
* igt@kms_color_chamelium@pipe-a-ctm-blue-to-red:
- shard-snb: NOTRUN -> [SKIP][56] ([fdo#109271] / [fdo#111827]) +23 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-snb6/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html
* igt@kms_content_protection@atomic:
- shard-kbl: NOTRUN -> [TIMEOUT][57] ([i915#1319]) +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-kbl2/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@dp-mst-type-0:
- shard-tglb: NOTRUN -> [SKIP][58] ([i915#3116]) +2 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb8/igt@kms_content_protection@dp-mst-type-0.html
* igt@kms_content_protection@legacy:
- shard-tglb: NOTRUN -> [SKIP][59] ([fdo#111828]) +1 similar issue
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb8/igt@kms_content_protection@legacy.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-tglb: [PASS][60] -> [INCOMPLETE][61] ([i915#2828] / [i915#456])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-tglb1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-b-cursor-128x128-random:
- shard-skl: NOTRUN -> [SKIP][62] ([fdo#109271]) +44 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-skl1/igt@kms_cursor_crc@pipe-b-cursor-128x128-random.html
* igt@kms_cursor_crc@pipe-b-cursor-32x32-sliding:
- shard-tglb: NOTRUN -> [SKIP][63] ([i915#3319]) +1 similar issue
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb6/igt@kms_cursor_crc@pipe-b-cursor-32x32-sliding.html
* igt@kms_cursor_crc@pipe-c-cursor-512x170-offscreen:
- shard-iclb: NOTRUN -> [SKIP][64] ([fdo#109278] / [fdo#109279]) +1 similar issue
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb5/igt@kms_cursor_crc@pipe-c-cursor-512x170-offscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-max-size-onscreen:
- shard-tglb: NOTRUN -> [SKIP][65] ([i915#3359]) +6 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb6/igt@kms_cursor_crc@pipe-c-cursor-max-size-onscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-256x256-onscreen:
- shard-kbl: NOTRUN -> [SKIP][66] ([fdo#109271]) +224 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-kbl3/igt@kms_cursor_crc@pipe-d-cursor-256x256-onscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-512x512-offscreen:
- shard-tglb: NOTRUN -> [SKIP][67] ([fdo#109279] / [i915#3359]) +5 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb3/igt@kms_cursor_crc@pipe-d-cursor-512x512-offscreen.html
* igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic:
- shard-iclb: NOTRUN -> [SKIP][68] ([fdo#109274] / [fdo#109278]) +2 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb4/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@pipe-d-torture-bo:
- shard-apl: NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#533]) +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-apl1/igt@kms_cursor_legacy@pipe-d-torture-bo.html
* igt@kms_dp_tiled_display@basic-test-pattern-with-chamelium:
- shard-tglb: NOTRUN -> [SKIP][70] ([i915#3528])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb6/igt@kms_dp_tiled_display@basic-test-pattern-with-chamelium.html
* igt@kms_flip@2x-flip-vs-panning-interruptible:
- shard-iclb: NOTRUN -> [SKIP][71] ([fdo#109274]) +2 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb8/igt@kms_flip@2x-flip-vs-panning-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-skl: [PASS][72] -> [FAIL][73] ([i915#79]) +1 similar issue
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-skl9/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-skl3/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_flip@flip-vs-suspend@c-dp1:
- shard-kbl: NOTRUN -> [DMESG-WARN][74] ([i915#180]) +2 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-kbl7/igt@kms_flip@flip-vs-suspend@c-dp1.html
* igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1:
- shard-skl: [PASS][75] -> [FAIL][76] ([i915#2122])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-skl4/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-skl6/igt@kms_flip@plain-flip-ts-check-interruptible@b-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
- shard-apl: NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#2672])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-apl8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile:
- shard-snb: NOTRUN -> [SKIP][78] ([fdo#109271]) +445 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-snb7/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc:
- shard-tglb: NOTRUN -> [SKIP][79] ([fdo#111825]) +44 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-iclb: NOTRUN -> [SKIP][80] ([fdo#109280]) +11 similar issues
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-cpu.html
* igt@kms_hdr@static-toggle-dpms:
- shard-tglb: NOTRUN -> [SKIP][81] ([i915#1187])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb3/igt@kms_hdr@static-toggle-dpms.html
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence:
- shard-kbl: NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#533]) +2 similar issues
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-kbl4/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
- shard-apl: NOTRUN -> [FAIL][83] ([fdo#108145] / [i915#265])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-apl8/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-kbl: NOTRUN -> [FAIL][84] ([fdo#108145] / [i915#265]) +3 similar issues
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-kbl3/igt@kms_plane_alpha_blend@pipe-c-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-kbl: NOTRUN -> [FAIL][85] ([i915#265]) +1 similar issue
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-kbl2/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_plane_lowres@pipe-c-tiling-y:
- shard-tglb: NOTRUN -> [SKIP][86] ([i915#3536])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb8/igt@kms_plane_lowres@pipe-c-tiling-y.html
* igt@kms_plane_multiple@atomic-pipe-d-tiling-yf:
- shard-tglb: NOTRUN -> [SKIP][87] ([fdo#112054]) +1 similar issue
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb8/igt@kms_plane_multiple@atomic-pipe-d-tiling-yf.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1:
- shard-apl: NOTRUN -> [SKIP][88] ([fdo#109271] / [i915#658]) +1 similar issue
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-apl1/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3:
- shard-glk: NOTRUN -> [SKIP][89] ([fdo#109271] / [i915#658]) +1 similar issue
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-glk9/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-3.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area-0:
- shard-tglb: NOTRUN -> [SKIP][90] ([i915#2920]) +4 similar issues
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb8/igt@kms_psr2_sf@plane-move-sf-dmg-area-0.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1:
- shard-kbl: NOTRUN -> [SKIP][91] ([fdo#109271] / [i915#658]) +2 similar issues
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-kbl2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2:
- shard-iclb: NOTRUN -> [SKIP][92] ([i915#658]) +1 similar issue
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb5/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [PASS][93] -> [SKIP][94] ([fdo#109441]) +2 similar issues
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb8/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_psr@psr2_sprite_render:
- shard-tglb: NOTRUN -> [FAIL][95] ([i915#132] / [i915#3467]) +2 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb8/igt@kms_psr@psr2_sprite_render.html
* igt@kms_psr@sprite_mmap_cpu:
- shard-glk: NOTRUN -> [SKIP][96] ([fdo#109271]) +13 similar issues
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-glk9/igt@kms_psr@sprite_mmap_cpu.html
* igt@kms_sysfs_edid_timing:
- shard-kbl: NOTRUN -> [FAIL][97] ([IGT#2])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-kbl2/igt@kms_sysfs_edid_timing.html
* igt@kms_vrr@flip-dpms:
- shard-tglb: NOTRUN -> [SKIP][98] ([fdo#109502])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb8/igt@kms_vrr@flip-dpms.html
* igt@kms_writeback@writeback-check-output:
- shard-apl: NOTRUN -> [SKIP][99] ([fdo#109271] / [i915#2437]) +2 similar issues
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-apl2/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-kbl: NOTRUN -> [SKIP][100] ([fdo#109271] / [i915#2437])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-kbl6/igt@kms_writeback@writeback-pixel-formats.html
* igt@nouveau_crc@pipe-a-ctx-flip-skip-current-frame:
- shard-iclb: NOTRUN -> [SKIP][101] ([i915#2530])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb5/igt@nouveau_crc@pipe-a-ctx-flip-skip-current-frame.html
* igt@nouveau_crc@pipe-d-ctx-flip-detection:
- shard-tglb: NOTRUN -> [SKIP][102] ([i915#2530]) +5 similar issues
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb6/igt@nouveau_crc@pipe-d-ctx-flip-detection.html
* igt@nouveau_crc@pipe-d-source-rg:
- shard-iclb: NOTRUN -> [SKIP][103] ([fdo#109278] / [i915#2530])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb8/igt@nouveau_crc@pipe-d-source-rg.html
* igt@prime_nv_api@nv_i915_reimport_twice_check_flink_name:
- shard-iclb: NOTRUN -> [SKIP][104] ([fdo#109291]) +1 similar issue
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb8/igt@prime_nv_api@nv_i915_reimport_twice_check_flink_name.html
* igt@prime_nv_pcopy@test1_macro:
- shard-tglb: NOTRUN -> [SKIP][105] ([fdo#109291]) +8 similar issues
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb8/igt@prime_nv_pcopy@test1_macro.html
* igt@prime_vgem@fence-flip-hang:
- shard-iclb: NOTRUN -> [SKIP][106] ([fdo#109295])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb8/igt@prime_vgem@fence-flip-hang.html
- shard-tglb: NOTRUN -> [SKIP][107] ([fdo#109295])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb1/igt@prime_vgem@fence-flip-hang.html
* igt@sysfs_clients@fair-3:
- shard-apl: NOTRUN -> [SKIP][108] ([fdo#109271] / [i915#2994])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-apl1/igt@sysfs_clients@fair-3.html
* igt@sysfs_clients@recycle-many:
- shard-kbl: NOTRUN -> [SKIP][109] ([fdo#109271] / [i915#2994])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-kbl2/igt@sysfs_clients@recycle-many.html
* igt@sysfs_clients@sema-10:
- shard-tglb: NOTRUN -> [SKIP][110] ([i915#2994]) +3 similar issues
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb8/igt@sysfs_clients@sema-10.html
#### Possible fixes ####
* igt@core_hotunplug@unbind-rebind:
- shard-glk: [INCOMPLETE][111] ([i915#4130] / [i915#4136]) -> [PASS][112]
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-glk1/igt@core_hotunplug@unbind-rebind.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-glk9/igt@core_hotunplug@unbind-rebind.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-glk: [FAIL][113] ([i915#2842]) -> [PASS][114]
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-glk3/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-glk2/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fence@basic-await@bcs0:
- shard-tglb: [INCOMPLETE][115] -> [PASS][116]
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-tglb1/igt@gem_exec_fence@basic-await@bcs0.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb1/igt@gem_exec_fence@basic-await@bcs0.html
* igt@gem_exec_suspend@basic-s3:
- shard-apl: [INCOMPLETE][117] -> [PASS][118]
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-apl3/igt@gem_exec_suspend@basic-s3.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-apl3/igt@gem_exec_suspend@basic-s3.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-apl: [DMESG-WARN][119] ([i915#180]) -> [PASS][120]
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-apl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-apl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-tglb: [INCOMPLETE][121] ([i915#456]) -> [PASS][122]
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-tglb7/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb8/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_flip@bo-too-big-interruptible@b-edp1:
- shard-iclb: [INCOMPLETE][123] -> [PASS][124]
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-iclb7/igt@kms_flip@bo-too-big-interruptible@b-edp1.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb5/igt@kms_flip@bo-too-big-interruptible@b-edp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile:
- shard-iclb: [SKIP][125] ([i915#3701]) -> [PASS][126]
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-iclb8/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile.html
* igt@kms_frontbuffer_tracking@fbcpsr-suspend:
- shard-tglb: [INCOMPLETE][127] ([i915#2411] / [i915#456]) -> [PASS][128] +1 similar issue
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10622/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-suspend.html
* igt@kms_hdr@bpc-switch:
- shard-skl:
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21124/index.html
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