* [PATCH 1/2] clk: renesas: r9a07g044: Add IA55_CLK and DMAC_ACLK
@ 2021-09-22 7:38 Biju Das
2021-09-22 7:38 ` [PATCH 2/2] clk: renesas: rzg2l: Fix clk status function Biju Das
0 siblings, 1 reply; 4+ messages in thread
From: Biju Das @ 2021-09-22 7:38 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Biju Das, Geert Uytterhoeven, Lad Prabhakar, linux-renesas-soc,
linux-clk, Chris Paterson, Biju Das
Add IA55_CLK and DMAC_ACLK as critical clocks.
Previously it worked ok, because of a bug in clock status function
and the following patch in this series fixes the original bug.
Fixes: c3e67ad6f5a2 ("dt-bindings: clock: r9a07g044-cpg: Update clock/reset definitions")
Fixes: eb829e549ba6 ("clk: renesas: r9a07g044: Add DMAC clocks/resets")
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/clk/renesas/r9a07g044-cpg.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 4c94b94c4125..1490446985e2 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -186,6 +186,8 @@ static struct rzg2l_reset r9a07g044_resets[] = {
static const unsigned int r9a07g044_crit_mod_clks[] __initconst = {
MOD_CLK_BASE + R9A07G044_GIC600_GICCLK,
+ MOD_CLK_BASE + R9A07G044_IA55_CLK,
+ MOD_CLK_BASE + R9A07G044_DMAC_ACLK,
};
const struct rzg2l_cpg_info r9a07g044_cpg_info = {
--
2.17.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/2] clk: renesas: rzg2l: Fix clk status function
2021-09-22 7:38 [PATCH 1/2] clk: renesas: r9a07g044: Add IA55_CLK and DMAC_ACLK Biju Das
@ 2021-09-22 7:38 ` Biju Das
2021-09-22 9:10 ` Sergei Shtylyov
0 siblings, 1 reply; 4+ messages in thread
From: Biju Das @ 2021-09-22 7:38 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Biju Das, Geert Uytterhoeven, Vinod Koul, Lad Prabhakar,
linux-renesas-soc, linux-clk, Chris Paterson, Biju Das
As per RZ/G2L HW(Rev.0.50) manual, clock monitor register value
0 means clock is not supplied and 1 means clock is supplied.
This patch fixes the issue by removing the inverted logic.
Fixing the above, triggered following 2 issues
1) GIC interrupts don't work if we disable IA55_CLK and DMAC_ACLK.
Fixed this issue by adding these clocks as critical clocks.
2) DMA is not working, since the DMA driver is not turning on DMAC_PCLK.
So will provide a fix in the DMA driver to turn on DMA_PCLK.
Fixes: ef3c613ccd68 ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC")
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/clk/renesas/rzg2l-cpg.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 3b3b2c3347f3..3e32a858b852 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -391,7 +391,7 @@ static int rzg2l_mod_clock_is_enabled(struct clk_hw *hw)
value = readl(priv->base + CLK_MON_R(clock->off));
- return !(value & bitmask);
+ return (value & bitmask);
}
static const struct clk_ops rzg2l_mod_clock_ops = {
--
2.17.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 2/2] clk: renesas: rzg2l: Fix clk status function
2021-09-22 7:38 ` [PATCH 2/2] clk: renesas: rzg2l: Fix clk status function Biju Das
@ 2021-09-22 9:10 ` Sergei Shtylyov
2021-09-22 11:18 ` Biju Das
0 siblings, 1 reply; 4+ messages in thread
From: Sergei Shtylyov @ 2021-09-22 9:10 UTC (permalink / raw)
To: Biju Das, Michael Turquette, Stephen Boyd
Cc: Geert Uytterhoeven, Vinod Koul, Lad Prabhakar, linux-renesas-soc,
linux-clk, Chris Paterson, Biju Das
Hello!
On 22.09.2021 10:38, Biju Das wrote:
> As per RZ/G2L HW(Rev.0.50) manual, clock monitor register value
> 0 means clock is not supplied and 1 means clock is supplied.
> This patch fixes the issue by removing the inverted logic.
>
> Fixing the above, triggered following 2 issues
>
> 1) GIC interrupts don't work if we disable IA55_CLK and DMAC_ACLK.
> Fixed this issue by adding these clocks as critical clocks.
>
> 2) DMA is not working, since the DMA driver is not turning on DMAC_PCLK.
> So will provide a fix in the DMA driver to turn on DMA_PCLK.
>
> Fixes: ef3c613ccd68 ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC")
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> drivers/clk/renesas/rzg2l-cpg.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
> index 3b3b2c3347f3..3e32a858b852 100644
> --- a/drivers/clk/renesas/rzg2l-cpg.c
> +++ b/drivers/clk/renesas/rzg2l-cpg.c
> @@ -391,7 +391,7 @@ static int rzg2l_mod_clock_is_enabled(struct clk_hw *hw)
>
> value = readl(priv->base + CLK_MON_R(clock->off));
>
> - return !(value & bitmask);
> + return (value & bitmask);
Parens not needed anymore...
[...]
MBR, Sergei
^ permalink raw reply [flat|nested] 4+ messages in thread
* RE: [PATCH 2/2] clk: renesas: rzg2l: Fix clk status function
2021-09-22 9:10 ` Sergei Shtylyov
@ 2021-09-22 11:18 ` Biju Das
0 siblings, 0 replies; 4+ messages in thread
From: Biju Das @ 2021-09-22 11:18 UTC (permalink / raw)
To: Sergei Shtylyov, Michael Turquette, Stephen Boyd
Cc: Geert Uytterhoeven, Vinod Koul, Prabhakar Mahadev Lad,
linux-renesas-soc, linux-clk, Chris Paterson, Biju Das
Hi Sergei,
Thanks for feedback.
> Subject: Re: [PATCH 2/2] clk: renesas: rzg2l: Fix clk status function
>
> Hello!
>
> On 22.09.2021 10:38, Biju Das wrote:
>
> > As per RZ/G2L HW(Rev.0.50) manual, clock monitor register value
> > 0 means clock is not supplied and 1 means clock is supplied.
> > This patch fixes the issue by removing the inverted logic.
> >
> > Fixing the above, triggered following 2 issues
> >
> > 1) GIC interrupts don't work if we disable IA55_CLK and DMAC_ACLK.
> > Fixed this issue by adding these clocks as critical clocks.
> >
> > 2) DMA is not working, since the DMA driver is not turning on DMAC_PCLK.
> > So will provide a fix in the DMA driver to turn on DMA_PCLK.
> >
> > Fixes: ef3c613ccd68 ("clk: renesas: Add CPG core wrapper for RZ/G2L
> > SoC")
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > drivers/clk/renesas/rzg2l-cpg.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/renesas/rzg2l-cpg.c
> > b/drivers/clk/renesas/rzg2l-cpg.c index 3b3b2c3347f3..3e32a858b852
> > 100644
> > --- a/drivers/clk/renesas/rzg2l-cpg.c
> > +++ b/drivers/clk/renesas/rzg2l-cpg.c
> > @@ -391,7 +391,7 @@ static int rzg2l_mod_clock_is_enabled(struct
> > clk_hw *hw)
> >
> > value = readl(priv->base + CLK_MON_R(clock->off));
> >
> > - return !(value & bitmask);
> > + return (value & bitmask);
>
> Parens not needed anymore...
Good catch. Will send V2.
Regards,
Biju
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2021-09-22 11:18 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2021-09-22 7:38 [PATCH 1/2] clk: renesas: r9a07g044: Add IA55_CLK and DMAC_ACLK Biju Das
2021-09-22 7:38 ` [PATCH 2/2] clk: renesas: rzg2l: Fix clk status function Biju Das
2021-09-22 9:10 ` Sergei Shtylyov
2021-09-22 11:18 ` Biju Das
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