From: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
To: <robh+dt@kernel.org>, <joel@jms.id.au>, <mturquette@baylibre.com>,
<sboyd@kernel.org>, <adrian.hunter@intel.com>,
<linux-aspeed@lists.ozlabs.org>, <openbmc@lists.ozlabs.org>,
<linux-mmc@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org>,
<andrew@aj.id.au>
Cc: <BMC-SW@aspeedtech.com>, <steven_lee@aspeedtech.com>
Subject: [PATCH 03/10] dts: aspeed: ast2600: Support SDR50 for SD device
Date: Wed, 22 Sep 2021 18:31:09 +0800 [thread overview]
Message-ID: <20210922103116.30652-4-chin-ting_kuo@aspeedtech.com> (raw)
In-Reply-To: <20210922103116.30652-1-chin-ting_kuo@aspeedtech.com>
The maximum frequency for SD controller on AST2600 EVB is
100MHz. In order to achieve 100MHz, sd-uhs-sdr50 property
should be added and the driver will set the SDR50 supported
bit in capability 2 register during probing stage.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
---
arch/arm/boot/dts/aspeed-ast2600-evb.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
index b7eb552640cb..4551dba499c2 100644
--- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts
+++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
@@ -280,6 +280,7 @@
&sdhci0 {
status = "okay";
bus-width = <4>;
+ sd-uhs-sdr50;
max-frequency = <100000000>;
sdhci-drive-type = /bits/ 8 <3>;
sdhci-caps-mask = <0x7 0x0>;
@@ -292,6 +293,7 @@
&sdhci1 {
status = "okay";
bus-width = <4>;
+ sd-uhs-sdr50;
max-frequency = <100000000>;
sdhci-drive-type = /bits/ 8 <3>;
sdhci-caps-mask = <0x7 0x0>;
--
2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
To: <robh+dt@kernel.org>, <joel@jms.id.au>, <mturquette@baylibre.com>,
<sboyd@kernel.org>, <adrian.hunter@intel.com>,
<linux-aspeed@lists.ozlabs.org>, <openbmc@lists.ozlabs.org>,
<linux-mmc@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org>,
<andrew@aj.id.au>
Cc: <BMC-SW@aspeedtech.com>, <steven_lee@aspeedtech.com>
Subject: [PATCH 03/10] dts: aspeed: ast2600: Support SDR50 for SD device
Date: Wed, 22 Sep 2021 18:31:09 +0800 [thread overview]
Message-ID: <20210922103116.30652-4-chin-ting_kuo@aspeedtech.com> (raw)
In-Reply-To: <20210922103116.30652-1-chin-ting_kuo@aspeedtech.com>
The maximum frequency for SD controller on AST2600 EVB is
100MHz. In order to achieve 100MHz, sd-uhs-sdr50 property
should be added and the driver will set the SDR50 supported
bit in capability 2 register during probing stage.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
---
arch/arm/boot/dts/aspeed-ast2600-evb.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
index b7eb552640cb..4551dba499c2 100644
--- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts
+++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
@@ -280,6 +280,7 @@
&sdhci0 {
status = "okay";
bus-width = <4>;
+ sd-uhs-sdr50;
max-frequency = <100000000>;
sdhci-drive-type = /bits/ 8 <3>;
sdhci-caps-mask = <0x7 0x0>;
@@ -292,6 +293,7 @@
&sdhci1 {
status = "okay";
bus-width = <4>;
+ sd-uhs-sdr50;
max-frequency = <100000000>;
sdhci-drive-type = /bits/ 8 <3>;
sdhci-caps-mask = <0x7 0x0>;
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
To: <robh+dt@kernel.org>, <joel@jms.id.au>, <mturquette@baylibre.com>,
<sboyd@kernel.org>, <adrian.hunter@intel.com>,
<linux-aspeed@lists.ozlabs.org>, <openbmc@lists.ozlabs.org>,
<linux-mmc@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org>,
<andrew@aj.id.au>
Cc: BMC-SW@aspeedtech.com, steven_lee@aspeedtech.com
Subject: [PATCH 03/10] dts: aspeed: ast2600: Support SDR50 for SD device
Date: Wed, 22 Sep 2021 18:31:09 +0800 [thread overview]
Message-ID: <20210922103116.30652-4-chin-ting_kuo@aspeedtech.com> (raw)
In-Reply-To: <20210922103116.30652-1-chin-ting_kuo@aspeedtech.com>
The maximum frequency for SD controller on AST2600 EVB is
100MHz. In order to achieve 100MHz, sd-uhs-sdr50 property
should be added and the driver will set the SDR50 supported
bit in capability 2 register during probing stage.
Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
---
arch/arm/boot/dts/aspeed-ast2600-evb.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
index b7eb552640cb..4551dba499c2 100644
--- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts
+++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
@@ -280,6 +280,7 @@
&sdhci0 {
status = "okay";
bus-width = <4>;
+ sd-uhs-sdr50;
max-frequency = <100000000>;
sdhci-drive-type = /bits/ 8 <3>;
sdhci-caps-mask = <0x7 0x0>;
@@ -292,6 +293,7 @@
&sdhci1 {
status = "okay";
bus-width = <4>;
+ sd-uhs-sdr50;
max-frequency = <100000000>;
sdhci-drive-type = /bits/ 8 <3>;
sdhci-caps-mask = <0x7 0x0>;
--
2.17.1
next prev parent reply other threads:[~2021-09-22 10:31 UTC|newest]
Thread overview: 84+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-22 10:31 [PATCH 00/10] ASPEED SD/eMMC controller clock configuration Chin-Ting Kuo
2021-09-22 10:31 ` Chin-Ting Kuo
2021-09-22 10:31 ` Chin-Ting Kuo
2021-09-22 10:31 ` [PATCH 01/10] clk: aspeed: ast2600: Porting sdhci clock source Chin-Ting Kuo
2021-09-22 10:31 ` Chin-Ting Kuo
2021-09-22 10:31 ` Chin-Ting Kuo
2021-09-23 0:02 ` Joel Stanley
2021-09-23 0:02 ` Joel Stanley
2021-09-23 0:02 ` Joel Stanley
2021-09-23 5:31 ` Chin-Ting Kuo
2021-09-23 5:31 ` Chin-Ting Kuo
2021-09-23 5:31 ` Chin-Ting Kuo
2021-10-26 6:10 ` Paul Menzel
2021-10-26 6:10 ` Paul Menzel
2021-10-26 6:10 ` Paul Menzel
2021-11-26 2:27 ` Chin-Ting Kuo
2021-11-26 2:27 ` Chin-Ting Kuo
2021-11-26 2:27 ` Chin-Ting Kuo
2021-09-22 10:31 ` [PATCH 02/10] sdhci: aspeed: Add SDR50 support Chin-Ting Kuo
2021-09-22 10:31 ` Chin-Ting Kuo
2021-09-22 10:31 ` Chin-Ting Kuo
2021-10-26 0:31 ` Andrew Jeffery
2021-10-26 0:31 ` Andrew Jeffery
2021-11-06 10:01 ` Chin-Ting Kuo
2021-11-06 10:01 ` Chin-Ting Kuo
2021-09-22 10:31 ` Chin-Ting Kuo [this message]
2021-09-22 10:31 ` [PATCH 03/10] dts: aspeed: ast2600: Support SDR50 for SD device Chin-Ting Kuo
2021-09-22 10:31 ` Chin-Ting Kuo
2021-10-26 0:42 ` Andrew Jeffery
2021-10-26 0:42 ` Andrew Jeffery
2021-11-06 10:01 ` Chin-Ting Kuo
2021-11-06 10:01 ` Chin-Ting Kuo
2021-09-22 10:31 ` [PATCH 04/10] mmc: Add invert flag for clock phase signedness Chin-Ting Kuo
2021-09-22 10:31 ` Chin-Ting Kuo
2021-09-22 10:31 ` Chin-Ting Kuo
2021-10-26 0:52 ` Andrew Jeffery
2021-10-26 0:52 ` Andrew Jeffery
2021-11-06 10:02 ` Chin-Ting Kuo
2021-11-06 10:02 ` Chin-Ting Kuo
2021-11-08 0:21 ` Andrew Jeffery
2021-11-08 0:21 ` Andrew Jeffery
2021-11-08 0:21 ` Andrew Jeffery
2021-09-22 10:31 ` [PATCH 05/10] mmc: aspeed: Adjust delay taps calculation method Chin-Ting Kuo
2021-09-22 10:31 ` Chin-Ting Kuo
2021-09-22 10:31 ` Chin-Ting Kuo
2021-10-26 3:10 ` Andrew Jeffery
2021-10-26 3:10 ` Andrew Jeffery
2021-11-06 10:05 ` Chin-Ting Kuo
2021-11-06 10:05 ` Chin-Ting Kuo
2021-11-07 23:42 ` Andrew Jeffery
2021-11-07 23:42 ` Andrew Jeffery
2021-09-22 10:31 ` [PATCH 06/10] arm: dts: aspeed: Change eMMC device compatible Chin-Ting Kuo
2021-09-22 10:31 ` Chin-Ting Kuo
2021-09-22 10:31 ` Chin-Ting Kuo
2021-09-22 10:31 ` [PATCH 07/10] arm: dts: aspeed: Adjust clock phase parameter Chin-Ting Kuo
2021-09-22 10:31 ` Chin-Ting Kuo
2021-09-22 10:31 ` Chin-Ting Kuo
2021-09-22 10:31 ` [PATCH 08/10] arm: dts: ibm: " Chin-Ting Kuo
2021-09-22 10:31 ` Chin-Ting Kuo
2021-09-22 10:31 ` Chin-Ting Kuo
2021-09-22 10:31 ` [PATCH 09/10] dt-bindings: mmc: aspeed: Add max-tap-delay property Chin-Ting Kuo
2021-09-22 10:31 ` Chin-Ting Kuo
2021-09-22 10:31 ` Chin-Ting Kuo
2021-09-27 18:40 ` Rob Herring
2021-09-27 18:40 ` Rob Herring
2021-09-27 18:40 ` Rob Herring
2021-09-28 2:50 ` Chin-Ting Kuo
2021-09-28 2:50 ` Chin-Ting Kuo
2021-09-28 2:50 ` Chin-Ting Kuo
2021-09-22 10:31 ` [PATCH 10/10] dt-bindings: mmc: aspeed: Add a new compatible string Chin-Ting Kuo
2021-09-22 10:31 ` Chin-Ting Kuo
2021-09-22 10:31 ` Chin-Ting Kuo
2021-09-27 18:59 ` Rob Herring
2021-09-27 18:59 ` Rob Herring
2021-09-27 18:59 ` Rob Herring
2021-09-28 2:50 ` Chin-Ting Kuo
2021-09-28 2:50 ` Chin-Ting Kuo
2021-09-28 2:50 ` Chin-Ting Kuo
2021-09-28 22:28 ` Rob Herring
2021-09-28 22:28 ` Rob Herring
2021-09-28 22:28 ` Rob Herring
2021-09-29 3:03 ` Chin-Ting Kuo
2021-09-29 3:03 ` Chin-Ting Kuo
2021-09-29 3:03 ` Chin-Ting Kuo
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210922103116.30652-4-chin-ting_kuo@aspeedtech.com \
--to=chin-ting_kuo@aspeedtech.com \
--cc=BMC-SW@aspeedtech.com \
--cc=adrian.hunter@intel.com \
--cc=andrew@aj.id.au \
--cc=devicetree@vger.kernel.org \
--cc=joel@jms.id.au \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-aspeed@lists.ozlabs.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mmc@vger.kernel.org \
--cc=mturquette@baylibre.com \
--cc=openbmc@lists.ozlabs.org \
--cc=robh+dt@kernel.org \
--cc=sboyd@kernel.org \
--cc=steven_lee@aspeedtech.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.