From: Marc Zyngier <maz@kernel.org> To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Mark Rutland <mark.rutland@arm.com>, Daniel Lezcano <daniel.lezcano@linaro.org>, Thomas Gleixner <tglx@linutronix.de>, Peter Shier <pshier@google.com>, Raghavendra Rao Ananta <rananta@google.com>, Ricardo Koller <ricarkol@google.com>, Oliver Upton <oupton@google.com>, Will Deacon <will@kernel.org>, Catalin Marinas <catalin.marinas@arm.com>, Linus Walleij <linus.walleij@linaro.org>, kernel-team@android.com Subject: [PATCH v2 07/16] clocksource/arm_arch_timer: Move MMIO timer programming over to CVAL Date: Wed, 22 Sep 2021 22:19:32 +0100 [thread overview] Message-ID: <20210922211941.2756270-8-maz@kernel.org> (raw) In-Reply-To: <20210922211941.2756270-1-maz@kernel.org> Similarily to the sysreg-based timer, move the MMIO over to using the CVAL registers instead of TVAL. Note that there is no warranty that the 64bit MMIO access will be atomic, but the timer is always disabled at the point where we program CVAL. Signed-off-by: Marc Zyngier <maz@kernel.org> --- arch/arm/include/asm/arch_timer.h | 1 + drivers/clocksource/arm_arch_timer.c | 50 +++++++++++++++++++++------- 2 files changed, 39 insertions(+), 12 deletions(-) diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h index a9b2b721c7f9..9f4b895b78f7 100644 --- a/arch/arm/include/asm/arch_timer.h +++ b/arch/arm/include/asm/arch_timer.h @@ -7,6 +7,7 @@ #include <asm/hwcap.h> #include <linux/clocksource.h> #include <linux/init.h> +#include <linux/io-64-nonatomic-lo-hi.h> #include <linux/types.h> #include <clocksource/arm_arch_timer.h> diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index bede10f67f9a..f4db3a65bc79 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -44,11 +44,13 @@ #define CNTACR_RWVT BIT(4) #define CNTACR_RWPT BIT(5) -#define CNTVCT_LO 0x08 -#define CNTVCT_HI 0x0c +#define CNTVCT_LO 0x00 +#define CNTPCT_LO 0x08 #define CNTFRQ 0x10 +#define CNTP_CVAL_LO 0x20 #define CNTP_TVAL 0x28 #define CNTP_CTL 0x2c +#define CNTV_CVAL_LO 0x30 #define CNTV_TVAL 0x38 #define CNTV_CTL 0x3c @@ -112,6 +114,13 @@ void arch_timer_reg_write(int access, enum arch_timer_reg reg, u64 val, case ARCH_TIMER_REG_TVAL: writel_relaxed((u32)val, timer->base + CNTP_TVAL); break; + case ARCH_TIMER_REG_CVAL: + /* + * Not guaranteed to be atomic, so the timer + * must be disabled at this point. + */ + writeq_relaxed(val, timer->base + CNTP_CVAL_LO); + break; default: BUILD_BUG(); } @@ -124,6 +133,10 @@ void arch_timer_reg_write(int access, enum arch_timer_reg reg, u64 val, case ARCH_TIMER_REG_TVAL: writel_relaxed((u32)val, timer->base + CNTV_TVAL); break; + case ARCH_TIMER_REG_CVAL: + /* Same restriction as above */ + writeq_relaxed(val, timer->base + CNTV_CVAL_LO); + break; default: BUILD_BUG(); } @@ -720,15 +733,36 @@ static int arch_timer_set_next_event_phys(unsigned long evt, return 0; } +static u64 arch_counter_get_cnt_mem(struct arch_timer *t, int offset_lo) +{ + u32 cnt_lo, cnt_hi, tmp_hi; + + do { + cnt_hi = readl_relaxed(t->base + offset_lo + 4); + cnt_lo = readl_relaxed(t->base + offset_lo); + tmp_hi = readl_relaxed(t->base + offset_lo + 4); + } while (cnt_hi != tmp_hi); + + return ((u64) cnt_hi << 32) | cnt_lo; +} + static __always_inline void set_next_event_mem(const int access, unsigned long evt, struct clock_event_device *clk) { + struct arch_timer *timer = to_arch_timer(clk); unsigned long ctrl; + u64 cnt; + ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk); ctrl |= ARCH_TIMER_CTRL_ENABLE; ctrl &= ~ARCH_TIMER_CTRL_IT_MASK; - arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt, clk); + if (access == ARCH_TIMER_MEM_VIRT_ACCESS) + cnt = arch_counter_get_cnt_mem(timer, CNTVCT_LO); + else + cnt = arch_counter_get_cnt_mem(timer, CNTPCT_LO); + + arch_timer_reg_write(access, ARCH_TIMER_REG_CVAL, evt + cnt, clk); arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk); } @@ -970,15 +1004,7 @@ bool arch_timer_evtstrm_available(void) static u64 arch_counter_get_cntvct_mem(void) { - u32 vct_lo, vct_hi, tmp_hi; - - do { - vct_hi = readl_relaxed(arch_timer_mem->base + CNTVCT_HI); - vct_lo = readl_relaxed(arch_timer_mem->base + CNTVCT_LO); - tmp_hi = readl_relaxed(arch_timer_mem->base + CNTVCT_HI); - } while (vct_hi != tmp_hi); - - return ((u64) vct_hi << 32) | vct_lo; + return arch_counter_get_cnt_mem(arch_timer_mem, CNTVCT_LO); } static struct arch_timer_kvm_info arch_timer_kvm_info; -- 2.30.2
WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org> To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Mark Rutland <mark.rutland@arm.com>, Daniel Lezcano <daniel.lezcano@linaro.org>, Thomas Gleixner <tglx@linutronix.de>, Peter Shier <pshier@google.com>, Raghavendra Rao Ananta <rananta@google.com>, Ricardo Koller <ricarkol@google.com>, Oliver Upton <oupton@google.com>, Will Deacon <will@kernel.org>, Catalin Marinas <catalin.marinas@arm.com>, Linus Walleij <linus.walleij@linaro.org>, kernel-team@android.com Subject: [PATCH v2 07/16] clocksource/arm_arch_timer: Move MMIO timer programming over to CVAL Date: Wed, 22 Sep 2021 22:19:32 +0100 [thread overview] Message-ID: <20210922211941.2756270-8-maz@kernel.org> (raw) In-Reply-To: <20210922211941.2756270-1-maz@kernel.org> Similarily to the sysreg-based timer, move the MMIO over to using the CVAL registers instead of TVAL. Note that there is no warranty that the 64bit MMIO access will be atomic, but the timer is always disabled at the point where we program CVAL. Signed-off-by: Marc Zyngier <maz@kernel.org> --- arch/arm/include/asm/arch_timer.h | 1 + drivers/clocksource/arm_arch_timer.c | 50 +++++++++++++++++++++------- 2 files changed, 39 insertions(+), 12 deletions(-) diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h index a9b2b721c7f9..9f4b895b78f7 100644 --- a/arch/arm/include/asm/arch_timer.h +++ b/arch/arm/include/asm/arch_timer.h @@ -7,6 +7,7 @@ #include <asm/hwcap.h> #include <linux/clocksource.h> #include <linux/init.h> +#include <linux/io-64-nonatomic-lo-hi.h> #include <linux/types.h> #include <clocksource/arm_arch_timer.h> diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index bede10f67f9a..f4db3a65bc79 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -44,11 +44,13 @@ #define CNTACR_RWVT BIT(4) #define CNTACR_RWPT BIT(5) -#define CNTVCT_LO 0x08 -#define CNTVCT_HI 0x0c +#define CNTVCT_LO 0x00 +#define CNTPCT_LO 0x08 #define CNTFRQ 0x10 +#define CNTP_CVAL_LO 0x20 #define CNTP_TVAL 0x28 #define CNTP_CTL 0x2c +#define CNTV_CVAL_LO 0x30 #define CNTV_TVAL 0x38 #define CNTV_CTL 0x3c @@ -112,6 +114,13 @@ void arch_timer_reg_write(int access, enum arch_timer_reg reg, u64 val, case ARCH_TIMER_REG_TVAL: writel_relaxed((u32)val, timer->base + CNTP_TVAL); break; + case ARCH_TIMER_REG_CVAL: + /* + * Not guaranteed to be atomic, so the timer + * must be disabled at this point. + */ + writeq_relaxed(val, timer->base + CNTP_CVAL_LO); + break; default: BUILD_BUG(); } @@ -124,6 +133,10 @@ void arch_timer_reg_write(int access, enum arch_timer_reg reg, u64 val, case ARCH_TIMER_REG_TVAL: writel_relaxed((u32)val, timer->base + CNTV_TVAL); break; + case ARCH_TIMER_REG_CVAL: + /* Same restriction as above */ + writeq_relaxed(val, timer->base + CNTV_CVAL_LO); + break; default: BUILD_BUG(); } @@ -720,15 +733,36 @@ static int arch_timer_set_next_event_phys(unsigned long evt, return 0; } +static u64 arch_counter_get_cnt_mem(struct arch_timer *t, int offset_lo) +{ + u32 cnt_lo, cnt_hi, tmp_hi; + + do { + cnt_hi = readl_relaxed(t->base + offset_lo + 4); + cnt_lo = readl_relaxed(t->base + offset_lo); + tmp_hi = readl_relaxed(t->base + offset_lo + 4); + } while (cnt_hi != tmp_hi); + + return ((u64) cnt_hi << 32) | cnt_lo; +} + static __always_inline void set_next_event_mem(const int access, unsigned long evt, struct clock_event_device *clk) { + struct arch_timer *timer = to_arch_timer(clk); unsigned long ctrl; + u64 cnt; + ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk); ctrl |= ARCH_TIMER_CTRL_ENABLE; ctrl &= ~ARCH_TIMER_CTRL_IT_MASK; - arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt, clk); + if (access == ARCH_TIMER_MEM_VIRT_ACCESS) + cnt = arch_counter_get_cnt_mem(timer, CNTVCT_LO); + else + cnt = arch_counter_get_cnt_mem(timer, CNTPCT_LO); + + arch_timer_reg_write(access, ARCH_TIMER_REG_CVAL, evt + cnt, clk); arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk); } @@ -970,15 +1004,7 @@ bool arch_timer_evtstrm_available(void) static u64 arch_counter_get_cntvct_mem(void) { - u32 vct_lo, vct_hi, tmp_hi; - - do { - vct_hi = readl_relaxed(arch_timer_mem->base + CNTVCT_HI); - vct_lo = readl_relaxed(arch_timer_mem->base + CNTVCT_LO); - tmp_hi = readl_relaxed(arch_timer_mem->base + CNTVCT_HI); - } while (vct_hi != tmp_hi); - - return ((u64) vct_hi << 32) | vct_lo; + return arch_counter_get_cnt_mem(arch_timer_mem, CNTVCT_LO); } static struct arch_timer_kvm_info arch_timer_kvm_info; -- 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-09-22 21:20 UTC|newest] Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-09-22 21:19 [PATCH v2 00/16] clocksource/arm_arch_timer: Add basic ARMv8.6 support Marc Zyngier 2021-09-22 21:19 ` Marc Zyngier 2021-09-22 21:19 ` [PATCH v2 01/16] clocksource/arm_arch_timer: Add build-time guards for unhandled register accesses Marc Zyngier 2021-09-22 21:19 ` Marc Zyngier 2021-09-22 21:19 ` [PATCH v2 02/16] clocksource/arm_arch_timer: Drop CNT*_TVAL read accessors Marc Zyngier 2021-09-22 21:19 ` Marc Zyngier 2021-09-22 21:19 ` [PATCH v2 03/16] clocksource/arm_arch_timer: Extend write side of timer register accessors to u64 Marc Zyngier 2021-09-22 21:19 ` Marc Zyngier 2021-09-22 21:19 ` [PATCH v2 04/16] clocksource/arm_arch_timer: Move system register timer programming over to CVAL Marc Zyngier 2021-09-22 21:19 ` Marc Zyngier 2021-09-22 21:19 ` [PATCH v2 05/16] clocksource/arm_arch_timer: Move drop _tval from erratum function names Marc Zyngier 2021-09-22 21:19 ` Marc Zyngier 2021-09-22 21:19 ` [PATCH v2 06/16] clocksource/arm_arch_timer: Fix MMIO base address vs callback ordering issue Marc Zyngier 2021-09-22 21:19 ` Marc Zyngier 2021-09-22 21:19 ` Marc Zyngier [this message] 2021-09-22 21:19 ` [PATCH v2 07/16] clocksource/arm_arch_timer: Move MMIO timer programming over to CVAL Marc Zyngier 2021-09-22 21:19 ` [PATCH v2 08/16] clocksource/arm_arch_timer: Advertise 56bit timer to the core code Marc Zyngier 2021-09-22 21:19 ` Marc Zyngier 2021-09-22 21:19 ` [PATCH v2 09/16] clocksource/arm_arch_timer: Work around broken CVAL implementations Marc Zyngier 2021-09-22 21:19 ` Marc Zyngier 2021-09-22 21:19 ` [PATCH v2 10/16] clocksource/arm_arch_timer: Remove any trace of the TVAL programming interface Marc Zyngier 2021-09-22 21:19 ` Marc Zyngier 2021-09-22 21:19 ` [PATCH v2 11/16] clocksource/arm_arch_timer: Drop unnecessary ISB on CVAL programming Marc Zyngier 2021-09-22 21:19 ` Marc Zyngier 2021-09-22 21:19 ` [PATCH v2 12/16] clocksource/arm_arch_timer: Fix masking for high freq counters Marc Zyngier 2021-09-22 21:19 ` Marc Zyngier 2021-09-22 21:19 ` [PATCH v2 13/16] clocksource/arch_arm_timer: Move workaround synchronisation around Marc Zyngier 2021-09-22 21:19 ` Marc Zyngier 2021-09-22 21:19 ` [PATCH v2 14/16] arm64: Add a capability for FEAT_ECV Marc Zyngier 2021-09-22 21:19 ` Marc Zyngier 2021-09-29 16:03 ` Will Deacon 2021-09-29 16:03 ` Will Deacon 2021-09-30 7:42 ` Marc Zyngier 2021-09-30 7:42 ` Marc Zyngier 2021-09-30 8:30 ` Will Deacon 2021-09-30 8:30 ` Will Deacon 2021-09-22 21:19 ` [PATCH v2 15/16] arm64: Add CNT{P,V}CTSS_EL0 alternatives to cnt{p,v}ct_el0 Marc Zyngier 2021-09-22 21:19 ` [PATCH v2 15/16] arm64: Add CNT{P, V}CTSS_EL0 alternatives to cnt{p, v}ct_el0 Marc Zyngier 2021-09-22 21:19 ` [PATCH v2 16/16] arm64: Add handling of CNTVCTSS traps Marc Zyngier 2021-09-22 21:19 ` Marc Zyngier
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