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From: Sasha Levin <sashal@kernel.org>
To: linux-kernel@vger.kernel.org, stable@vger.kernel.org
Cc: Jesper Nilsson <jesper.nilsson@axis.com>,
	"David S . Miller" <davem@davemloft.net>,
	Sasha Levin <sashal@kernel.org>,
	peppe.cavallaro@st.com, alexandre.torgue@foss.st.com,
	joabreu@synopsys.com, kuba@kernel.org, mcoquelin.stm32@gmail.com,
	netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH AUTOSEL 4.19 03/15] net: stmmac: allow CSR clock of 300MHz
Date: Wed, 22 Sep 2021 23:39:17 -0400	[thread overview]
Message-ID: <20210923033929.1421446-3-sashal@kernel.org> (raw)
In-Reply-To: <20210923033929.1421446-1-sashal@kernel.org>

From: Jesper Nilsson <jesper.nilsson@axis.com>

[ Upstream commit 08dad2f4d541fcfe5e7bfda72cc6314bbfd2802f ]

The Synopsys Ethernet IP uses the CSR clock as a base clock for MDC.
The divisor used is set in the MAC_MDIO_Address register field CR
(Clock Rate)

The divisor is there to change the CSR clock into a clock that falls
below the IEEE 802.3 specified max frequency of 2.5MHz.

If the CSR clock is 300MHz, the code falls back to using the reset
value in the MAC_MDIO_Address register, as described in the comment
above this code.

However, 300MHz is actually an allowed value and the proper divider
can be estimated quite easily (it's just 1Hz difference!)

A CSR frequency of 300MHz with the maximum clock rate value of 0x5
(STMMAC_CSR_250_300M, a divisor of 124) gives somewhere around
~2.42MHz which is below the IEEE 802.3 specified maximum.

For the ARTPEC-8 SoC, the CSR clock is this problematic 300MHz,
and unfortunately, the reset-value of the MAC_MDIO_Address CR field
is 0x0.

This leads to a clock rate of zero and a divisor of 42, and gives an
MDC frequency of ~7.14MHz.

Allow CSR clock of 300MHz by making the comparison inclusive.

Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index af59761ddfa0..064e13bd2c8b 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -227,7 +227,7 @@ static void stmmac_clk_csr_set(struct stmmac_priv *priv)
 			priv->clk_csr = STMMAC_CSR_100_150M;
 		else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
 			priv->clk_csr = STMMAC_CSR_150_250M;
-		else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
+		else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M))
 			priv->clk_csr = STMMAC_CSR_250_300M;
 	}
 
-- 
2.30.2


WARNING: multiple messages have this Message-ID (diff)
From: Sasha Levin <sashal@kernel.org>
To: linux-kernel@vger.kernel.org, stable@vger.kernel.org
Cc: Jesper Nilsson <jesper.nilsson@axis.com>,
	"David S . Miller" <davem@davemloft.net>,
	Sasha Levin <sashal@kernel.org>,
	peppe.cavallaro@st.com, alexandre.torgue@foss.st.com,
	joabreu@synopsys.com, kuba@kernel.org, mcoquelin.stm32@gmail.com,
	netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH AUTOSEL 4.19 03/15] net: stmmac: allow CSR clock of 300MHz
Date: Wed, 22 Sep 2021 23:39:17 -0400	[thread overview]
Message-ID: <20210923033929.1421446-3-sashal@kernel.org> (raw)
In-Reply-To: <20210923033929.1421446-1-sashal@kernel.org>

From: Jesper Nilsson <jesper.nilsson@axis.com>

[ Upstream commit 08dad2f4d541fcfe5e7bfda72cc6314bbfd2802f ]

The Synopsys Ethernet IP uses the CSR clock as a base clock for MDC.
The divisor used is set in the MAC_MDIO_Address register field CR
(Clock Rate)

The divisor is there to change the CSR clock into a clock that falls
below the IEEE 802.3 specified max frequency of 2.5MHz.

If the CSR clock is 300MHz, the code falls back to using the reset
value in the MAC_MDIO_Address register, as described in the comment
above this code.

However, 300MHz is actually an allowed value and the proper divider
can be estimated quite easily (it's just 1Hz difference!)

A CSR frequency of 300MHz with the maximum clock rate value of 0x5
(STMMAC_CSR_250_300M, a divisor of 124) gives somewhere around
~2.42MHz which is below the IEEE 802.3 specified maximum.

For the ARTPEC-8 SoC, the CSR clock is this problematic 300MHz,
and unfortunately, the reset-value of the MAC_MDIO_Address CR field
is 0x0.

This leads to a clock rate of zero and a divisor of 42, and gives an
MDC frequency of ~7.14MHz.

Allow CSR clock of 300MHz by making the comparison inclusive.

Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index af59761ddfa0..064e13bd2c8b 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -227,7 +227,7 @@ static void stmmac_clk_csr_set(struct stmmac_priv *priv)
 			priv->clk_csr = STMMAC_CSR_100_150M;
 		else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
 			priv->clk_csr = STMMAC_CSR_150_250M;
-		else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
+		else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M))
 			priv->clk_csr = STMMAC_CSR_250_300M;
 	}
 
-- 
2.30.2


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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2021-09-23  3:41 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-23  3:39 [PATCH AUTOSEL 4.19 01/15] ibmvnic: check failover_pending in login response Sasha Levin
2021-09-23  3:39 ` Sasha Levin
2021-09-23  3:39 ` [PATCH AUTOSEL 4.19 02/15] net: macb: fix use after free on rmmod Sasha Levin
2021-09-23  3:39 ` Sasha Levin [this message]
2021-09-23  3:39   ` [PATCH AUTOSEL 4.19 03/15] net: stmmac: allow CSR clock of 300MHz Sasha Levin
2021-09-23  3:39 ` [PATCH AUTOSEL 4.19 04/15] m68k: Double cast io functions to unsigned long Sasha Levin
2021-09-23  3:39 ` [PATCH AUTOSEL 4.19 05/15] xen/balloon: use a kernel thread instead a workqueue Sasha Levin
2021-09-23  3:39 ` [PATCH AUTOSEL 4.19 06/15] nvme-multipath: fix ANA state updates when a namespace is not present Sasha Levin
2021-09-23  3:39 ` [PATCH AUTOSEL 4.19 07/15] compiler.h: Introduce absolute_pointer macro Sasha Levin
2021-09-23  3:39 ` [PATCH AUTOSEL 4.19 08/15] net: i825xx: Use absolute_pointer for memcpy from fixed memory location Sasha Levin
2021-09-23  3:39 ` [PATCH AUTOSEL 4.19 09/15] sparc: avoid stringop-overread errors Sasha Levin
2021-09-23  3:39 ` [PATCH AUTOSEL 4.19 10/15] qnx4: " Sasha Levin
2021-09-23  3:39 ` [PATCH AUTOSEL 4.19 11/15] parisc: Use absolute_pointer() to define PAGE0 Sasha Levin
2021-09-23  3:39 ` [PATCH AUTOSEL 4.19 12/15] arm64: Mark __stack_chk_guard as __ro_after_init Sasha Levin
2021-09-23  3:39   ` Sasha Levin
2021-09-23  3:39 ` [PATCH AUTOSEL 4.19 13/15] alpha: Declare virt_to_phys and virt_to_bus parameter as pointer to volatile Sasha Levin
2021-09-23  3:39 ` [PATCH AUTOSEL 4.19 14/15] net: 6pack: Fix tx timeout and slot time Sasha Levin
2021-09-23  3:39 ` [PATCH AUTOSEL 4.19 15/15] spi: Fix tegra20 build with CONFIG_PM=n Sasha Levin

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