From: Claudiu Beznea <claudiu.beznea@microchip.com>
To: <mturquette@baylibre.com>, <sboyd@kernel.org>,
<nicolas.ferre@microchip.com>, <alexandre.belloni@bootlin.com>,
<ludovic.desroches@microchip.com>
Cc: <linux-clk@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
Claudiu Beznea <claudiu.beznea@microchip.com>
Subject: [PATCH v4 10/17] clk: at91: clk-master: fix prescaler logic
Date: Thu, 23 Sep 2021 16:20:39 +0300 [thread overview]
Message-ID: <20210923132046.1860549-11-claudiu.beznea@microchip.com> (raw)
In-Reply-To: <20210923132046.1860549-1-claudiu.beznea@microchip.com>
When prescaler value read from register is MASTER_PRES_MAX it means
that the input clock will be divided by 3. Fix the code to reflect
this.
Fixes: 7a110b9107ed8 ("clk: at91: clk-master: re-factor master clock")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
drivers/clk/at91/clk-master.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c
index 6da9ae34313a..e67bcd03a827 100644
--- a/drivers/clk/at91/clk-master.c
+++ b/drivers/clk/at91/clk-master.c
@@ -386,7 +386,7 @@ static unsigned long clk_master_pres_recalc_rate(struct clk_hw *hw,
val &= master->layout->mask;
pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK;
- if (pres == 3 && characteristics->have_div3_pres)
+ if (pres == MASTER_PRES_MAX && characteristics->have_div3_pres)
pres = 3;
else
pres = (1 << pres);
--
2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Claudiu Beznea <claudiu.beznea@microchip.com>
To: <mturquette@baylibre.com>, <sboyd@kernel.org>,
<nicolas.ferre@microchip.com>, <alexandre.belloni@bootlin.com>,
<ludovic.desroches@microchip.com>
Cc: <linux-clk@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
Claudiu Beznea <claudiu.beznea@microchip.com>
Subject: [PATCH v4 10/17] clk: at91: clk-master: fix prescaler logic
Date: Thu, 23 Sep 2021 16:20:39 +0300 [thread overview]
Message-ID: <20210923132046.1860549-11-claudiu.beznea@microchip.com> (raw)
In-Reply-To: <20210923132046.1860549-1-claudiu.beznea@microchip.com>
When prescaler value read from register is MASTER_PRES_MAX it means
that the input clock will be divided by 3. Fix the code to reflect
this.
Fixes: 7a110b9107ed8 ("clk: at91: clk-master: re-factor master clock")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
drivers/clk/at91/clk-master.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c
index 6da9ae34313a..e67bcd03a827 100644
--- a/drivers/clk/at91/clk-master.c
+++ b/drivers/clk/at91/clk-master.c
@@ -386,7 +386,7 @@ static unsigned long clk_master_pres_recalc_rate(struct clk_hw *hw,
val &= master->layout->mask;
pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK;
- if (pres == 3 && characteristics->have_div3_pres)
+ if (pres == MASTER_PRES_MAX && characteristics->have_div3_pres)
pres = 3;
else
pres = (1 << pres);
--
2.25.1
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next prev parent reply other threads:[~2021-09-23 13:21 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-23 13:20 [PATCH v4 00/17] clk: at91: updates for power management and dvfs Claudiu Beznea
2021-09-23 13:20 ` Claudiu Beznea
2021-09-23 13:20 ` [PATCH v4 01/17] clk: at91: re-factor clocks suspend/resume Claudiu Beznea
2021-09-23 13:20 ` Claudiu Beznea
2021-09-23 13:23 ` Claudiu.Beznea
2021-09-23 13:23 ` Claudiu.Beznea
2021-09-23 13:20 ` [PATCH v4 02/17] clk: at91: pmc: execute suspend/resume only for backup mode Claudiu Beznea
2021-09-23 13:20 ` Claudiu Beznea
2021-10-08 3:51 ` Stephen Boyd
2021-10-08 3:51 ` Stephen Boyd
2021-10-08 6:47 ` Claudiu.Beznea
2021-10-08 6:47 ` Claudiu.Beznea
2021-10-08 22:05 ` Stephen Boyd
2021-10-08 22:05 ` Stephen Boyd
2021-09-23 13:20 ` [PATCH v4 03/17] clk: at91: sama7g5: add securam's peripheral clock Claudiu Beznea
2021-09-23 13:20 ` Claudiu Beznea
2021-09-23 13:20 ` [PATCH v4 04/17] clk: at91: clk-master: add register definition for sama7g5's master clock Claudiu Beznea
2021-09-23 13:20 ` Claudiu Beznea
2021-09-23 13:20 ` [PATCH v4 05/17] clk: at91: clk-master: improve readability by using local variables Claudiu Beznea
2021-09-23 13:20 ` Claudiu Beznea
2021-09-23 13:20 ` [PATCH v4 06/17] clk: at91: pmc: add sama7g5 to the list of available pmcs Claudiu Beznea
2021-09-23 13:20 ` Claudiu Beznea
2021-09-23 13:20 ` [PATCH v4 07/17] clk: at91: sam9x60-pll: use DIV_ROUND_CLOSEST_ULL Claudiu Beznea
2021-09-23 13:20 ` Claudiu Beznea
2021-09-23 13:20 ` [PATCH v4 08/17] clk: at91: clk-master: check if div or pres is zero Claudiu Beznea
2021-09-23 13:20 ` Claudiu Beznea
2021-09-23 13:20 ` [PATCH v4 09/17] clk: at91: clk-master: mask mckr against layout->mask Claudiu Beznea
2021-09-23 13:20 ` Claudiu Beznea
2021-09-23 13:20 ` Claudiu Beznea [this message]
2021-09-23 13:20 ` [PATCH v4 10/17] clk: at91: clk-master: fix prescaler logic Claudiu Beznea
2021-09-23 13:20 ` [PATCH v4 11/17] clk: at91: clk-sam9x60-pll: add notifier for div part of PLL Claudiu Beznea
2021-09-23 13:20 ` Claudiu Beznea
2021-09-23 13:20 ` [PATCH v4 12/17] clk: at91: clk-master: add notifier for divider Claudiu Beznea
2021-09-23 13:20 ` Claudiu Beznea
2021-09-23 13:20 ` [PATCH v4 13/17] clk: at91: sama7g5: remove prescaler part of master clock Claudiu Beznea
2021-09-23 13:20 ` Claudiu Beznea
2021-09-23 13:20 ` [PATCH v4 14/17] clk: at91: sama7g5: set low limit for mck0 at 32KHz Claudiu Beznea
2021-09-23 13:20 ` Claudiu Beznea
2021-09-23 13:20 ` [PATCH v4 15/17] clk: use clk_core_get_rate_recalc() in clk_rate_get() Claudiu Beznea
2021-09-23 13:20 ` Claudiu Beznea
2021-09-23 13:20 ` [PATCH v4 16/17] clk: remove extra empty line Claudiu Beznea
2021-09-23 13:20 ` Claudiu Beznea
2021-10-08 3:54 ` Stephen Boyd
2021-10-08 3:54 ` Stephen Boyd
2021-09-23 13:20 ` [PATCH v4 17/17] clk: do not initialize ret Claudiu Beznea
2021-09-23 13:20 ` Claudiu Beznea
2021-10-08 3:55 ` Stephen Boyd
2021-10-08 3:55 ` Stephen Boyd
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