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From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
	"open list:ARM TCG CPUs" <qemu-arm@nongnu.org>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PATCH v7 17/40] target/arm: Restrict has_work() handler to sysemu and TCG
Date: Sat, 25 Sep 2021 16:50:55 +0200	[thread overview]
Message-ID: <20210925145118.1361230-18-f4bug@amsat.org> (raw)
In-Reply-To: <20210925145118.1361230-1-f4bug@amsat.org>

Restrict arm_cpu_has_work() and has_work() handler to TCG sysemu.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/arm/internals.h | 4 +++-
 target/arm/cpu.c       | 7 +++++--
 target/arm/cpu_tcg.c   | 2 +-
 3 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index f20aeb97fa0..18b3c2bf1ea 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -175,9 +175,11 @@ void arm_translate_init(void);
 
 #ifdef CONFIG_TCG
 void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb);
-#endif /* CONFIG_TCG */
 
+#if !defined(CONFIG_USER_ONLY)
 bool arm_cpu_has_work(CPUState *cs);
+#endif /* !CONFIG_USER_ONLY */
+#endif /* CONFIG_TCG */
 
 /**
  * aarch64_sve_zcr_get_valid_len:
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 4b08f717f64..53c478171ac 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -74,8 +74,8 @@ void arm_cpu_synchronize_from_tb(CPUState *cs,
         env->regs[15] = tb->pc;
     }
 }
-#endif /* CONFIG_TCG */
 
+#ifndef CONFIG_USER_ONLY
 bool arm_cpu_has_work(CPUState *cs)
 {
     ARMCPU *cpu = ARM_CPU(cs);
@@ -86,6 +86,9 @@ bool arm_cpu_has_work(CPUState *cs)
          | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
          | CPU_INTERRUPT_EXITTB);
 }
+#endif /* !CONFIG_USER_ONLY */
+
+#endif /* CONFIG_TCG */
 
 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
                                  void *opaque)
@@ -2035,6 +2038,7 @@ static const struct TCGCPUOps arm_tcg_ops = {
     .debug_excp_handler = arm_debug_excp_handler,
 
 #if !defined(CONFIG_USER_ONLY)
+    .has_work = arm_cpu_has_work,
     .cpu_exec_interrupt = arm_cpu_exec_interrupt,
     .do_interrupt = arm_cpu_do_interrupt,
     .do_transaction_failed = arm_cpu_do_transaction_failed,
@@ -2059,7 +2063,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
     device_class_set_parent_reset(dc, arm_cpu_reset, &acc->parent_reset);
 
     cc->class_by_name = arm_cpu_class_by_name;
-    cc->has_work = arm_cpu_has_work;
     cc->dump_state = arm_cpu_dump_state;
     cc->set_pc = arm_cpu_set_pc;
     cc->gdb_read_register = arm_cpu_gdb_read_register;
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index 9a0927ad5d0..7d0d9fcbc79 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -902,6 +902,7 @@ static const struct TCGCPUOps arm_v7m_tcg_ops = {
     .debug_excp_handler = arm_debug_excp_handler,
 
 #if !defined(CONFIG_USER_ONLY)
+    .has_work = arm_cpu_has_work,
     .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt,
     .do_interrupt = arm_v7m_cpu_do_interrupt,
     .do_transaction_failed = arm_cpu_do_transaction_failed,
@@ -920,7 +921,6 @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
 
     acc->info = data;
 #ifdef CONFIG_TCG
-    cc->has_work = arm_cpu_has_work;
     cc->tcg_ops = &arm_v7m_tcg_ops;
 #endif /* CONFIG_TCG */
 
-- 
2.31.1



  parent reply	other threads:[~2021-09-25 15:22 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-25 14:50 [PATCH v7 00/40] accel: Move has_work() from CPUClass to AccelOpsClass Philippe Mathieu-Daudé
2021-09-25 14:50 ` [PATCH v7 01/40] accel: Simplify qemu_init_vcpu() Philippe Mathieu-Daudé
2021-09-25 15:25   ` Richard Henderson
2021-09-25 14:50 ` [PATCH v7 02/40] hw/core: Restrict cpu_has_work() to sysemu Philippe Mathieu-Daudé
2021-09-25 14:50 ` [PATCH v7 03/40] hw/core: Un-inline cpu_has_work() Philippe Mathieu-Daudé
2021-09-25 14:50 ` [PATCH v7 04/40] hw/core: Move cpu_common_has_work() to cpu_has_work() Philippe Mathieu-Daudé
2021-09-25 14:50 ` [PATCH v7 05/40] accel: Introduce AccelOpsClass::has_work() Philippe Mathieu-Daudé
2021-09-25 14:50 ` [PATCH v7 06/40] accel/kvm: Implement AccelOpsClass::has_work() Philippe Mathieu-Daudé
2021-09-25 14:50   ` Philippe Mathieu-Daudé
2021-09-25 14:50 ` [PATCH v7 07/40] accel/whpx: " Philippe Mathieu-Daudé
2021-09-25 14:50 ` [PATCH v7 08/40] accel/hvf: " Philippe Mathieu-Daudé
2021-09-25 14:50 ` [PATCH v7 09/40] accel/xen: " Philippe Mathieu-Daudé
2021-09-25 14:50   ` Philippe Mathieu-Daudé
2021-09-25 14:50 ` [PATCH v7 10/40] accel/hax: " Philippe Mathieu-Daudé
2021-09-25 14:50 ` [PATCH v7 11/40] accel/nvmm: " Philippe Mathieu-Daudé
2021-09-25 14:50 ` [PATCH v7 12/40] accel/qtest: " Philippe Mathieu-Daudé
2021-09-25 15:27   ` Philippe Mathieu-Daudé
2021-09-25 15:32     ` Richard Henderson
2021-09-25 16:01       ` Philippe Mathieu-Daudé
2021-09-27  6:12         ` Laurent Vivier
2021-09-25 14:50 ` [PATCH v7 13/40] accel/tcg: " Philippe Mathieu-Daudé
2021-09-25 14:50 ` [PATCH v7 14/40] accel: Simplify cpu_has_work() Philippe Mathieu-Daudé
2021-09-25 14:50 ` [PATCH v7 15/40] accel/tcg: Introduce TCGCPUOps::has_work() Philippe Mathieu-Daudé
2021-09-25 14:50 ` [PATCH v7 16/40] target/arm: Explicit v7M cores use arm_cpu_has_work as CPUClass:has_work Philippe Mathieu-Daudé
2021-09-25 14:50 ` Philippe Mathieu-Daudé [this message]
2021-09-25 14:50 ` [PATCH v7 18/40] target/alpha: Restrict has_work() handler to sysemu Philippe Mathieu-Daudé
2021-09-25 14:50 ` [PATCH v7 19/40] target/avr: " Philippe Mathieu-Daudé
2021-09-25 14:50 ` [PATCH v7 20/40] target/cris: " Philippe Mathieu-Daudé
2021-09-25 14:50 ` [PATCH v7 21/40] target/hexagon: Remove unused has_work() handler Philippe Mathieu-Daudé
2021-09-25 14:51 ` [PATCH v7 22/40] target/hppa: Restrict has_work() handler to sysemu Philippe Mathieu-Daudé
2021-09-25 14:51 ` [PATCH v7 23/40] target/i386: Restrict has_work() handler to sysemu and TCG Philippe Mathieu-Daudé
2021-09-25 14:51 ` [PATCH v7 24/40] target/m68k: Restrict has_work() handler to sysemu Philippe Mathieu-Daudé
2021-09-25 14:51 ` [PATCH v7 25/40] target/microblaze: " Philippe Mathieu-Daudé
2021-09-25 14:51 ` [PATCH v7 26/40] target/mips: Restrict has_work() handler to sysemu and TCG Philippe Mathieu-Daudé
2021-09-25 14:51 ` [PATCH v7 27/40] target/nios2: Restrict has_work() handler to sysemu Philippe Mathieu-Daudé
2021-09-25 14:51 ` [PATCH v7 28/40] target/openrisc: " Philippe Mathieu-Daudé
2021-09-25 14:51 ` [PATCH v7 29/40] target/ppc: Introduce PowerPCCPUClass::has_work() Philippe Mathieu-Daudé
2021-09-25 14:51 ` [PATCH v7 30/40] target/ppc: Restrict has_work() handlers to sysemu and TCG Philippe Mathieu-Daudé
2021-09-25 14:51 ` [PATCH v7 31/40] target/riscv: Restrict has_work() handler " Philippe Mathieu-Daudé
2021-09-25 14:51   ` Philippe Mathieu-Daudé
2021-09-25 14:51 ` [PATCH v7 32/40] target/rx: Restrict has_work() handler to sysemu Philippe Mathieu-Daudé
2021-09-25 14:51 ` [PATCH v7 33/40] target/s390x: Restrict has_work() handler to sysemu and TCG Philippe Mathieu-Daudé
2021-09-25 14:51 ` [PATCH v7 34/40] target/sh4: Restrict has_work() handler to sysemu Philippe Mathieu-Daudé
2021-09-25 14:51 ` [PATCH v7 35/40] target/sparc: Remove pointless use of CONFIG_TCG definition Philippe Mathieu-Daudé
2021-09-25 14:51 ` [PATCH v7 36/40] target/sparc: Restrict has_work() handler to sysemu Philippe Mathieu-Daudé
2021-09-25 14:51 ` [PATCH v7 37/40] target/tricore: " Philippe Mathieu-Daudé
2021-09-25 14:51 ` [PATCH v7 38/40] target/xtensa: " Philippe Mathieu-Daudé
2021-09-25 14:51 ` [PATCH v7 39/40] accel/tcg: Remove CPUClass::has_work() Philippe Mathieu-Daudé
2021-09-25 14:51 ` [PATCH v7 40/40] accel/tcg: Simplify tcg_cpu_has_work() Philippe Mathieu-Daudé
2021-09-25 15:28 ` [PATCH v7 00/40] accel: Move has_work() from CPUClass to AccelOpsClass Richard Henderson
2021-09-25 15:36   ` Philippe Mathieu-Daudé

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