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From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "open list:PowerPC TCG CPUs" <qemu-ppc@nongnu.org>,
	"Greg Kurz" <groug@kaod.org>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"David Gibson" <david@gibson.dropbear.id.au>
Subject: [PATCH v7 30/40] target/ppc: Restrict has_work() handlers to sysemu and TCG
Date: Sat, 25 Sep 2021 16:51:08 +0200	[thread overview]
Message-ID: <20210925145118.1361230-31-f4bug@amsat.org> (raw)
In-Reply-To: <20210925145118.1361230-1-f4bug@amsat.org>

Restrict PowerPCCPUClass::has_work() and ppc_cpu_has_work()
- SysemuCPUOps::has_work() implementation - to TCG sysemu.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/ppc/cpu-qom.h  |  4 +++-
 target/ppc/cpu_init.c | 24 ++++++++++++++++++------
 2 files changed, 21 insertions(+), 7 deletions(-)

diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index 36110112506..ff2bafcde6f 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -188,8 +188,10 @@ struct PowerPCCPUClass {
     uint32_t flags;
     int bfd_mach;
     uint32_t l1_dcache_size, l1_icache_size;
-    bool (*has_work)(CPUState *cpu);
 #ifndef CONFIG_USER_ONLY
+#ifdef CONFIG_TCG
+    bool (*has_work)(CPUState *cpu);
+#endif /* CONFIG_TCG */
     unsigned int gdb_num_sprs;
     const char *gdb_spr_xml;
 #endif
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 2f7d262b176..5c134adeea9 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -7583,6 +7583,7 @@ static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr)
     return false;
 }
 
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
 static bool cpu_has_work_POWER7(CPUState *cs)
 {
     PowerPCCPU *cpu = POWERPC_CPU(cs);
@@ -7616,6 +7617,7 @@ static bool cpu_has_work_POWER7(CPUState *cs)
         return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
     }
 }
+#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
 
 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
 {
@@ -7629,7 +7631,6 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
     pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
     pcc->init_proc = init_proc_POWER7;
     pcc->check_pow = check_pow_nocheck;
-    pcc->has_work = cpu_has_work_POWER7;
     pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
                        PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
@@ -7672,6 +7673,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
     pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2;
     pcc->mmu_model = POWERPC_MMU_2_06;
 #if defined(CONFIG_SOFTMMU)
+    pcc->has_work = cpu_has_work_POWER7;
     pcc->hash64_opts = &ppc_hash64_opts_POWER7;
     pcc->lrg_decr_bits = 32;
 #endif
@@ -7742,6 +7744,7 @@ static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr)
     return false;
 }
 
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
 static bool cpu_has_work_POWER8(CPUState *cs)
 {
     PowerPCCPU *cpu = POWERPC_CPU(cs);
@@ -7783,6 +7786,7 @@ static bool cpu_has_work_POWER8(CPUState *cs)
         return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
     }
 }
+#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
 
 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
 {
@@ -7796,7 +7800,6 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
     pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
     pcc->init_proc = init_proc_POWER8;
     pcc->check_pow = check_pow_nocheck;
-    pcc->has_work = cpu_has_work_POWER8;
     pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
                        PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
@@ -7846,6 +7849,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
                    LPCR_P8_PECE3 | LPCR_P8_PECE4;
     pcc->mmu_model = POWERPC_MMU_2_07;
 #if defined(CONFIG_SOFTMMU)
+    pcc->has_work = cpu_has_work_POWER8;
     pcc->hash64_opts = &ppc_hash64_opts_POWER7;
     pcc->lrg_decr_bits = 32;
     pcc->n_host_threads = 8;
@@ -7939,6 +7943,7 @@ static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr)
     return false;
 }
 
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
 static bool cpu_has_work_POWER9(CPUState *cs)
 {
     PowerPCCPU *cpu = POWERPC_CPU(cs);
@@ -7996,6 +8001,7 @@ static bool cpu_has_work_POWER9(CPUState *cs)
         return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
     }
 }
+#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
 
 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
 {
@@ -8010,7 +8016,6 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
                          PCR_COMPAT_2_05;
     pcc->init_proc = init_proc_POWER9;
     pcc->check_pow = check_pow_nocheck;
-    pcc->has_work = cpu_has_work_POWER9;
     pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
                        PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
@@ -8059,6 +8064,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
     pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
     pcc->mmu_model = POWERPC_MMU_3_00;
 #if defined(CONFIG_SOFTMMU)
+    pcc->has_work = cpu_has_work_POWER9;
     /* segment page size remain the same */
     pcc->hash64_opts = &ppc_hash64_opts_POWER7;
     pcc->radix_page_info = &POWER9_radix_page_info;
@@ -8147,6 +8153,7 @@ static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr)
     return false;
 }
 
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
 static bool cpu_has_work_POWER10(CPUState *cs)
 {
     PowerPCCPU *cpu = POWERPC_CPU(cs);
@@ -8204,6 +8211,7 @@ static bool cpu_has_work_POWER10(CPUState *cs)
         return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
     }
 }
+#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
 
 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
 {
@@ -8219,7 +8227,6 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
                          PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
     pcc->init_proc = init_proc_POWER10;
     pcc->check_pow = check_pow_nocheck;
-    pcc->has_work = cpu_has_work_POWER10;
     pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
                        PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
@@ -8271,6 +8278,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
     pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
     pcc->mmu_model = POWERPC_MMU_3_00;
 #if defined(CONFIG_SOFTMMU)
+    pcc->has_work = cpu_has_work_POWER10;
     /* segment page size remain the same */
     pcc->hash64_opts = &ppc_hash64_opts_POWER7;
     pcc->radix_page_info = &POWER10_radix_page_info;
@@ -8786,6 +8794,7 @@ static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
     cpu->env.nip = value;
 }
 
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
 static bool cpu_has_work_default(CPUState *cs)
 {
     PowerPCCPU *cpu = POWERPC_CPU(cs);
@@ -8801,6 +8810,7 @@ static bool ppc_cpu_has_work(CPUState *cs)
 
     return pcc->has_work(cs);
 }
+#endif /* CONFIG_TCG && !CONFIG_USER_ONLY */
 
 static void ppc_cpu_reset(DeviceState *dev)
 {
@@ -9021,6 +9031,7 @@ static const struct TCGCPUOps ppc_tcg_ops = {
   .tlb_fill = ppc_cpu_tlb_fill,
 
 #ifndef CONFIG_USER_ONLY
+  .has_work = ppc_cpu_has_work,
   .cpu_exec_interrupt = ppc_cpu_exec_interrupt,
   .do_interrupt = ppc_cpu_do_interrupt,
   .cpu_exec_enter = ppc_cpu_exec_enter,
@@ -9041,13 +9052,11 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
     device_class_set_parent_unrealize(dc, ppc_cpu_unrealize,
                                       &pcc->parent_unrealize);
     pcc->pvr_match = ppc_pvr_match_default;
-    pcc->has_work = cpu_has_work_default;
     device_class_set_props(dc, ppc_cpu_properties);
 
     device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset);
 
     cc->class_by_name = ppc_cpu_class_by_name;
-    cc->has_work = ppc_cpu_has_work;
     cc->dump_state = ppc_cpu_dump_state;
     cc->set_pc = ppc_cpu_set_pc;
     cc->gdb_read_register = ppc_cpu_gdb_read_register;
@@ -9078,6 +9087,9 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
 
 #ifdef CONFIG_TCG
     cc->tcg_ops = &ppc_tcg_ops;
+#ifndef CONFIG_USER_ONLY
+    pcc->has_work = cpu_has_work_default;
+#endif
 #endif /* CONFIG_TCG */
 }
 
-- 
2.31.1



  parent reply	other threads:[~2021-09-25 15:17 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-25 14:50 [PATCH v7 00/40] accel: Move has_work() from CPUClass to AccelOpsClass Philippe Mathieu-Daudé
2021-09-25 14:50 ` [PATCH v7 01/40] accel: Simplify qemu_init_vcpu() Philippe Mathieu-Daudé
2021-09-25 15:25   ` Richard Henderson
2021-09-25 14:50 ` [PATCH v7 02/40] hw/core: Restrict cpu_has_work() to sysemu Philippe Mathieu-Daudé
2021-09-25 14:50 ` [PATCH v7 03/40] hw/core: Un-inline cpu_has_work() Philippe Mathieu-Daudé
2021-09-25 14:50 ` [PATCH v7 04/40] hw/core: Move cpu_common_has_work() to cpu_has_work() Philippe Mathieu-Daudé
2021-09-25 14:50 ` [PATCH v7 05/40] accel: Introduce AccelOpsClass::has_work() Philippe Mathieu-Daudé
2021-09-25 14:50 ` [PATCH v7 06/40] accel/kvm: Implement AccelOpsClass::has_work() Philippe Mathieu-Daudé
2021-09-25 14:50   ` Philippe Mathieu-Daudé
2021-09-25 14:50 ` [PATCH v7 07/40] accel/whpx: " Philippe Mathieu-Daudé
2021-09-25 14:50 ` [PATCH v7 08/40] accel/hvf: " Philippe Mathieu-Daudé
2021-09-25 14:50 ` [PATCH v7 09/40] accel/xen: " Philippe Mathieu-Daudé
2021-09-25 14:50   ` Philippe Mathieu-Daudé
2021-09-25 14:50 ` [PATCH v7 10/40] accel/hax: " Philippe Mathieu-Daudé
2021-09-25 14:50 ` [PATCH v7 11/40] accel/nvmm: " Philippe Mathieu-Daudé
2021-09-25 14:50 ` [PATCH v7 12/40] accel/qtest: " Philippe Mathieu-Daudé
2021-09-25 15:27   ` Philippe Mathieu-Daudé
2021-09-25 15:32     ` Richard Henderson
2021-09-25 16:01       ` Philippe Mathieu-Daudé
2021-09-27  6:12         ` Laurent Vivier
2021-09-25 14:50 ` [PATCH v7 13/40] accel/tcg: " Philippe Mathieu-Daudé
2021-09-25 14:50 ` [PATCH v7 14/40] accel: Simplify cpu_has_work() Philippe Mathieu-Daudé
2021-09-25 14:50 ` [PATCH v7 15/40] accel/tcg: Introduce TCGCPUOps::has_work() Philippe Mathieu-Daudé
2021-09-25 14:50 ` [PATCH v7 16/40] target/arm: Explicit v7M cores use arm_cpu_has_work as CPUClass:has_work Philippe Mathieu-Daudé
2021-09-25 14:50 ` [PATCH v7 17/40] target/arm: Restrict has_work() handler to sysemu and TCG Philippe Mathieu-Daudé
2021-09-25 14:50 ` [PATCH v7 18/40] target/alpha: Restrict has_work() handler to sysemu Philippe Mathieu-Daudé
2021-09-25 14:50 ` [PATCH v7 19/40] target/avr: " Philippe Mathieu-Daudé
2021-09-25 14:50 ` [PATCH v7 20/40] target/cris: " Philippe Mathieu-Daudé
2021-09-25 14:50 ` [PATCH v7 21/40] target/hexagon: Remove unused has_work() handler Philippe Mathieu-Daudé
2021-09-25 14:51 ` [PATCH v7 22/40] target/hppa: Restrict has_work() handler to sysemu Philippe Mathieu-Daudé
2021-09-25 14:51 ` [PATCH v7 23/40] target/i386: Restrict has_work() handler to sysemu and TCG Philippe Mathieu-Daudé
2021-09-25 14:51 ` [PATCH v7 24/40] target/m68k: Restrict has_work() handler to sysemu Philippe Mathieu-Daudé
2021-09-25 14:51 ` [PATCH v7 25/40] target/microblaze: " Philippe Mathieu-Daudé
2021-09-25 14:51 ` [PATCH v7 26/40] target/mips: Restrict has_work() handler to sysemu and TCG Philippe Mathieu-Daudé
2021-09-25 14:51 ` [PATCH v7 27/40] target/nios2: Restrict has_work() handler to sysemu Philippe Mathieu-Daudé
2021-09-25 14:51 ` [PATCH v7 28/40] target/openrisc: " Philippe Mathieu-Daudé
2021-09-25 14:51 ` [PATCH v7 29/40] target/ppc: Introduce PowerPCCPUClass::has_work() Philippe Mathieu-Daudé
2021-09-25 14:51 ` Philippe Mathieu-Daudé [this message]
2021-09-25 14:51 ` [PATCH v7 31/40] target/riscv: Restrict has_work() handler to sysemu and TCG Philippe Mathieu-Daudé
2021-09-25 14:51   ` Philippe Mathieu-Daudé
2021-09-25 14:51 ` [PATCH v7 32/40] target/rx: Restrict has_work() handler to sysemu Philippe Mathieu-Daudé
2021-09-25 14:51 ` [PATCH v7 33/40] target/s390x: Restrict has_work() handler to sysemu and TCG Philippe Mathieu-Daudé
2021-09-25 14:51 ` [PATCH v7 34/40] target/sh4: Restrict has_work() handler to sysemu Philippe Mathieu-Daudé
2021-09-25 14:51 ` [PATCH v7 35/40] target/sparc: Remove pointless use of CONFIG_TCG definition Philippe Mathieu-Daudé
2021-09-25 14:51 ` [PATCH v7 36/40] target/sparc: Restrict has_work() handler to sysemu Philippe Mathieu-Daudé
2021-09-25 14:51 ` [PATCH v7 37/40] target/tricore: " Philippe Mathieu-Daudé
2021-09-25 14:51 ` [PATCH v7 38/40] target/xtensa: " Philippe Mathieu-Daudé
2021-09-25 14:51 ` [PATCH v7 39/40] accel/tcg: Remove CPUClass::has_work() Philippe Mathieu-Daudé
2021-09-25 14:51 ` [PATCH v7 40/40] accel/tcg: Simplify tcg_cpu_has_work() Philippe Mathieu-Daudé
2021-09-25 15:28 ` [PATCH v7 00/40] accel: Move has_work() from CPUClass to AccelOpsClass Richard Henderson
2021-09-25 15:36   ` Philippe Mathieu-Daudé

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