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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 11/22] docs/system/arm: xlnx-versal-virt: BBRAM and eFUSE Usage
Date: Thu, 30 Sep 2021 16:11:50 +0100	[thread overview]
Message-ID: <20210930151201.9407-12-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210930151201.9407-1-peter.maydell@linaro.org>

From: Tong Ho <tong.ho@xilinx.com>

Add BBRAM and eFUSE usage to the Xilinx Versal Virt board
document.

Signed-off-by: Tong Ho <tong.ho@xilinx.com>
Message-id: 20210917052400.1249094-10-tong.ho@xilinx.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 docs/system/arm/xlnx-versal-virt.rst | 49 ++++++++++++++++++++++++++++
 1 file changed, 49 insertions(+)

diff --git a/docs/system/arm/xlnx-versal-virt.rst b/docs/system/arm/xlnx-versal-virt.rst
index 27f73500d95..92ad10d2da4 100644
--- a/docs/system/arm/xlnx-versal-virt.rst
+++ b/docs/system/arm/xlnx-versal-virt.rst
@@ -32,6 +32,8 @@ Implemented devices:
 - OCM (256KB of On Chip Memory)
 - XRAM (4MB of on chip Accelerator RAM)
 - DDR memory
+- BBRAM (36 bytes of Battery-backed RAM)
+- eFUSE (3072 bytes of one-time field-programmable bit array)
 
 QEMU does not yet model any other devices, including the PL and the AI Engine.
 
@@ -175,3 +177,50 @@ Run the following at the U-Boot prompt:
   fdt set /chosen/dom0 reg <0x00000000 0x40000000 0x0 0x03100000>
   booti 30000000 - 20000000
 
+BBRAM File Backend
+""""""""""""""""""
+BBRAM can have an optional file backend, which must be a seekable
+binary file with a size of 36 bytes or larger. A file with all
+binary 0s is a 'blank'.
+
+To add a file-backend for the BBRAM:
+
+.. code-block:: bash
+
+  -drive if=pflash,index=0,file=versal-bbram.bin,format=raw
+
+To use a different index value, N, from default of 0, add:
+
+.. code-block:: bash
+
+  -global xlnx,bbram-ctrl.drive-index=N
+
+eFUSE File Backend
+""""""""""""""""""
+eFUSE can have an optional file backend, which must be a seekable
+binary file with a size of 3072 bytes or larger. A file with all
+binary 0s is a 'blank'.
+
+To add a file-backend for the eFUSE:
+
+.. code-block:: bash
+
+  -drive if=pflash,index=1,file=versal-efuse.bin,format=raw
+
+To use a different index value, N, from default of 1, add:
+
+.. code-block:: bash
+
+  -global xlnx,efuse.drive-index=N
+
+.. warning::
+  In actual physical Versal, BBRAM and eFUSE contain sensitive data.
+  The QEMU device models do **not** encrypt nor obfuscate any data
+  when holding them in models' memory or when writing them to their
+  file backends.
+
+  Thus, a file backend should be used with caution, and 'format=luks'
+  is highly recommended (albeit with usage complexity).
+
+  Better yet, do not use actual product data when running guest image
+  on this Xilinx Versal Virt board.
-- 
2.20.1



  parent reply	other threads:[~2021-09-30 15:21 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-30 15:11 [PULL 00/22] target-arm queue Peter Maydell
2021-09-30 15:11 ` [PULL 01/22] allwinner-h3: Switch to SMC as PSCI conduit Peter Maydell
2021-09-30 15:11 ` [PULL 02/22] arm: tcg: Adhere to SMCCC 1.3 section 5.2 Peter Maydell
2021-11-18 21:57   ` Peter Maydell
2021-11-19 10:35     ` Alexander Graf
2021-11-19 14:15       ` Peter Maydell
2021-09-30 15:11 ` [PULL 03/22] hw/nvram: Introduce Xilinx eFuse QOM Peter Maydell
2021-09-30 15:11 ` [PULL 04/22] hw/nvram: Introduce Xilinx Versal eFuse device Peter Maydell
2021-09-30 15:11 ` [PULL 05/22] hw/nvram: Introduce Xilinx ZynqMP " Peter Maydell
2021-09-30 15:11 ` [PULL 06/22] hw/nvram: Introduce Xilinx battery-backed ram Peter Maydell
2022-04-01 14:23   ` Peter Maydell
2021-09-30 15:11 ` [PULL 07/22] hw/arm: xlnx-versal-virt: Add Xilinx BBRAM device Peter Maydell
2021-09-30 15:11 ` [PULL 08/22] hw/arm: xlnx-versal-virt: Add Xilinx eFUSE device Peter Maydell
2021-09-30 15:11 ` [PULL 09/22] hw/arm: xlnx-zcu102: Add Xilinx BBRAM device Peter Maydell
2021-09-30 15:11 ` [PULL 10/22] hw/arm: xlnx-zcu102: Add Xilinx eFUSE device Peter Maydell
2021-09-30 15:11 ` Peter Maydell [this message]
2021-09-30 15:11 ` [PULL 12/22] configs: Don't include 32-bit-only GDB XML in aarch64 linux configs Peter Maydell
2021-09-30 15:11 ` [PULL 13/22] target/arm: Fix coding style issues in gdbstub code in helper.c Peter Maydell
2021-09-30 15:11 ` [PULL 14/22] target/arm: Move gdbstub related code out of helper.c Peter Maydell
2021-09-30 15:11 ` [PULL 15/22] target/arm: Don't put FPEXC and FPSID in org.gnu.gdb.arm.vfp XML Peter Maydell
2021-09-30 15:11 ` [PULL 16/22] scsi: Replace scsi_bus_new() with scsi_bus_init(), scsi_bus_init_named() Peter Maydell
2021-09-30 15:11 ` [PULL 17/22] ipack: Rename ipack_bus_new_inplace() to ipack_bus_init() Peter Maydell
2021-09-30 15:11 ` [PULL 18/22] pci: Rename pci_root_bus_new_inplace() to pci_root_bus_init() Peter Maydell
2021-09-30 15:11 ` [PULL 19/22] qbus: Rename qbus_create_inplace() to qbus_init() Peter Maydell
2021-09-30 15:11 ` [PULL 20/22] qbus: Rename qbus_create() to qbus_new() Peter Maydell
2021-09-30 15:12 ` [PULL 21/22] ide: Rename ide_bus_new() to ide_bus_init() Peter Maydell
2021-09-30 15:12 ` [PULL 22/22] hw/arm: sabrelite: Connect SPI flash CS line to GPIO3_19 Peter Maydell
2021-10-01  9:27 ` [PULL 00/22] target-arm queue Peter Maydell

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