From: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
To: Harry Wentland <harry.wentland@amd.com>
Cc: Fangzhi Zuo <Jerry.Zuo@amd.com>,
dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org, jani.nikula@intel.com,
Nicholas.Kazlauskas@amd.com, wayne.lin@amd.com
Subject: Re: [PATCH v3] drm/dp: Add Additional DP2 Headers
Date: Thu, 30 Sep 2021 17:21:13 -0400 [thread overview]
Message-ID: <20210930212113.rsy5lbg3mhejvsdo@outlook.office365.com> (raw)
In-Reply-To: <b2ce7b34-23f1-75c8-182e-3e7fe9b845e1@amd.com>
Applied to drm-misc-next.
Thanks
On 09/28, Harry Wentland wrote:
> On 2021-09-27 15:23, Fangzhi Zuo wrote:
> > Include FEC, DSC, Link Training related headers.
> >
> > Change since v2
> > - Align with the spec for DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT
> >
> > Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
>
> Reviewed-by: Harry Wentland <harry.wentland@amd.com>
>
> Harry
>
> > ---
> > This patch is based on top of the other DP2.0 work in
> > "drm/dp: add LTTPR DP 2.0 DPCD addresses"
> > ---
> > include/drm/drm_dp_helper.h | 20 ++++++++++++++++++++
> > 1 file changed, 20 insertions(+)
> >
> > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> > index 1d5b3dbb6e56..a1df35aa6e68 100644
> > --- a/include/drm/drm_dp_helper.h
> > +++ b/include/drm/drm_dp_helper.h
> > @@ -453,6 +453,7 @@ struct drm_panel;
> > # define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1)
> > # define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2)
> > # define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3)
> > +#define DP_FEC_CAPABILITY_1 0x091 /* 2.0 */
> >
> > /* DP-HDMI2.1 PCON DSC ENCODER SUPPORT */
> > #define DP_PCON_DSC_ENCODER_CAP_SIZE 0xC /* 0x9E - 0x92 */
> > @@ -537,6 +538,9 @@ struct drm_panel;
> > #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1
> > #define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2
> >
> > +/* DFP Capability Extension */
> > +#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > +
> > /* Link Configuration */
> > #define DP_LINK_BW_SET 0x100
> > # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
> > @@ -688,6 +692,7 @@ struct drm_panel;
> >
> > #define DP_DSC_ENABLE 0x160 /* DP 1.4 */
> > # define DP_DECOMPRESSION_EN (1 << 0)
> > +#define DP_DSC_CONFIGURATION 0x161 /* DP 2.0 */
> >
> > #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
> > # define DP_PSR_ENABLE BIT(0)
> > @@ -743,6 +748,7 @@ struct drm_panel;
> > # define DP_RECEIVE_PORT_0_STATUS (1 << 0)
> > # define DP_RECEIVE_PORT_1_STATUS (1 << 1)
> > # define DP_STREAM_REGENERATION_STATUS (1 << 2) /* 2.0 */
> > +# define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) /* 2.0 */
> >
> > #define DP_ADJUST_REQUEST_LANE0_1 0x206
> > #define DP_ADJUST_REQUEST_LANE2_3 0x207
> > @@ -865,6 +871,8 @@ struct drm_panel;
> > # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4
> > # define DP_PHY_TEST_PATTERN_CP2520 0x5
> >
> > +#define DP_PHY_SQUARE_PATTERN 0x249
> > +
> > #define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A
> > #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
> > #define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251
> > @@ -1109,6 +1117,18 @@ struct drm_panel;
> > #define DP_128B132B_TRAINING_AUX_RD_INTERVAL 0x2216 /* 2.0 */
> > # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f
> >
> > +#define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0x2230
> > +#define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0x2250
> > +
> > +/* DSC Extended Capability Branch Total DSC Resources */
> > +#define DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT 0x2260 /* 2.0 */
> > +# define DP_DSC_DECODER_COUNT_MASK (0b111 << 5)
> > +# define DP_DSC_DECODER_COUNT_SHIFT 5
> > +#define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 /* 2.0 */
> > +# define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0)
> > +# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1)
> > +# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1
> > +
> > /* Protocol Converter Extension */
> > /* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */
> > #define DP_CEC_TUNNELING_CAPABILITY 0x3000
> >
>
--
Rodrigo Siqueira
https://siqueira.tech
WARNING: multiple messages have this Message-ID (diff)
From: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
To: Harry Wentland <harry.wentland@amd.com>
Cc: Fangzhi Zuo <Jerry.Zuo@amd.com>,
dri-devel@lists.freedesktop.org, amd-gfx@lists.freedesktop.org,
intel-gfx@lists.freedesktop.org, jani.nikula@intel.com,
Nicholas.Kazlauskas@amd.com, wayne.lin@amd.com
Subject: Re: [Intel-gfx] [PATCH v3] drm/dp: Add Additional DP2 Headers
Date: Thu, 30 Sep 2021 17:21:13 -0400 [thread overview]
Message-ID: <20210930212113.rsy5lbg3mhejvsdo@outlook.office365.com> (raw)
In-Reply-To: <b2ce7b34-23f1-75c8-182e-3e7fe9b845e1@amd.com>
Applied to drm-misc-next.
Thanks
On 09/28, Harry Wentland wrote:
> On 2021-09-27 15:23, Fangzhi Zuo wrote:
> > Include FEC, DSC, Link Training related headers.
> >
> > Change since v2
> > - Align with the spec for DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT
> >
> > Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
>
> Reviewed-by: Harry Wentland <harry.wentland@amd.com>
>
> Harry
>
> > ---
> > This patch is based on top of the other DP2.0 work in
> > "drm/dp: add LTTPR DP 2.0 DPCD addresses"
> > ---
> > include/drm/drm_dp_helper.h | 20 ++++++++++++++++++++
> > 1 file changed, 20 insertions(+)
> >
> > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> > index 1d5b3dbb6e56..a1df35aa6e68 100644
> > --- a/include/drm/drm_dp_helper.h
> > +++ b/include/drm/drm_dp_helper.h
> > @@ -453,6 +453,7 @@ struct drm_panel;
> > # define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP (1 << 1)
> > # define DP_FEC_CORR_BLK_ERROR_COUNT_CAP (1 << 2)
> > # define DP_FEC_BIT_ERROR_COUNT_CAP (1 << 3)
> > +#define DP_FEC_CAPABILITY_1 0x091 /* 2.0 */
> >
> > /* DP-HDMI2.1 PCON DSC ENCODER SUPPORT */
> > #define DP_PCON_DSC_ENCODER_CAP_SIZE 0xC /* 0x9E - 0x92 */
> > @@ -537,6 +538,9 @@ struct drm_panel;
> > #define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1
> > #define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2
> >
> > +/* DFP Capability Extension */
> > +#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> > +
> > /* Link Configuration */
> > #define DP_LINK_BW_SET 0x100
> > # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
> > @@ -688,6 +692,7 @@ struct drm_panel;
> >
> > #define DP_DSC_ENABLE 0x160 /* DP 1.4 */
> > # define DP_DECOMPRESSION_EN (1 << 0)
> > +#define DP_DSC_CONFIGURATION 0x161 /* DP 2.0 */
> >
> > #define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */
> > # define DP_PSR_ENABLE BIT(0)
> > @@ -743,6 +748,7 @@ struct drm_panel;
> > # define DP_RECEIVE_PORT_0_STATUS (1 << 0)
> > # define DP_RECEIVE_PORT_1_STATUS (1 << 1)
> > # define DP_STREAM_REGENERATION_STATUS (1 << 2) /* 2.0 */
> > +# define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) /* 2.0 */
> >
> > #define DP_ADJUST_REQUEST_LANE0_1 0x206
> > #define DP_ADJUST_REQUEST_LANE2_3 0x207
> > @@ -865,6 +871,8 @@ struct drm_panel;
> > # define DP_PHY_TEST_PATTERN_80BIT_CUSTOM 0x4
> > # define DP_PHY_TEST_PATTERN_CP2520 0x5
> >
> > +#define DP_PHY_SQUARE_PATTERN 0x249
> > +
> > #define DP_TEST_HBR2_SCRAMBLER_RESET 0x24A
> > #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250
> > #define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251
> > @@ -1109,6 +1117,18 @@ struct drm_panel;
> > #define DP_128B132B_TRAINING_AUX_RD_INTERVAL 0x2216 /* 2.0 */
> > # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f
> >
> > +#define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0x2230
> > +#define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0x2250
> > +
> > +/* DSC Extended Capability Branch Total DSC Resources */
> > +#define DP_DSC_SUPPORT_AND_DSC_DECODER_COUNT 0x2260 /* 2.0 */
> > +# define DP_DSC_DECODER_COUNT_MASK (0b111 << 5)
> > +# define DP_DSC_DECODER_COUNT_SHIFT 5
> > +#define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 /* 2.0 */
> > +# define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0)
> > +# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1)
> > +# define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1
> > +
> > /* Protocol Converter Extension */
> > /* HDMI CEC tunneling over AUX DP 1.3 section 5.3.3.3.1 DPCD 1.4+ */
> > #define DP_CEC_TUNNELING_CAPABILITY 0x3000
> >
>
--
Rodrigo Siqueira
https://siqueira.tech
next prev parent reply other threads:[~2021-09-30 21:21 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-27 19:23 [PATCH v3] drm/dp: Add Additional DP2 Headers Fangzhi Zuo
2021-09-27 19:23 ` [Intel-gfx] " Fangzhi Zuo
2021-09-28 12:28 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/dp: Add Additional DP2 Headers (rev3) Patchwork
2021-09-28 12:55 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-28 14:17 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-09-28 15:19 ` [PATCH v3] drm/dp: Add Additional DP2 Headers Harry Wentland
2021-09-28 15:19 ` [Intel-gfx] " Harry Wentland
2021-09-30 21:21 ` Rodrigo Siqueira [this message]
2021-09-30 21:21 ` Rodrigo Siqueira
2021-10-08 8:36 ` Tvrtko Ursulin
2021-10-08 8:36 ` [Intel-gfx] " Tvrtko Ursulin
2021-10-08 21:03 ` Harry Wentland
2021-10-08 21:03 ` [Intel-gfx] " Harry Wentland
2022-02-03 11:58 ` binary constants (was: Re: [PATCH v3] drm/dp: Add Additional DP2 Headers) Jani Nikula
2022-02-03 11:58 ` Jani Nikula
2022-02-03 11:58 ` [Intel-gfx] " Jani Nikula
2022-02-03 12:57 ` Daniel Vetter
2022-02-03 12:57 ` Daniel Vetter
2022-02-03 12:57 ` [Intel-gfx] " Daniel Vetter
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210930212113.rsy5lbg3mhejvsdo@outlook.office365.com \
--to=rodrigo.siqueira@amd.com \
--cc=Jerry.Zuo@amd.com \
--cc=Nicholas.Kazlauskas@amd.com \
--cc=amd-gfx@lists.freedesktop.org \
--cc=dri-devel@lists.freedesktop.org \
--cc=harry.wentland@amd.com \
--cc=intel-gfx@lists.freedesktop.org \
--cc=jani.nikula@intel.com \
--cc=wayne.lin@amd.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.