* [PATCH] target/mips: Remove unused register from MSA 2R/2RF instruction format
@ 2021-10-03 0:25 Philippe Mathieu-Daudé
2021-10-03 13:55 ` Richard Henderson
0 siblings, 1 reply; 2+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-10-03 0:25 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Richard Henderson, Aurelien Jarno,
Philippe Mathieu-Daudé
MSA 2R/2RF instructions don't use any target vector register.
Remove the unused TCG temporaries.
Fixes: cbe50b9a8e7 ("target-mips: add MSA VEC/2R format instructions")
Fixes: 3bdeb68866e ("target-mips: add MSA 2RF format instructions")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/tcg/msa_translate.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 8170a8df26b..ee6424126f7 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -1942,13 +1942,11 @@ static void gen_msa_2r(DisasContext *ctx)
{
#define MASK_MSA_2R(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
(op & (0x7 << 18)))
- uint8_t wt = (ctx->opcode >> 16) & 0x1f;
uint8_t ws = (ctx->opcode >> 11) & 0x1f;
uint8_t wd = (ctx->opcode >> 6) & 0x1f;
uint8_t df = (ctx->opcode >> 16) & 0x3;
TCGv_i32 twd = tcg_const_i32(wd);
TCGv_i32 tws = tcg_const_i32(ws);
- TCGv_i32 twt = tcg_const_i32(wt);
TCGv_i32 tdf = tcg_const_i32(df);
switch (MASK_MSA_2R(ctx->opcode)) {
@@ -2018,7 +2016,6 @@ static void gen_msa_2r(DisasContext *ctx)
tcg_temp_free_i32(twd);
tcg_temp_free_i32(tws);
- tcg_temp_free_i32(twt);
tcg_temp_free_i32(tdf);
}
@@ -2026,13 +2023,11 @@ static void gen_msa_2rf(DisasContext *ctx)
{
#define MASK_MSA_2RF(op) (MASK_MSA_MINOR(op) | (op & (0x1f << 21)) | \
(op & (0xf << 17)))
- uint8_t wt = (ctx->opcode >> 16) & 0x1f;
uint8_t ws = (ctx->opcode >> 11) & 0x1f;
uint8_t wd = (ctx->opcode >> 6) & 0x1f;
uint8_t df = (ctx->opcode >> 16) & 0x1;
TCGv_i32 twd = tcg_const_i32(wd);
TCGv_i32 tws = tcg_const_i32(ws);
- TCGv_i32 twt = tcg_const_i32(wt);
/* adjust df value for floating-point instruction */
TCGv_i32 tdf = tcg_const_i32(df + 2);
@@ -2089,7 +2084,6 @@ static void gen_msa_2rf(DisasContext *ctx)
tcg_temp_free_i32(twd);
tcg_temp_free_i32(tws);
- tcg_temp_free_i32(twt);
tcg_temp_free_i32(tdf);
}
--
2.31.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] target/mips: Remove unused register from MSA 2R/2RF instruction format
2021-10-03 0:25 [PATCH] target/mips: Remove unused register from MSA 2R/2RF instruction format Philippe Mathieu-Daudé
@ 2021-10-03 13:55 ` Richard Henderson
0 siblings, 0 replies; 2+ messages in thread
From: Richard Henderson @ 2021-10-03 13:55 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel; +Cc: Aleksandar Rikalo, Aurelien Jarno
On 10/2/21 8:25 PM, Philippe Mathieu-Daudé wrote:
> MSA 2R/2RF instructions don't use any target vector register.
> Remove the unused TCG temporaries.
>
> Fixes: cbe50b9a8e7 ("target-mips: add MSA VEC/2R format instructions")
> Fixes: 3bdeb68866e ("target-mips: add MSA 2RF format instructions")
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
> target/mips/tcg/msa_translate.c | 6 ------
> 1 file changed, 6 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 2+ messages in thread
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2021-10-03 0:25 [PATCH] target/mips: Remove unused register from MSA 2R/2RF instruction format Philippe Mathieu-Daudé
2021-10-03 13:55 ` Richard Henderson
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