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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: David Hildenbrand <david@redhat.com>
Subject: [PULL 22/28] tcg/s390x: Implement andc, orc, abs, neg, not vector operations
Date: Wed,  6 Oct 2021 08:20:08 -0700	[thread overview]
Message-ID: <20211006152014.741026-23-richard.henderson@linaro.org> (raw)
In-Reply-To: <20211006152014.741026-1-richard.henderson@linaro.org>

These logical and arithmetic operations are optional but trivial.

Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/s390x/tcg-target-con-set.h |  1 +
 tcg/s390x/tcg-target.h         | 11 ++++++-----
 tcg/s390x/tcg-target.c.inc     | 32 ++++++++++++++++++++++++++++++++
 3 files changed, 39 insertions(+), 5 deletions(-)

diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h
index ce9432cfe3..cb953896d5 100644
--- a/tcg/s390x/tcg-target-con-set.h
+++ b/tcg/s390x/tcg-target-con-set.h
@@ -17,6 +17,7 @@ C_O0_I2(v, r)
 C_O1_I1(r, L)
 C_O1_I1(r, r)
 C_O1_I1(v, r)
+C_O1_I1(v, v)
 C_O1_I1(v, vr)
 C_O1_I2(r, 0, ri)
 C_O1_I2(r, 0, rI)
diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h
index 5a03c5f2f4..a42074e451 100644
--- a/tcg/s390x/tcg-target.h
+++ b/tcg/s390x/tcg-target.h
@@ -64,6 +64,7 @@ typedef enum TCGReg {
 #define FACILITY_DISTINCT_OPS         FACILITY_LOAD_ON_COND
 #define FACILITY_LOAD_ON_COND2        53
 #define FACILITY_VECTOR               129
+#define FACILITY_VECTOR_ENH1          135
 
 extern uint64_t s390_facilities[3];
 
@@ -142,11 +143,11 @@ extern uint64_t s390_facilities[3];
 #define TCG_TARGET_HAS_v128           HAVE_FACILITY(VECTOR)
 #define TCG_TARGET_HAS_v256           0
 
-#define TCG_TARGET_HAS_andc_vec       0
-#define TCG_TARGET_HAS_orc_vec        0
-#define TCG_TARGET_HAS_not_vec        0
-#define TCG_TARGET_HAS_neg_vec        0
-#define TCG_TARGET_HAS_abs_vec        0
+#define TCG_TARGET_HAS_andc_vec       1
+#define TCG_TARGET_HAS_orc_vec        HAVE_FACILITY(VECTOR_ENH1)
+#define TCG_TARGET_HAS_not_vec        1
+#define TCG_TARGET_HAS_neg_vec        1
+#define TCG_TARGET_HAS_abs_vec        1
 #define TCG_TARGET_HAS_roti_vec       0
 #define TCG_TARGET_HAS_rots_vec       0
 #define TCG_TARGET_HAS_rotv_vec       0
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index 063f720199..cbad88271a 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -270,13 +270,18 @@ typedef enum S390Opcode {
     VRIb_VGM    = 0xe746,
     VRIc_VREP   = 0xe74d,
 
+    VRRa_VLC    = 0xe7de,
+    VRRa_VLP    = 0xe7df,
     VRRa_VLR    = 0xe756,
     VRRc_VA     = 0xe7f3,
     VRRc_VCEQ   = 0xe7f8,   /* we leave the m5 cs field 0 */
     VRRc_VCH    = 0xe7fb,   /* " */
     VRRc_VCHL   = 0xe7f9,   /* " */
     VRRc_VN     = 0xe768,
+    VRRc_VNC    = 0xe769,
+    VRRc_VNO    = 0xe76b,
     VRRc_VO     = 0xe76a,
+    VRRc_VOC    = 0xe76f,
     VRRc_VS     = 0xe7f7,
     VRRc_VX     = 0xe76d,
     VRRf_VLVGP  = 0xe762,
@@ -2669,6 +2674,16 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
         tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
         break;
 
+    case INDEX_op_abs_vec:
+        tcg_out_insn(s, VRRa, VLP, a0, a1, vece);
+        break;
+    case INDEX_op_neg_vec:
+        tcg_out_insn(s, VRRa, VLC, a0, a1, vece);
+        break;
+    case INDEX_op_not_vec:
+        tcg_out_insn(s, VRRc, VNO, a0, a1, a1, 0);
+        break;
+
     case INDEX_op_add_vec:
         tcg_out_insn(s, VRRc, VA, a0, a1, a2, vece);
         break;
@@ -2678,9 +2693,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
     case INDEX_op_and_vec:
         tcg_out_insn(s, VRRc, VN, a0, a1, a2, 0);
         break;
+    case INDEX_op_andc_vec:
+        tcg_out_insn(s, VRRc, VNC, a0, a1, a2, 0);
+        break;
     case INDEX_op_or_vec:
         tcg_out_insn(s, VRRc, VO, a0, a1, a2, 0);
         break;
+    case INDEX_op_orc_vec:
+        tcg_out_insn(s, VRRc, VOC, a0, a1, a2, 0);
+        break;
     case INDEX_op_xor_vec:
         tcg_out_insn(s, VRRc, VX, a0, a1, a2, 0);
         break;
@@ -2711,9 +2732,14 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
 int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
 {
     switch (opc) {
+    case INDEX_op_abs_vec:
     case INDEX_op_add_vec:
     case INDEX_op_and_vec:
+    case INDEX_op_andc_vec:
+    case INDEX_op_neg_vec:
+    case INDEX_op_not_vec:
     case INDEX_op_or_vec:
+    case INDEX_op_orc_vec:
     case INDEX_op_sub_vec:
     case INDEX_op_xor_vec:
         return 1;
@@ -2943,10 +2969,16 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
         return C_O1_I1(v, r);
     case INDEX_op_dup_vec:
         return C_O1_I1(v, vr);
+    case INDEX_op_abs_vec:
+    case INDEX_op_neg_vec:
+    case INDEX_op_not_vec:
+        return C_O1_I1(v, v);
     case INDEX_op_add_vec:
     case INDEX_op_sub_vec:
     case INDEX_op_and_vec:
+    case INDEX_op_andc_vec:
     case INDEX_op_or_vec:
+    case INDEX_op_orc_vec:
     case INDEX_op_xor_vec:
     case INDEX_op_cmp_vec:
         return C_O1_I2(v, v, v);
-- 
2.25.1



  parent reply	other threads:[~2021-10-06 15:49 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-06 15:19 [PULL 00/28] tcg patch queue Richard Henderson
2021-10-06 15:19 ` [PULL 01/28] tests/docker: Remove fedora-i386-cross from DOCKER_PARTIAL_IMAGES Richard Henderson
2021-10-06 15:19 ` [PULL 02/28] tests/docker: Fix fedora-i386-cross cross-compilation Richard Henderson
2021-10-06 15:19 ` [PULL 03/28] tcg: add dup_const_tl wrapper Richard Henderson
2021-10-06 15:19 ` [PULL 04/28] accel/tcg: Drop signness in tracing in cputlb.c Richard Henderson
2021-10-06 15:19 ` [PULL 05/28] tcg: Expand MO_SIZE to 3 bits Richard Henderson
2021-10-06 15:19 ` [PULL 06/28] tcg: Rename TCGMemOpIdx to MemOpIdx Richard Henderson
2021-10-06 15:19 ` [PULL 07/28] tcg: Split out MemOpIdx to exec/memopidx.h Richard Henderson
2021-10-06 15:19 ` [PULL 08/28] trace/mem: Pass MemOpIdx to trace_mem_get_info Richard Henderson
2021-10-06 15:19 ` [PULL 09/28] accel/tcg: Pass MemOpIdx to atomic_trace_*_post Richard Henderson
2021-10-06 15:19 ` [PULL 10/28] plugins: Reorg arguments to qemu_plugin_vcpu_mem_cb Richard Henderson
2021-10-06 15:19 ` [PULL 11/28] trace: Split guest_mem_before Richard Henderson
2021-10-06 15:19 ` [PULL 12/28] hw/core/cpu: Re-sort the non-pointers to the end of CPUClass Richard Henderson
2021-10-06 15:19 ` [PULL 13/28] tcg: Expand usadd/ussub with umin/umax Richard Henderson
2021-10-06 15:20 ` [PULL 14/28] tcg/s390x: Rename from tcg/s390 Richard Henderson
2021-10-06 15:20 ` [PULL 15/28] tcg/s390x: Change FACILITY representation Richard Henderson
2021-10-06 15:20 ` [PULL 16/28] tcg/s390x: Merge TCG_AREG0 and TCG_REG_CALL_STACK into TCGReg Richard Henderson
2021-10-06 15:20 ` [PULL 17/28] tcg/s390x: Add host vector framework Richard Henderson
2021-10-06 15:20 ` [PULL 18/28] tcg/s390x: Implement tcg_out_ld/st for vector types Richard Henderson
2021-10-06 15:20 ` [PULL 19/28] tcg/s390x: Implement tcg_out_mov " Richard Henderson
2021-10-06 15:20 ` [PULL 20/28] tcg/s390x: Implement tcg_out_dup*_vec Richard Henderson
2021-10-06 15:20 ` [PULL 21/28] tcg/s390x: Implement minimal vector operations Richard Henderson
2021-10-06 15:20 ` Richard Henderson [this message]
2021-10-06 15:20 ` [PULL 23/28] tcg/s390x: Implement TCG_TARGET_HAS_mul_vec Richard Henderson
2021-10-06 15:20 ` [PULL 24/28] tcg/s390x: Implement vector shift operations Richard Henderson
2021-10-06 15:20 ` [PULL 25/28] tcg/s390x: Implement TCG_TARGET_HAS_minmax_vec Richard Henderson
2021-10-06 15:20 ` [PULL 26/28] tcg/s390x: Implement TCG_TARGET_HAS_sat_vec Richard Henderson
2021-10-06 15:20 ` [PULL 27/28] tcg/s390x: Implement TCG_TARGET_HAS_bitsel_vec Richard Henderson
2021-10-06 15:20 ` [PULL 28/28] tcg/s390x: Implement TCG_TARGET_HAS_cmpsel_vec Richard Henderson
2021-10-06 18:46 ` [PULL 00/28] tcg patch queue Richard Henderson

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