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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 11/16] drm/i915: Query the vswing levels per-lane for snps phy
Date: Wed,  6 Oct 2021 23:49:32 +0300	[thread overview]
Message-ID: <20211006204937.30774-12-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20211006204937.30774-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Prepare for per-lane drive settings by querying the desired vswing
level per-lane.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_snps_phy.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
index 5e20f340730f..c2251218a39e 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
@@ -58,7 +58,6 @@ void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	const struct intel_ddi_buf_trans *trans;
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
-	int level = intel_ddi_level(encoder, crtc_state, 0);
 	int n_entries, ln;
 
 	trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
@@ -66,6 +65,7 @@ void intel_snps_phy_set_signal_levels(struct intel_encoder *encoder,
 		return;
 
 	for (ln = 0; ln < 4; ln++) {
+		int level = intel_ddi_level(encoder, crtc_state, ln);
 		u32 val = 0;
 
 		val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, trans->entries[level].snps.vswing);
-- 
2.32.0


  parent reply	other threads:[~2021-10-06 20:50 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-06 20:49 [Intel-gfx] [PATCH 00/16] drm/i915: DP per-lane drive settings for icl+ Ville Syrjala
2021-10-06 20:49 ` [Intel-gfx] [PATCH 01/16] drm/i915: Remove pointless extra namespace from dkl/snps buf trans structs Ville Syrjala
2021-10-08 10:18   ` Jani Nikula
2021-10-06 20:49 ` [Intel-gfx] [PATCH 02/16] drm/i915: Shrink {icl_mg, tgl_dkl}_phy_ddi_buf_trans Ville Syrjala
2021-10-08 10:19   ` Jani Nikula
2021-10-06 20:49 ` [Intel-gfx] [PATCH 03/16] drm/i915: Use standard form terminating condition for lane for loops Ville Syrjala
2021-10-08 10:19   ` Jani Nikula
2021-10-06 20:49 ` [Intel-gfx] [PATCH 04/16] drm/i915: Add all per-lane register definitions for icl combo phy Ville Syrjala
2021-10-08 10:21   ` Jani Nikula
2021-10-08 10:29     ` Ville Syrjälä
2021-10-06 20:49 ` [Intel-gfx] [PATCH 05/16] drm/i915: Remove dead DKL_TX_LOADGEN_SHARING_PMD_DISABLE stuff Ville Syrjala
2021-10-08 10:23   ` Jani Nikula
2021-10-06 20:49 ` [Intel-gfx] [PATCH 06/16] drm/i915: Extract icl_combo_phy_loadgen_select() Ville Syrjala
2021-10-08 10:25   ` Jani Nikula
2021-10-06 20:49 ` [Intel-gfx] [PATCH 07/16] drm/i915: Stop using group access when progrmming icl combo phy TX Ville Syrjala
2021-10-29 21:53   ` Souza, Jose
2021-10-06 20:49 ` [Intel-gfx] [PATCH 08/16] drm/i915: Query the vswing levels per-lane for icl combo phy Ville Syrjala
2021-10-29 21:57   ` Souza, Jose
2021-11-01 10:11     ` Ville Syrjälä
2021-11-01 17:36       ` Souza, Jose
2021-10-06 20:49 ` [Intel-gfx] [PATCH 09/16] drm/i915: Query the vswing levels per-lane for icl mg phy Ville Syrjala
2021-10-29 21:59   ` Souza, Jose
2021-11-01  9:56     ` Ville Syrjälä
2021-10-06 20:49 ` [Intel-gfx] [PATCH 10/16] drm/i915: Query the vswing levels per-lane for tgl dkl phy Ville Syrjala
2021-10-29 21:59   ` Souza, Jose
2021-10-06 20:49 ` Ville Syrjala [this message]
2021-10-29 22:00   ` [Intel-gfx] [PATCH 11/16] drm/i915: Query the vswing levels per-lane for snps phy Souza, Jose
2021-10-06 20:49 ` [Intel-gfx] [PATCH 12/16] drm/i915: Enable per-lane drive settings for icl+ Ville Syrjala
2021-10-29 22:04   ` Souza, Jose
2021-10-06 20:49 ` [Intel-gfx] [PATCH 13/16] drm/i915: Use intel_de_rmw() for tgl dkl phy programming Ville Syrjala
2021-10-29 22:01   ` Souza, Jose
2021-10-06 20:49 ` [Intel-gfx] [PATCH 14/16] drm/i915: Use intel_de_rmw() for icl mg " Ville Syrjala
2021-10-29 22:02   ` Souza, Jose
2021-10-06 20:49 ` [Intel-gfx] [PATCH 15/16] drm/i915: Use intel_de_rmw() for icl combo " Ville Syrjala
2021-10-29 22:02   ` Souza, Jose
2021-10-06 20:49 ` [Intel-gfx] [PATCH 16/16] drm/i915: Fix icl+ combo phy static lane power down setup Ville Syrjala
2021-10-28 13:25   ` Imre Deak
2021-10-28 17:43   ` Jani Nikula
2021-10-07  0:18 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: DP per-lane drive settings for icl+ Patchwork
2021-10-07  0:20 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-10-07  0:52 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-10-07  3:08 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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