All of lore.kernel.org
 help / color / mirror / Atom feed
From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 12/16] drm/i915: Enable per-lane drive settings for icl+
Date: Wed,  6 Oct 2021 23:49:33 +0300	[thread overview]
Message-ID: <20211006204937.30774-13-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20211006204937.30774-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Now that the link buf_trans, link training, and the
combo/mg/dkl/snps phy programming are all fixed up we can
allow per-lane DP drive settings on icl+. Make it so.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_link_training.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 1a943ae38a6b..279371237fe9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -301,7 +301,10 @@ static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp,
 static bool has_per_lane_signal_levels(struct intel_dp *intel_dp,
 				       enum drm_dp_phy dp_phy)
 {
-	return !intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy);
+	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+
+	return !intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy) ||
+		DISPLAY_VER(i915) >= 11;
 }
 
 static u8 intel_dp_get_lane_adjust_train(struct intel_dp *intel_dp,
-- 
2.32.0


  parent reply	other threads:[~2021-10-06 20:50 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-06 20:49 [Intel-gfx] [PATCH 00/16] drm/i915: DP per-lane drive settings for icl+ Ville Syrjala
2021-10-06 20:49 ` [Intel-gfx] [PATCH 01/16] drm/i915: Remove pointless extra namespace from dkl/snps buf trans structs Ville Syrjala
2021-10-08 10:18   ` Jani Nikula
2021-10-06 20:49 ` [Intel-gfx] [PATCH 02/16] drm/i915: Shrink {icl_mg, tgl_dkl}_phy_ddi_buf_trans Ville Syrjala
2021-10-08 10:19   ` Jani Nikula
2021-10-06 20:49 ` [Intel-gfx] [PATCH 03/16] drm/i915: Use standard form terminating condition for lane for loops Ville Syrjala
2021-10-08 10:19   ` Jani Nikula
2021-10-06 20:49 ` [Intel-gfx] [PATCH 04/16] drm/i915: Add all per-lane register definitions for icl combo phy Ville Syrjala
2021-10-08 10:21   ` Jani Nikula
2021-10-08 10:29     ` Ville Syrjälä
2021-10-06 20:49 ` [Intel-gfx] [PATCH 05/16] drm/i915: Remove dead DKL_TX_LOADGEN_SHARING_PMD_DISABLE stuff Ville Syrjala
2021-10-08 10:23   ` Jani Nikula
2021-10-06 20:49 ` [Intel-gfx] [PATCH 06/16] drm/i915: Extract icl_combo_phy_loadgen_select() Ville Syrjala
2021-10-08 10:25   ` Jani Nikula
2021-10-06 20:49 ` [Intel-gfx] [PATCH 07/16] drm/i915: Stop using group access when progrmming icl combo phy TX Ville Syrjala
2021-10-29 21:53   ` Souza, Jose
2021-10-06 20:49 ` [Intel-gfx] [PATCH 08/16] drm/i915: Query the vswing levels per-lane for icl combo phy Ville Syrjala
2021-10-29 21:57   ` Souza, Jose
2021-11-01 10:11     ` Ville Syrjälä
2021-11-01 17:36       ` Souza, Jose
2021-10-06 20:49 ` [Intel-gfx] [PATCH 09/16] drm/i915: Query the vswing levels per-lane for icl mg phy Ville Syrjala
2021-10-29 21:59   ` Souza, Jose
2021-11-01  9:56     ` Ville Syrjälä
2021-10-06 20:49 ` [Intel-gfx] [PATCH 10/16] drm/i915: Query the vswing levels per-lane for tgl dkl phy Ville Syrjala
2021-10-29 21:59   ` Souza, Jose
2021-10-06 20:49 ` [Intel-gfx] [PATCH 11/16] drm/i915: Query the vswing levels per-lane for snps phy Ville Syrjala
2021-10-29 22:00   ` Souza, Jose
2021-10-06 20:49 ` Ville Syrjala [this message]
2021-10-29 22:04   ` [Intel-gfx] [PATCH 12/16] drm/i915: Enable per-lane drive settings for icl+ Souza, Jose
2021-10-06 20:49 ` [Intel-gfx] [PATCH 13/16] drm/i915: Use intel_de_rmw() for tgl dkl phy programming Ville Syrjala
2021-10-29 22:01   ` Souza, Jose
2021-10-06 20:49 ` [Intel-gfx] [PATCH 14/16] drm/i915: Use intel_de_rmw() for icl mg " Ville Syrjala
2021-10-29 22:02   ` Souza, Jose
2021-10-06 20:49 ` [Intel-gfx] [PATCH 15/16] drm/i915: Use intel_de_rmw() for icl combo " Ville Syrjala
2021-10-29 22:02   ` Souza, Jose
2021-10-06 20:49 ` [Intel-gfx] [PATCH 16/16] drm/i915: Fix icl+ combo phy static lane power down setup Ville Syrjala
2021-10-28 13:25   ` Imre Deak
2021-10-28 17:43   ` Jani Nikula
2021-10-07  0:18 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: DP per-lane drive settings for icl+ Patchwork
2021-10-07  0:20 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-10-07  0:52 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-10-07  3:08 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20211006204937.30774-13-ville.syrjala@linux.intel.com \
    --to=ville.syrjala@linux.intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.