[Intel-gfx] [PATCH v2 0/4] Panel replay phase1 implementation

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* [Intel-gfx] [PATCH v2 0/4] Panel replay phase1 implementation
@ 2021-10-07 15:57 Animesh Manna
  2021-10-07 15:57 ` [Intel-gfx] [PATCH v2 1/4] drm/i915/panelreplay: HAS_PR() macro added for panel replay Animesh Manna
                   ` (5 more replies)
  0 siblings, 6 replies; 15+ messages in thread
From: Animesh Manna @ 2021-10-07 15:57 UTC (permalink / raw)
  To: intel-gfx
  Cc: gwan-gyeong.mun, mika.kahola, jani.nikula, manasi.d.navare,
	jose.souza, Animesh Manna

Panel Replay is a power saving feature for DP 2.0 monitor and similar
to PSR on EDP.

These patches are basic enablement patches and reused psr
framework to add panel replay related new changes which
may need further fine tuning to fill the gap if there is any.

Note: The patches are not tested due to unavailability of monitor

Animesh Manna (4):
  drm/i915/panelreplay: HAS_PR() macro added for panel replay
  drm/i915/panelreplay: Initializaton and compute config for panel
    replay
  drm/i915/panelreplay: enable/disable panel replay
  drm/i915/panelreplay: Added state checker for panel replay state

 drivers/gpu/drm/i915/display/intel_display.c  |  1 +
 .../drm/i915/display/intel_display_types.h    |  2 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 47 +++++++++---
 drivers/gpu/drm/i915/display/intel_psr.c      | 75 ++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_psr.h      |  3 +
 drivers/gpu/drm/i915/i915_drv.h               |  1 +
 drivers/gpu/drm/i915/i915_reg.h               |  1 +
 include/drm/drm_dp_helper.h                   |  6 ++
 8 files changed, 123 insertions(+), 13 deletions(-)

-- 
2.29.0


^ permalink raw reply	[flat|nested] 15+ messages in thread

* [Intel-gfx] [PATCH v2 1/4] drm/i915/panelreplay: HAS_PR() macro added for panel replay
  2021-10-07 15:57 [Intel-gfx] [PATCH v2 0/4] Panel replay phase1 implementation Animesh Manna
@ 2021-10-07 15:57 ` Animesh Manna
  2021-10-07 16:39   ` Ville Syrjälä
  2021-10-07 15:57 ` [Intel-gfx] [PATCH v2 2/4] drm/i915/panelreplay: Initializaton and compute config " Animesh Manna
                   ` (4 subsequent siblings)
  5 siblings, 1 reply; 15+ messages in thread
From: Animesh Manna @ 2021-10-07 15:57 UTC (permalink / raw)
  To: intel-gfx
  Cc: gwan-gyeong.mun, mika.kahola, jani.nikula, manasi.d.navare,
	jose.souza, Animesh Manna

Platforms having Display 13 and above will support panel
replay feature of DP 2.0 monitor. Added a HAS_PR() macro
to check for panel replay capability.

v1: Initial version.
v2: DISPLAY_VER macro used instead of has_pr flag. [Jose]

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 12256218634f..8db0626337e3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1693,6 +1693,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define HAS_DDI(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_ddi)
 #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
 #define HAS_PSR(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_psr)
+#define HAS_PR(dev_priv)		 (DISPLAY_VER(dev_priv) >= 13)
 #define HAS_PSR_HW_TRACKING(dev_priv) \
 	(INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
 #define HAS_PSR2_SEL_FETCH(dev_priv)	 (GRAPHICS_VER(dev_priv) >= 12)
-- 
2.29.0


^ permalink raw reply related	[flat|nested] 15+ messages in thread

* Re: [Intel-gfx] [PATCH v2 1/4] drm/i915/panelreplay: HAS_PR() macro added for panel replay
  2021-10-07 15:57 ` [Intel-gfx] [PATCH v2 1/4] drm/i915/panelreplay: HAS_PR() macro added for panel replay Animesh Manna
@ 2021-10-07 16:39   ` Ville Syrjälä
  2021-10-07 16:56     ` Manna, Animesh
  2021-10-07 16:59     ` Jani Nikula
  0 siblings, 2 replies; 15+ messages in thread
From: Ville Syrjälä @ 2021-10-07 16:39 UTC (permalink / raw)
  To: Animesh Manna
  Cc: intel-gfx, gwan-gyeong.mun, mika.kahola, jani.nikula,
	manasi.d.navare, jose.souza

On Thu, Oct 07, 2021 at 09:27:26PM +0530, Animesh Manna wrote:
> Platforms having Display 13 and above will support panel
> replay feature of DP 2.0 monitor. Added a HAS_PR() macro
> to check for panel replay capability.
> 
> v1: Initial version.
> v2: DISPLAY_VER macro used instead of has_pr flag. [Jose]
> 
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 12256218634f..8db0626337e3 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1693,6 +1693,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  #define HAS_DDI(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_ddi)
>  #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
>  #define HAS_PSR(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_psr)
> +#define HAS_PR(dev_priv)		 (DISPLAY_VER(dev_priv) >= 13)

Public relations?

>  #define HAS_PSR_HW_TRACKING(dev_priv) \
>  	(INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
>  #define HAS_PSR2_SEL_FETCH(dev_priv)	 (GRAPHICS_VER(dev_priv) >= 12)
> -- 
> 2.29.0

-- 
Ville Syrjälä
Intel

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [Intel-gfx] [PATCH v2 1/4] drm/i915/panelreplay: HAS_PR() macro added for panel replay
  2021-10-07 16:39   ` Ville Syrjälä
@ 2021-10-07 16:56     ` Manna, Animesh
  2021-10-07 16:59     ` Jani Nikula
  1 sibling, 0 replies; 15+ messages in thread
From: Manna, Animesh @ 2021-10-07 16:56 UTC (permalink / raw)
  To: Ville Syrjälä
  Cc: intel-gfx, Mun,  Gwan-gyeong, Kahola, Mika, Nikula, Jani, Navare,
	Manasi D, Souza, Jose



> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Thursday, October 7, 2021 10:10 PM
> To: Manna, Animesh <animesh.manna@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Mun, Gwan-gyeong <gwan-
> gyeong.mun@intel.com>; Kahola, Mika <mika.kahola@intel.com>; Nikula, Jani
> <jani.nikula@intel.com>; Navare, Manasi D <manasi.d.navare@intel.com>;
> Souza, Jose <jose.souza@intel.com>
> Subject: Re: [Intel-gfx] [PATCH v2 1/4] drm/i915/panelreplay: HAS_PR() macro
> added for panel replay
> 
> On Thu, Oct 07, 2021 at 09:27:26PM +0530, Animesh Manna wrote:
> > Platforms having Display 13 and above will support panel replay
> > feature of DP 2.0 monitor. Added a HAS_PR() macro to check for panel
> > replay capability.
> >
> > v1: Initial version.
> > v2: DISPLAY_VER macro used instead of has_pr flag. [Jose]
> >
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h index 12256218634f..8db0626337e3
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1693,6 +1693,7 @@ IS_SUBPLATFORM(const struct drm_i915_private
> *i915,
> >  #define HAS_DDI(dev_priv)		 (INTEL_INFO(dev_priv)-
> >display.has_ddi)
> >  #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)-
> >display.has_fpga_dbg)
> >  #define HAS_PSR(dev_priv)		 (INTEL_INFO(dev_priv)-
> >display.has_psr)
> > +#define HAS_PR(dev_priv)		 (DISPLAY_VER(dev_priv) >= 13)
> 
> Public relations?

Want to have a flag to enable/disable overall feature and useful in future to check power improvement with and without panel replay.
Initial had a feature flag in device_info structure like other features and later make a relation with DISPLAY_VER as per feedback.
https://patchwork.freedesktop.org/patch/452817/?series=94470&rev=1
Should we go back with feature flag or can go ahead with DISPLAY_VER relation?

Regards,
Animesh

> 
> >  #define HAS_PSR_HW_TRACKING(dev_priv) \
> >  	(INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
> >  #define HAS_PSR2_SEL_FETCH(dev_priv)	 (GRAPHICS_VER(dev_priv) >=
> 12)
> > --
> > 2.29.0
> 
> --
> Ville Syrjälä
> Intel

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [Intel-gfx] [PATCH v2 1/4] drm/i915/panelreplay: HAS_PR() macro added for panel replay
  2021-10-07 16:39   ` Ville Syrjälä
  2021-10-07 16:56     ` Manna, Animesh
@ 2021-10-07 16:59     ` Jani Nikula
  1 sibling, 0 replies; 15+ messages in thread
From: Jani Nikula @ 2021-10-07 16:59 UTC (permalink / raw)
  To: Ville Syrjälä, Animesh Manna
  Cc: intel-gfx, gwan-gyeong.mun, mika.kahola, manasi.d.navare, jose.souza

On Thu, 07 Oct 2021, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Thu, Oct 07, 2021 at 09:27:26PM +0530, Animesh Manna wrote:
>> Platforms having Display 13 and above will support panel
>> replay feature of DP 2.0 monitor. Added a HAS_PR() macro
>> to check for panel replay capability.
>> 
>> v1: Initial version.
>> v2: DISPLAY_VER macro used instead of has_pr flag. [Jose]
>> 
>> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_drv.h | 1 +
>>  1 file changed, 1 insertion(+)
>> 
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 12256218634f..8db0626337e3 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1693,6 +1693,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>>  #define HAS_DDI(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_ddi)
>>  #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
>>  #define HAS_PSR(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_psr)
>> +#define HAS_PR(dev_priv)		 (DISPLAY_VER(dev_priv) >= 13)
>
> Public relations?

Yeah, HAS_PANEL_REPLAY() sounds more like it. Also wondering why this
doesn't depend on HAS_DP20() which is what effectively gets done in
patch 2. Sure, it's more restrictive at the moment, but IIUC that's the
dependency.

BR,
Jani.

>
>>  #define HAS_PSR_HW_TRACKING(dev_priv) \
>>  	(INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
>>  #define HAS_PSR2_SEL_FETCH(dev_priv)	 (GRAPHICS_VER(dev_priv) >= 12)
>> -- 
>> 2.29.0

-- 
Jani Nikula, Intel Open Source Graphics Center

^ permalink raw reply	[flat|nested] 15+ messages in thread

* [Intel-gfx] [PATCH v2 2/4] drm/i915/panelreplay: Initializaton and compute config for panel replay
  2021-10-07 15:57 [Intel-gfx] [PATCH v2 0/4] Panel replay phase1 implementation Animesh Manna
  2021-10-07 15:57 ` [Intel-gfx] [PATCH v2 1/4] drm/i915/panelreplay: HAS_PR() macro added for panel replay Animesh Manna
@ 2021-10-07 15:57 ` Animesh Manna
  2021-10-07 17:41   ` Jani Nikula
  2021-10-07 17:41   ` Jani Nikula
  2021-10-07 15:57 ` [Intel-gfx] [PATCH v2 3/4] drm/i915/panelreplay: enable/disable " Animesh Manna
                   ` (3 subsequent siblings)
  5 siblings, 2 replies; 15+ messages in thread
From: Animesh Manna @ 2021-10-07 15:57 UTC (permalink / raw)
  To: intel-gfx
  Cc: gwan-gyeong.mun, mika.kahola, jani.nikula, manasi.d.navare,
	jose.souza, Animesh Manna

As panel replay feature similar to PSR feature of EDP panel, so currently
utilized existing psr framework for panel replay.

v1: RFC version.
v2: optimized code, pr_enabled and pr_dpcd variable removed. [Jose]

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  2 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 47 +++++++++++++++----
 drivers/gpu/drm/i915/display/intel_psr.c      | 43 +++++++++++++++++
 drivers/gpu/drm/i915/display/intel_psr.h      |  3 ++
 include/drm/drm_dp_helper.h                   |  3 ++
 5 files changed, 89 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 21ce8bccc645..b32d9529feef 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1070,6 +1070,7 @@ struct intel_crtc_state {
 	bool req_psr2_sdp_prior_scanline;
 	u32 dc3co_exitline;
 	u16 su_y_granularity;
+	bool has_panel_replay;
 	struct drm_dp_vsc_sdp psr_vsc;
 
 	/*
@@ -1531,6 +1532,7 @@ struct intel_psr {
 	bool irq_aux_error;
 	u16 su_w_granularity;
 	u16 su_y_granularity;
+	bool sink_pr_support;
 	u32 dc3co_exitline;
 	u32 dc3co_exit_delay;
 	struct delayed_work dc3co_work;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 74a657ae131a..45181692e3b0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1569,12 +1569,22 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 
-	/*
-	 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
-	 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
-	 * Colorimetry Format indication.
-	 */
-	vsc->revision = 0x5;
+	if (crtc_state->has_panel_replay) {
+		/*
+		 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
+		 * VSC SDP supporting 3D stereo, Panel Replay, and Pixel
+		 * Encoding/Colorimetry Format indication.
+		 */
+		vsc->revision = 0x7;
+	} else {
+		/*
+		 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
+		 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
+		 * Colorimetry Format indication.
+		 */
+		vsc->revision = 0x5;
+	}
+
 	vsc->length = 0x13;
 
 	/* DP 1.4a spec, Table 2-120 */
@@ -1683,6 +1693,22 @@ void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
 			vsc->revision = 0x4;
 			vsc->length = 0xe;
 		}
+	} else if (intel_dp->psr.enabled && !intel_dp_is_edp(intel_dp)) {
+		if (intel_dp->psr.colorimetry_support &&
+		    intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
+			/* [PR, +Colorimetry] */
+			intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
+							 vsc);
+		} else {
+			/*
+			 * [PR, -Colorimetry]
+			 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
+			 * VSC SDP supporting 3D stereo + PR (applies to eDP v1.3 or
+			 * higher).
+			 */
+			vsc->revision = 0x6;
+			vsc->length = 0x10;
+		}
 	} else {
 		/*
 		 * [PSR1]
@@ -1824,6 +1850,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 
 	intel_vrr_compute_config(pipe_config, conn_state);
 	intel_psr_compute_config(intel_dp, pipe_config, conn_state);
+	intel_panel_replay_compute_config(intel_dp, pipe_config);
 	intel_drrs_compute_config(intel_dp, pipe_config, output_bpp,
 				  constant_n);
 	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
@@ -2731,10 +2758,10 @@ static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
 	sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
 
 	/*
-	 * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
-	 * per DP 1.4a spec.
+	 * Revision 0x5 and 0x7 supports Pixel Encoding/Colorimetry Format as
+	 * per DP 1.4a spec and DP 2.0 spec respectively.
 	 */
-	if (vsc->revision != 0x5)
+	if (vsc->revision != 0x5 || vsc->revision != 0x7)
 		goto out;
 
 	/* VSC SDP Payload for DB16 through DB18 */
@@ -5044,6 +5071,8 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
 
 	intel_psr_init(intel_dp);
 
+	intel_panel_replay_init(intel_dp);
+
 	return true;
 
 fail:
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 7a205fd5023b..935ea1c434ac 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -933,6 +933,21 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 	return true;
 }
 
+void intel_panel_replay_compute_config(struct intel_dp *intel_dp,
+				       struct intel_crtc_state *crtc_state)
+{
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+	if (!intel_dp->psr.sink_pr_support)
+		return;
+
+	crtc_state->has_panel_replay = true;
+	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
+
+	if (HAS_PSR2_SEL_FETCH(dev_priv))
+		intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state);
+}
+
 void intel_psr_compute_config(struct intel_dp *intel_dp,
 			      struct intel_crtc_state *crtc_state,
 			      struct drm_connector_state *conn_state)
@@ -2170,6 +2185,34 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
 	}
 }
 
+/**
+ * intel_panel_replay_init - Check for sink and source capability.
+ * @intel_dp: Intel DP
+ *
+ * This function is called after the initializing connector.
+ * (the initializing of connector treats the handling of connector capabilities)
+ * And it initializes basic panel replay stuff for each DP Encoder.
+ */
+void intel_panel_replay_init(struct intel_dp *intel_dp)
+{
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+	u8 pr_dpcd;
+
+	if (!(HAS_DP20(dev_priv) && HAS_PR(dev_priv)))
+		return;
+
+	drm_dp_dpcd_read(&intel_dp->aux, DP_PANEL_REPLAY_SUPPORT, &pr_dpcd,
+			 sizeof(pr_dpcd));
+
+	if (!(pr_dpcd & PANEL_REPLAY_SUPPORT)) {
+		drm_dbg_kms(&dev_priv->drm,
+			    "Panel replay is not supported by panel\n");
+		return;
+	}
+
+	intel_dp->psr.sink_pr_support = true;
+}
+
 /**
  * intel_psr_init - Init basic PSR work and mutex.
  * @intel_dp: Intel DP
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index facffbacd357..c9d1c1f0b470 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -32,6 +32,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
 		     unsigned frontbuffer_bits,
 		     enum fb_op_origin origin);
 void intel_psr_init(struct intel_dp *intel_dp);
+void intel_panel_replay_init(struct intel_dp *intel_dp);
 void intel_psr_compute_config(struct intel_dp *intel_dp,
 			      struct intel_crtc_state *crtc_state,
 			      struct drm_connector_state *conn_state);
@@ -52,5 +53,7 @@ void intel_psr2_disable_plane_sel_fetch(struct intel_plane *plane,
 					const struct intel_crtc_state *crtc_state);
 void intel_psr_pause(struct intel_dp *intel_dp);
 void intel_psr_resume(struct intel_dp *intel_dp);
+void intel_panel_replay_compute_config(struct intel_dp *intel_dp,
+				       struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_PSR_H__ */
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index b52df4db3e8f..d18340cbf8ac 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -541,6 +541,9 @@ struct drm_panel;
 /* DFP Capability Extension */
 #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT	0x0a3	/* 2.0 */
 
+#define DP_PANEL_REPLAY_SUPPORT             0x0b0
+# define PANEL_REPLAY_SUPPORT               (1 << 0)
+
 /* Link Configuration */
 #define	DP_LINK_BW_SET		            0x100
 # define DP_LINK_RATE_TABLE		    0x00    /* eDP 1.4 */
-- 
2.29.0


^ permalink raw reply related	[flat|nested] 15+ messages in thread

* Re: [Intel-gfx] [PATCH v2 2/4] drm/i915/panelreplay: Initializaton and compute config for panel replay
  2021-10-07 15:57 ` [Intel-gfx] [PATCH v2 2/4] drm/i915/panelreplay: Initializaton and compute config " Animesh Manna
@ 2021-10-07 17:41   ` Jani Nikula
  2021-10-08  9:18     ` Manna, Animesh
  2021-10-07 17:41   ` Jani Nikula
  1 sibling, 1 reply; 15+ messages in thread
From: Jani Nikula @ 2021-10-07 17:41 UTC (permalink / raw)
  To: Animesh Manna, intel-gfx
  Cc: gwan-gyeong.mun, mika.kahola, manasi.d.navare, jose.souza, Animesh Manna

On Thu, 07 Oct 2021, Animesh Manna <animesh.manna@intel.com> wrote:
> As panel replay feature similar to PSR feature of EDP panel, so currently
> utilized existing psr framework for panel replay.
>
> v1: RFC version.
> v2: optimized code, pr_enabled and pr_dpcd variable removed. [Jose]
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  .../drm/i915/display/intel_display_types.h    |  2 +
>  drivers/gpu/drm/i915/display/intel_dp.c       | 47 +++++++++++++++----
>  drivers/gpu/drm/i915/display/intel_psr.c      | 43 +++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_psr.h      |  3 ++
>  include/drm/drm_dp_helper.h                   |  3 ++
>  5 files changed, 89 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 21ce8bccc645..b32d9529feef 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1070,6 +1070,7 @@ struct intel_crtc_state {
>  	bool req_psr2_sdp_prior_scanline;
>  	u32 dc3co_exitline;
>  	u16 su_y_granularity;
> +	bool has_panel_replay;
>  	struct drm_dp_vsc_sdp psr_vsc;
>  
>  	/*
> @@ -1531,6 +1532,7 @@ struct intel_psr {
>  	bool irq_aux_error;
>  	u16 su_w_granularity;
>  	u16 su_y_granularity;
> +	bool sink_pr_support;
>  	u32 dc3co_exitline;
>  	u32 dc3co_exit_delay;
>  	struct delayed_work dc3co_work;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 74a657ae131a..45181692e3b0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1569,12 +1569,22 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  
> -	/*
> -	 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> -	 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> -	 * Colorimetry Format indication.
> -	 */
> -	vsc->revision = 0x5;
> +	if (crtc_state->has_panel_replay) {
> +		/*
> +		 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
> +		 * VSC SDP supporting 3D stereo, Panel Replay, and Pixel
> +		 * Encoding/Colorimetry Format indication.
> +		 */
> +		vsc->revision = 0x7;
> +	} else {
> +		/*
> +		 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> +		 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> +		 * Colorimetry Format indication.
> +		 */
> +		vsc->revision = 0x5;
> +	}
> +
>  	vsc->length = 0x13;
>  
>  	/* DP 1.4a spec, Table 2-120 */
> @@ -1683,6 +1693,22 @@ void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
>  			vsc->revision = 0x4;
>  			vsc->length = 0xe;
>  		}
> +	} else if (intel_dp->psr.enabled && !intel_dp_is_edp(intel_dp)) {
> +		if (intel_dp->psr.colorimetry_support &&
> +		    intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> +			/* [PR, +Colorimetry] */
> +			intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
> +							 vsc);
> +		} else {
> +			/*
> +			 * [PR, -Colorimetry]

I don't understand the comment format here and above. Plain English,
please.

> +			 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
> +			 * VSC SDP supporting 3D stereo + PR (applies to eDP v1.3 or
> +			 * higher).
> +			 */
> +			vsc->revision = 0x6;
> +			vsc->length = 0x10;
> +		}
>  	} else {
>  		/*
>  		 * [PSR1]
> @@ -1824,6 +1850,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>  
>  	intel_vrr_compute_config(pipe_config, conn_state);
>  	intel_psr_compute_config(intel_dp, pipe_config, conn_state);
> +	intel_panel_replay_compute_config(intel_dp, pipe_config);

Are there any cases where we'd actually need to keep
intel_psr_compute_config and intel_panel_replay_compute_config separate?
Could you just call intel_panel_replay_compute_config from within
intel_psr_compute_config to not clutter this?

>  	intel_drrs_compute_config(intel_dp, pipe_config, output_bpp,
>  				  constant_n);
>  	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
> @@ -2731,10 +2758,10 @@ static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
>  	sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
>  
>  	/*
> -	 * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
> -	 * per DP 1.4a spec.
> +	 * Revision 0x5 and 0x7 supports Pixel Encoding/Colorimetry Format as
> +	 * per DP 1.4a spec and DP 2.0 spec respectively.
>  	 */
> -	if (vsc->revision != 0x5)
> +	if (vsc->revision != 0x5 || vsc->revision != 0x7)
>  		goto out;
>  
>  	/* VSC SDP Payload for DB16 through DB18 */
> @@ -5044,6 +5071,8 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
>  
>  	intel_psr_init(intel_dp);
>  
> +	intel_panel_replay_init(intel_dp);
> +

Ditto here, why not just call intel_panel_replay_init in intel_psr_init?

>  	return true;
>  
>  fail:
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 7a205fd5023b..935ea1c434ac 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -933,6 +933,21 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
>  	return true;
>  }
>  
> +void intel_panel_replay_compute_config(struct intel_dp *intel_dp,
> +				       struct intel_crtc_state *crtc_state)
> +{
> +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);

Please use i915 local variable name instead of dev_priv whenever
possible for new code.

> +
> +	if (!intel_dp->psr.sink_pr_support)
> +		return;
> +
> +	crtc_state->has_panel_replay = true;
> +	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
> +
> +	if (HAS_PSR2_SEL_FETCH(dev_priv))
> +		intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state);
> +}
> +
>  void intel_psr_compute_config(struct intel_dp *intel_dp,
>  			      struct intel_crtc_state *crtc_state,
>  			      struct drm_connector_state *conn_state)
> @@ -2170,6 +2185,34 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
>  	}
>  }
>  
> +/**
> + * intel_panel_replay_init - Check for sink and source capability.
> + * @intel_dp: Intel DP
> + *
> + * This function is called after the initializing connector.
> + * (the initializing of connector treats the handling of connector capabilities)
> + * And it initializes basic panel replay stuff for each DP Encoder.
> + */
> +void intel_panel_replay_init(struct intel_dp *intel_dp)
> +{
> +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +	u8 pr_dpcd;
> +
> +	if (!(HAS_DP20(dev_priv) && HAS_PR(dev_priv)))
> +		return;
> +
> +	drm_dp_dpcd_read(&intel_dp->aux, DP_PANEL_REPLAY_SUPPORT, &pr_dpcd,
> +			 sizeof(pr_dpcd));

drm_dp_dpcd_readb is for 1-byte reads.

If the read fails, pr_dpcd might be uninitialized. Either initialize
pr_dpcd = 0 or check the return value.

> +
> +	if (!(pr_dpcd & PANEL_REPLAY_SUPPORT)) {
> +		drm_dbg_kms(&dev_priv->drm,
> +			    "Panel replay is not supported by panel\n");

So I'd rather see debug log when panel replay *is* supported.

Or both is and isn't supported.

But really not this asymmetric not supported alone.

> +		return;
> +	}
> +
> +	intel_dp->psr.sink_pr_support = true;
> +}
> +
>  /**
>   * intel_psr_init - Init basic PSR work and mutex.
>   * @intel_dp: Intel DP
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
> index facffbacd357..c9d1c1f0b470 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -32,6 +32,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
>  		     unsigned frontbuffer_bits,
>  		     enum fb_op_origin origin);
>  void intel_psr_init(struct intel_dp *intel_dp);
> +void intel_panel_replay_init(struct intel_dp *intel_dp);
>  void intel_psr_compute_config(struct intel_dp *intel_dp,
>  			      struct intel_crtc_state *crtc_state,
>  			      struct drm_connector_state *conn_state);
> @@ -52,5 +53,7 @@ void intel_psr2_disable_plane_sel_fetch(struct intel_plane *plane,
>  					const struct intel_crtc_state *crtc_state);
>  void intel_psr_pause(struct intel_dp *intel_dp);
>  void intel_psr_resume(struct intel_dp *intel_dp);
> +void intel_panel_replay_compute_config(struct intel_dp *intel_dp,
> +				       struct intel_crtc_state *crtc_state);
>  
>  #endif /* __INTEL_PSR_H__ */
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index b52df4db3e8f..d18340cbf8ac 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -541,6 +541,9 @@ struct drm_panel;
>  /* DFP Capability Extension */
>  #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT	0x0a3	/* 2.0 */
>  
> +#define DP_PANEL_REPLAY_SUPPORT             0x0b0
> +# define PANEL_REPLAY_SUPPORT               (1 << 0)
> +

Often easier and better to split out drm helper changes to separate
patches for all kinds of reasons.

BR,
Jani.

>  /* Link Configuration */
>  #define	DP_LINK_BW_SET		            0x100
>  # define DP_LINK_RATE_TABLE		    0x00    /* eDP 1.4 */

-- 
Jani Nikula, Intel Open Source Graphics Center

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [Intel-gfx] [PATCH v2 2/4] drm/i915/panelreplay: Initializaton and compute config for panel replay
  2021-10-07 17:41   ` Jani Nikula
@ 2021-10-08  9:18     ` Manna, Animesh
  0 siblings, 0 replies; 15+ messages in thread
From: Manna, Animesh @ 2021-10-08  9:18 UTC (permalink / raw)
  To: Nikula, Jani, intel-gfx
  Cc: Mun, Gwan-gyeong, Kahola, Mika, Navare, Manasi D, Souza, Jose



> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Thursday, October 7, 2021 11:11 PM
> To: Manna, Animesh <animesh.manna@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Mun, Gwan-gyeong <gwan-gyeong.mun@intel.com>; Kahola, Mika
> <mika.kahola@intel.com>; Navare, Manasi D <manasi.d.navare@intel.com>;
> Souza, Jose <jose.souza@intel.com>; Manna, Animesh
> <animesh.manna@intel.com>
> Subject: Re: [PATCH v2 2/4] drm/i915/panelreplay: Initializaton and compute
> config for panel replay
> 
> On Thu, 07 Oct 2021, Animesh Manna <animesh.manna@intel.com> wrote:
> > As panel replay feature similar to PSR feature of EDP panel, so
> > currently utilized existing psr framework for panel replay.
> >
> > v1: RFC version.
> > v2: optimized code, pr_enabled and pr_dpcd variable removed. [Jose]
> >
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> >  .../drm/i915/display/intel_display_types.h    |  2 +
> >  drivers/gpu/drm/i915/display/intel_dp.c       | 47 +++++++++++++++----
> >  drivers/gpu/drm/i915/display/intel_psr.c      | 43 +++++++++++++++++
> >  drivers/gpu/drm/i915/display/intel_psr.h      |  3 ++
> >  include/drm/drm_dp_helper.h                   |  3 ++
> >  5 files changed, 89 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 21ce8bccc645..b32d9529feef 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1070,6 +1070,7 @@ struct intel_crtc_state {
> >  	bool req_psr2_sdp_prior_scanline;
> >  	u32 dc3co_exitline;
> >  	u16 su_y_granularity;
> > +	bool has_panel_replay;
> >  	struct drm_dp_vsc_sdp psr_vsc;
> >
> >  	/*
> > @@ -1531,6 +1532,7 @@ struct intel_psr {
> >  	bool irq_aux_error;
> >  	u16 su_w_granularity;
> >  	u16 su_y_granularity;
> > +	bool sink_pr_support;
> >  	u32 dc3co_exitline;
> >  	u32 dc3co_exit_delay;
> >  	struct delayed_work dc3co_work;
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 74a657ae131a..45181692e3b0 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -1569,12 +1569,22 @@ static void
> intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
> >  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >
> > -	/*
> > -	 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> > -	 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> > -	 * Colorimetry Format indication.
> > -	 */
> > -	vsc->revision = 0x5;
> > +	if (crtc_state->has_panel_replay) {
> > +		/*
> > +		 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
> > +		 * VSC SDP supporting 3D stereo, Panel Replay, and Pixel
> > +		 * Encoding/Colorimetry Format indication.
> > +		 */
> > +		vsc->revision = 0x7;
> > +	} else {
> > +		/*
> > +		 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> > +		 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> > +		 * Colorimetry Format indication.
> > +		 */
> > +		vsc->revision = 0x5;
> > +	}
> > +
> >  	vsc->length = 0x13;
> >
> >  	/* DP 1.4a spec, Table 2-120 */
> > @@ -1683,6 +1693,22 @@ void intel_dp_compute_psr_vsc_sdp(struct
> intel_dp *intel_dp,
> >  			vsc->revision = 0x4;
> >  			vsc->length = 0xe;
> >  		}
> > +	} else if (intel_dp->psr.enabled && !intel_dp_is_edp(intel_dp)) {
> > +		if (intel_dp->psr.colorimetry_support &&
> > +		    intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> > +			/* [PR, +Colorimetry] */
> > +			intel_dp_compute_vsc_colorimetry(crtc_state,
> conn_state,
> > +							 vsc);
> > +		} else {
> > +			/*
> > +			 * [PR, -Colorimetry]
> 
> I don't understand the comment format here and above. Plain English, please.

Thanks for review.
Sure, Will change it to "Panel Replay with colorimetry info" and "Panel replay without colorimetry info"
Earlier followed same format used by PSR2 ... 

> 
> > +			 * Prepare VSC Header for SU as per DP 2.0 spec, Table
> 2-223
> > +			 * VSC SDP supporting 3D stereo + PR (applies to eDP
> v1.3 or
> > +			 * higher).
> > +			 */
> > +			vsc->revision = 0x6;
> > +			vsc->length = 0x10;
> > +		}
> >  	} else {
> >  		/*
> >  		 * [PSR1]
> > @@ -1824,6 +1850,7 @@ intel_dp_compute_config(struct intel_encoder
> > *encoder,
> >
> >  	intel_vrr_compute_config(pipe_config, conn_state);
> >  	intel_psr_compute_config(intel_dp, pipe_config, conn_state);
> > +	intel_panel_replay_compute_config(intel_dp, pipe_config);
> 
> Are there any cases where we'd actually need to keep intel_psr_compute_config
> and intel_panel_replay_compute_config separate?
> Could you just call intel_panel_replay_compute_config from within
> intel_psr_compute_config to not clutter this?

Ok .. moved intel_panel_replay_compute_config() inside intel_psr_compute_config().

> 
> >  	intel_drrs_compute_config(intel_dp, pipe_config, output_bpp,
> >  				  constant_n);
> >  	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state); @@
> > -2731,10 +2758,10 @@ static ssize_t intel_dp_vsc_sdp_pack(const struct
> drm_dp_vsc_sdp *vsc,
> >  	sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
> >
> >  	/*
> > -	 * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
> > -	 * per DP 1.4a spec.
> > +	 * Revision 0x5 and 0x7 supports Pixel Encoding/Colorimetry Format as
> > +	 * per DP 1.4a spec and DP 2.0 spec respectively.
> >  	 */
> > -	if (vsc->revision != 0x5)
> > +	if (vsc->revision != 0x5 || vsc->revision != 0x7)
> >  		goto out;
> >
> >  	/* VSC SDP Payload for DB16 through DB18 */ @@ -5044,6 +5071,8
> @@
> > intel_dp_init_connector(struct intel_digital_port *dig_port,
> >
> >  	intel_psr_init(intel_dp);
> >
> > +	intel_panel_replay_init(intel_dp);
> > +
> 
> Ditto here, why not just call intel_panel_replay_init in intel_psr_init?

Ok, moved intel_panel_replay_init() inside intel_psr_init().

> 
> >  	return true;
> >
> >  fail:
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 7a205fd5023b..935ea1c434ac 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -933,6 +933,21 @@ static bool intel_psr2_config_valid(struct intel_dp
> *intel_dp,
> >  	return true;
> >  }
> >
> > +void intel_panel_replay_compute_config(struct intel_dp *intel_dp,
> > +				       struct intel_crtc_state *crtc_state) {
> > +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> 
> Please use i915 local variable name instead of dev_priv whenever possible for
> new code.

Ok.

> 
> > +
> > +	if (!intel_dp->psr.sink_pr_support)
> > +		return;
> > +
> > +	crtc_state->has_panel_replay = true;
> > +	crtc_state->infoframes.enable |=
> > +intel_hdmi_infoframe_enable(DP_SDP_VSC);
> > +
> > +	if (HAS_PSR2_SEL_FETCH(dev_priv))
> > +		intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state); }
> > +
> >  void intel_psr_compute_config(struct intel_dp *intel_dp,
> >  			      struct intel_crtc_state *crtc_state,
> >  			      struct drm_connector_state *conn_state) @@ -
> 2170,6 +2185,34
> > @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
> >  	}
> >  }
> >
> > +/**
> > + * intel_panel_replay_init - Check for sink and source capability.
> > + * @intel_dp: Intel DP
> > + *
> > + * This function is called after the initializing connector.
> > + * (the initializing of connector treats the handling of connector
> > +capabilities)
> > + * And it initializes basic panel replay stuff for each DP Encoder.
> > + */
> > +void intel_panel_replay_init(struct intel_dp *intel_dp) {
> > +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > +	u8 pr_dpcd;
> > +
> > +	if (!(HAS_DP20(dev_priv) && HAS_PR(dev_priv)))
> > +		return;
> > +
> > +	drm_dp_dpcd_read(&intel_dp->aux, DP_PANEL_REPLAY_SUPPORT,
> &pr_dpcd,
> > +			 sizeof(pr_dpcd));
> 
> drm_dp_dpcd_readb is for 1-byte reads.
> 
> If the read fails, pr_dpcd might be uninitialized. Either initialize pr_dpcd = 0 or
> check the return value.

Ok.

> 
> > +
> > +	if (!(pr_dpcd & PANEL_REPLAY_SUPPORT)) {
> > +		drm_dbg_kms(&dev_priv->drm,
> > +			    "Panel replay is not supported by panel\n");
> 
> So I'd rather see debug log when panel replay *is* supported.
> 
> Or both is and isn't supported.
> 
> But really not this asymmetric not supported alone.

Ok, have added print for both.

> 
> > +		return;
> > +	}
> > +
> > +	intel_dp->psr.sink_pr_support = true; }
> > +
> >  /**
> >   * intel_psr_init - Init basic PSR work and mutex.
> >   * @intel_dp: Intel DP
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> > b/drivers/gpu/drm/i915/display/intel_psr.h
> > index facffbacd357..c9d1c1f0b470 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.h
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> > @@ -32,6 +32,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
> >  		     unsigned frontbuffer_bits,
> >  		     enum fb_op_origin origin);
> >  void intel_psr_init(struct intel_dp *intel_dp);
> > +void intel_panel_replay_init(struct intel_dp *intel_dp);
> >  void intel_psr_compute_config(struct intel_dp *intel_dp,
> >  			      struct intel_crtc_state *crtc_state,
> >  			      struct drm_connector_state *conn_state); @@ -
> 52,5 +53,7 @@
> > void intel_psr2_disable_plane_sel_fetch(struct intel_plane *plane,
> >  					const struct intel_crtc_state
> *crtc_state);  void
> > intel_psr_pause(struct intel_dp *intel_dp);  void
> > intel_psr_resume(struct intel_dp *intel_dp);
> > +void intel_panel_replay_compute_config(struct intel_dp *intel_dp,
> > +				       struct intel_crtc_state *crtc_state);
> >
> >  #endif /* __INTEL_PSR_H__ */
> > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> > index b52df4db3e8f..d18340cbf8ac 100644
> > --- a/include/drm/drm_dp_helper.h
> > +++ b/include/drm/drm_dp_helper.h
> > @@ -541,6 +541,9 @@ struct drm_panel;
> >  /* DFP Capability Extension */
> >  #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT	0x0a3	/* 2.0 */
> >
> > +#define DP_PANEL_REPLAY_SUPPORT             0x0b0
> > +# define PANEL_REPLAY_SUPPORT               (1 << 0)
> > +
> 
> Often easier and better to split out drm helper changes to separate patches for
> all kinds of reasons.

Ok.

Regards,
Animesh
> 
> BR,
> Jani.
> 
> >  /* Link Configuration */
> >  #define	DP_LINK_BW_SET		            0x100
> >  # define DP_LINK_RATE_TABLE		    0x00    /* eDP 1.4 */
> 
> --
> Jani Nikula, Intel Open Source Graphics Center

^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [Intel-gfx] [PATCH v2 2/4] drm/i915/panelreplay: Initializaton and compute config for panel replay
  2021-10-07 15:57 ` [Intel-gfx] [PATCH v2 2/4] drm/i915/panelreplay: Initializaton and compute config " Animesh Manna
  2021-10-07 17:41   ` Jani Nikula
@ 2021-10-07 17:41   ` Jani Nikula
  1 sibling, 0 replies; 15+ messages in thread
From: Jani Nikula @ 2021-10-07 17:41 UTC (permalink / raw)
  To: Animesh Manna, intel-gfx
  Cc: gwan-gyeong.mun, mika.kahola, manasi.d.navare, jose.souza, Animesh Manna

On Thu, 07 Oct 2021, Animesh Manna <animesh.manna@intel.com> wrote:
> As panel replay feature similar to PSR feature of EDP panel, so currently
> utilized existing psr framework for panel replay.
>
> v1: RFC version.
> v2: optimized code, pr_enabled and pr_dpcd variable removed. [Jose]
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  .../drm/i915/display/intel_display_types.h    |  2 +
>  drivers/gpu/drm/i915/display/intel_dp.c       | 47 +++++++++++++++----
>  drivers/gpu/drm/i915/display/intel_psr.c      | 43 +++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_psr.h      |  3 ++
>  include/drm/drm_dp_helper.h                   |  3 ++
>  5 files changed, 89 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 21ce8bccc645..b32d9529feef 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1070,6 +1070,7 @@ struct intel_crtc_state {
>  	bool req_psr2_sdp_prior_scanline;
>  	u32 dc3co_exitline;
>  	u16 su_y_granularity;
> +	bool has_panel_replay;
>  	struct drm_dp_vsc_sdp psr_vsc;
>  
>  	/*
> @@ -1531,6 +1532,7 @@ struct intel_psr {
>  	bool irq_aux_error;
>  	u16 su_w_granularity;
>  	u16 su_y_granularity;
> +	bool sink_pr_support;

Maybe spell out panel_replay here too, pr is just too short IMO.

>  	u32 dc3co_exitline;
>  	u32 dc3co_exit_delay;
>  	struct delayed_work dc3co_work;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 74a657ae131a..45181692e3b0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1569,12 +1569,22 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  
> -	/*
> -	 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> -	 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> -	 * Colorimetry Format indication.
> -	 */
> -	vsc->revision = 0x5;
> +	if (crtc_state->has_panel_replay) {
> +		/*
> +		 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
> +		 * VSC SDP supporting 3D stereo, Panel Replay, and Pixel
> +		 * Encoding/Colorimetry Format indication.
> +		 */
> +		vsc->revision = 0x7;
> +	} else {
> +		/*
> +		 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> +		 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> +		 * Colorimetry Format indication.
> +		 */
> +		vsc->revision = 0x5;
> +	}
> +
>  	vsc->length = 0x13;
>  
>  	/* DP 1.4a spec, Table 2-120 */
> @@ -1683,6 +1693,22 @@ void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
>  			vsc->revision = 0x4;
>  			vsc->length = 0xe;
>  		}
> +	} else if (intel_dp->psr.enabled && !intel_dp_is_edp(intel_dp)) {
> +		if (intel_dp->psr.colorimetry_support &&
> +		    intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> +			/* [PR, +Colorimetry] */
> +			intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
> +							 vsc);
> +		} else {
> +			/*
> +			 * [PR, -Colorimetry]
> +			 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
> +			 * VSC SDP supporting 3D stereo + PR (applies to eDP v1.3 or
> +			 * higher).
> +			 */
> +			vsc->revision = 0x6;
> +			vsc->length = 0x10;
> +		}
>  	} else {
>  		/*
>  		 * [PSR1]
> @@ -1824,6 +1850,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
>  
>  	intel_vrr_compute_config(pipe_config, conn_state);
>  	intel_psr_compute_config(intel_dp, pipe_config, conn_state);
> +	intel_panel_replay_compute_config(intel_dp, pipe_config);
>  	intel_drrs_compute_config(intel_dp, pipe_config, output_bpp,
>  				  constant_n);
>  	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
> @@ -2731,10 +2758,10 @@ static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
>  	sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
>  
>  	/*
> -	 * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
> -	 * per DP 1.4a spec.
> +	 * Revision 0x5 and 0x7 supports Pixel Encoding/Colorimetry Format as
> +	 * per DP 1.4a spec and DP 2.0 spec respectively.
>  	 */
> -	if (vsc->revision != 0x5)
> +	if (vsc->revision != 0x5 || vsc->revision != 0x7)
>  		goto out;
>  
>  	/* VSC SDP Payload for DB16 through DB18 */
> @@ -5044,6 +5071,8 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
>  
>  	intel_psr_init(intel_dp);
>  
> +	intel_panel_replay_init(intel_dp);
> +
>  	return true;
>  
>  fail:
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 7a205fd5023b..935ea1c434ac 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -933,6 +933,21 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
>  	return true;
>  }
>  
> +void intel_panel_replay_compute_config(struct intel_dp *intel_dp,
> +				       struct intel_crtc_state *crtc_state)
> +{
> +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> +	if (!intel_dp->psr.sink_pr_support)
> +		return;
> +
> +	crtc_state->has_panel_replay = true;
> +	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
> +
> +	if (HAS_PSR2_SEL_FETCH(dev_priv))
> +		intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state);
> +}
> +
>  void intel_psr_compute_config(struct intel_dp *intel_dp,
>  			      struct intel_crtc_state *crtc_state,
>  			      struct drm_connector_state *conn_state)
> @@ -2170,6 +2185,34 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
>  	}
>  }
>  
> +/**
> + * intel_panel_replay_init - Check for sink and source capability.
> + * @intel_dp: Intel DP
> + *
> + * This function is called after the initializing connector.
> + * (the initializing of connector treats the handling of connector capabilities)
> + * And it initializes basic panel replay stuff for each DP Encoder.
> + */
> +void intel_panel_replay_init(struct intel_dp *intel_dp)
> +{
> +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +	u8 pr_dpcd;
> +
> +	if (!(HAS_DP20(dev_priv) && HAS_PR(dev_priv)))
> +		return;
> +
> +	drm_dp_dpcd_read(&intel_dp->aux, DP_PANEL_REPLAY_SUPPORT, &pr_dpcd,
> +			 sizeof(pr_dpcd));
> +
> +	if (!(pr_dpcd & PANEL_REPLAY_SUPPORT)) {
> +		drm_dbg_kms(&dev_priv->drm,
> +			    "Panel replay is not supported by panel\n");
> +		return;
> +	}
> +
> +	intel_dp->psr.sink_pr_support = true;
> +}
> +
>  /**
>   * intel_psr_init - Init basic PSR work and mutex.
>   * @intel_dp: Intel DP
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
> index facffbacd357..c9d1c1f0b470 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -32,6 +32,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
>  		     unsigned frontbuffer_bits,
>  		     enum fb_op_origin origin);
>  void intel_psr_init(struct intel_dp *intel_dp);
> +void intel_panel_replay_init(struct intel_dp *intel_dp);
>  void intel_psr_compute_config(struct intel_dp *intel_dp,
>  			      struct intel_crtc_state *crtc_state,
>  			      struct drm_connector_state *conn_state);
> @@ -52,5 +53,7 @@ void intel_psr2_disable_plane_sel_fetch(struct intel_plane *plane,
>  					const struct intel_crtc_state *crtc_state);
>  void intel_psr_pause(struct intel_dp *intel_dp);
>  void intel_psr_resume(struct intel_dp *intel_dp);
> +void intel_panel_replay_compute_config(struct intel_dp *intel_dp,
> +				       struct intel_crtc_state *crtc_state);
>  
>  #endif /* __INTEL_PSR_H__ */
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index b52df4db3e8f..d18340cbf8ac 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -541,6 +541,9 @@ struct drm_panel;
>  /* DFP Capability Extension */
>  #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT	0x0a3	/* 2.0 */
>  
> +#define DP_PANEL_REPLAY_SUPPORT             0x0b0
> +# define PANEL_REPLAY_SUPPORT               (1 << 0)
> +
>  /* Link Configuration */
>  #define	DP_LINK_BW_SET		            0x100
>  # define DP_LINK_RATE_TABLE		    0x00    /* eDP 1.4 */

-- 
Jani Nikula, Intel Open Source Graphics Center

^ permalink raw reply	[flat|nested] 15+ messages in thread

* [Intel-gfx] [PATCH v2 3/4] drm/i915/panelreplay: enable/disable panel replay
  2021-10-07 15:57 [Intel-gfx] [PATCH v2 0/4] Panel replay phase1 implementation Animesh Manna
  2021-10-07 15:57 ` [Intel-gfx] [PATCH v2 1/4] drm/i915/panelreplay: HAS_PR() macro added for panel replay Animesh Manna
  2021-10-07 15:57 ` [Intel-gfx] [PATCH v2 2/4] drm/i915/panelreplay: Initializaton and compute config " Animesh Manna
@ 2021-10-07 15:57 ` Animesh Manna
  2021-10-07 17:44   ` Jani Nikula
  2021-10-07 15:57 ` [Intel-gfx] [PATCH v2 4/4] drm/i915/panelreplay: Added state checker for panel replay state Animesh Manna
                   ` (2 subsequent siblings)
  5 siblings, 1 reply; 15+ messages in thread
From: Animesh Manna @ 2021-10-07 15:57 UTC (permalink / raw)
  To: intel-gfx
  Cc: gwan-gyeong.mun, mika.kahola, jani.nikula, manasi.d.navare,
	jose.souza, Animesh Manna

TRANS_DP2_CTL register is programmed to enable panel replay from source
and sink is enabled through panel replay dpcd configuration address.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 30 ++++++++++++++++++++----
 drivers/gpu/drm/i915/i915_reg.h          |  1 +
 include/drm/drm_dp_helper.h              |  3 +++
 3 files changed, 30 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 935ea1c434ac..197cab7551c6 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -370,8 +370,14 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp)
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	u8 dpcd_val = DP_PSR_ENABLE;
 
-	/* Enable ALPM at sink for psr2 */
+	if (intel_dp->psr.enabled && !intel_dp_is_edp(intel_dp)) {
+		drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG,
+				   PANEL_REPLAY_ENABLE);
+		return;
+	}
+
 	if (intel_dp->psr.psr2_enabled) {
+		/* Enable ALPM at sink for psr2 */
 		drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
 				   DP_ALPM_ENABLE |
 				   DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
@@ -498,6 +504,17 @@ static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
 	return val;
 }
 
+static void dg2_activate_panel_replay(struct intel_dp *intel_dp)
+{
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+	intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
+		       ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE);
+
+	intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0,
+		     TRANS_DP2_PANEL_REPLAY_ENABLE);
+}
+
 static void hsw_activate_psr2(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -1067,8 +1084,10 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
 	drm_WARN_ON(&dev_priv->drm, intel_dp->psr.active);
 	lockdep_assert_held(&intel_dp->psr.lock);
 
-	/* psr1 and psr2 are mutually exclusive.*/
-	if (intel_dp->psr.psr2_enabled)
+	/* psr1, psr2 and panel-replay are mutually exclusive.*/
+	if (intel_dp->psr.enabled && !intel_dp_is_edp(intel_dp))
+		dg2_activate_panel_replay(intel_dp);
+	else if (intel_dp->psr.psr2_enabled)
 		hsw_activate_psr2(intel_dp);
 	else
 		hsw_activate_psr1(intel_dp);
@@ -1241,7 +1260,10 @@ static void intel_psr_exit(struct intel_dp *intel_dp)
 		return;
 	}
 
-	if (intel_dp->psr.psr2_enabled) {
+	if (intel_dp->psr.enabled && !intel_dp_is_edp(intel_dp)) {
+		intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder),
+			     TRANS_DP2_PANEL_REPLAY_ENABLE, 0);
+	} else if (intel_dp->psr.psr2_enabled) {
 		tgl_disallow_dc3co_on_psr2_exit(intel_dp);
 		val = intel_de_read(dev_priv,
 				    EDP_PSR2_CTL(intel_dp->psr.transcoder));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a897f4abea0c..6cc6ebcd3bdb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4725,6 +4725,7 @@ enum {
 #define  PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME			REG_BIT(3)
 #define  PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME		REG_BIT(2)
 #define  PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE		REG_BIT(1)
+#define  ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE		REG_BIT(31)
 #define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK	REG_GENMASK(28, 16)
 #define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val)	REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
 #define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK		REG_GENMASK(12, 0)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index d18340cbf8ac..4b95289e6edf 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -712,6 +712,9 @@ struct drm_panel;
 #define DP_BRANCH_DEVICE_CTRL		    0x1a1
 # define DP_BRANCH_DEVICE_IRQ_HPD	    (1 << 0)
 
+#define PANEL_REPLAY_CONFIG                 0x1b0
+# define PANEL_REPLAY_ENABLE                (1 << 0)
+
 #define DP_PAYLOAD_ALLOCATE_SET		    0x1c0
 #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
 #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
-- 
2.29.0


^ permalink raw reply related	[flat|nested] 15+ messages in thread

* Re: [Intel-gfx] [PATCH v2 3/4] drm/i915/panelreplay: enable/disable panel replay
  2021-10-07 15:57 ` [Intel-gfx] [PATCH v2 3/4] drm/i915/panelreplay: enable/disable " Animesh Manna
@ 2021-10-07 17:44   ` Jani Nikula
  0 siblings, 0 replies; 15+ messages in thread
From: Jani Nikula @ 2021-10-07 17:44 UTC (permalink / raw)
  To: Animesh Manna, intel-gfx
  Cc: gwan-gyeong.mun, mika.kahola, manasi.d.navare, jose.souza, Animesh Manna

On Thu, 07 Oct 2021, Animesh Manna <animesh.manna@intel.com> wrote:
> TRANS_DP2_CTL register is programmed to enable panel replay from source
> and sink is enabled through panel replay dpcd configuration address.
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 30 ++++++++++++++++++++----
>  drivers/gpu/drm/i915/i915_reg.h          |  1 +
>  include/drm/drm_dp_helper.h              |  3 +++
>  3 files changed, 30 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 935ea1c434ac..197cab7551c6 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -370,8 +370,14 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp)
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  	u8 dpcd_val = DP_PSR_ENABLE;
>  
> -	/* Enable ALPM at sink for psr2 */
> +	if (intel_dp->psr.enabled && !intel_dp_is_edp(intel_dp)) {
> +		drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG,
> +				   PANEL_REPLAY_ENABLE);
> +		return;
> +	}
> +
>  	if (intel_dp->psr.psr2_enabled) {
> +		/* Enable ALPM at sink for psr2 */
>  		drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
>  				   DP_ALPM_ENABLE |
>  				   DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
> @@ -498,6 +504,17 @@ static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
>  	return val;
>  }
>  
> +static void dg2_activate_panel_replay(struct intel_dp *intel_dp)
> +{
> +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +
> +	intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
> +		       ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE);
> +
> +	intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0,
> +		     TRANS_DP2_PANEL_REPLAY_ENABLE);
> +}
> +
>  static void hsw_activate_psr2(struct intel_dp *intel_dp)
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> @@ -1067,8 +1084,10 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
>  	drm_WARN_ON(&dev_priv->drm, intel_dp->psr.active);
>  	lockdep_assert_held(&intel_dp->psr.lock);
>  
> -	/* psr1 and psr2 are mutually exclusive.*/
> -	if (intel_dp->psr.psr2_enabled)
> +	/* psr1, psr2 and panel-replay are mutually exclusive.*/
> +	if (intel_dp->psr.enabled && !intel_dp_is_edp(intel_dp))
> +		dg2_activate_panel_replay(intel_dp);
> +	else if (intel_dp->psr.psr2_enabled)
>  		hsw_activate_psr2(intel_dp);
>  	else
>  		hsw_activate_psr1(intel_dp);
> @@ -1241,7 +1260,10 @@ static void intel_psr_exit(struct intel_dp *intel_dp)
>  		return;
>  	}
>  
> -	if (intel_dp->psr.psr2_enabled) {
> +	if (intel_dp->psr.enabled && !intel_dp_is_edp(intel_dp)) {
> +		intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder),
> +			     TRANS_DP2_PANEL_REPLAY_ENABLE, 0);
> +	} else if (intel_dp->psr.psr2_enabled) {
>  		tgl_disallow_dc3co_on_psr2_exit(intel_dp);
>  		val = intel_de_read(dev_priv,
>  				    EDP_PSR2_CTL(intel_dp->psr.transcoder));
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a897f4abea0c..6cc6ebcd3bdb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4725,6 +4725,7 @@ enum {
>  #define  PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME			REG_BIT(3)
>  #define  PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME		REG_BIT(2)
>  #define  PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE		REG_BIT(1)
> +#define  ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE		REG_BIT(31)
>  #define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK	REG_GENMASK(28, 16)
>  #define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val)	REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
>  #define  ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK		REG_GENMASK(12, 0)
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index d18340cbf8ac..4b95289e6edf 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -712,6 +712,9 @@ struct drm_panel;
>  #define DP_BRANCH_DEVICE_CTRL		    0x1a1
>  # define DP_BRANCH_DEVICE_IRQ_HPD	    (1 << 0)
>  
> +#define PANEL_REPLAY_CONFIG                 0x1b0
> +# define PANEL_REPLAY_ENABLE                (1 << 0)
> +

Previous patch has:

 +#define DP_PANEL_REPLAY_SUPPORT             0x0b0
 +# define PANEL_REPLAY_SUPPORT               (1 << 0)
 +

Also, it's called "PANEL REPLAY CAPABILITY SUPPORTED" in the spec, so
DP_PANEL_REPLAY_CAP or something sounds more like it.


>  #define DP_PAYLOAD_ALLOCATE_SET		    0x1c0
>  #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
>  #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2

-- 
Jani Nikula, Intel Open Source Graphics Center

^ permalink raw reply	[flat|nested] 15+ messages in thread

* [Intel-gfx] [PATCH v2 4/4] drm/i915/panelreplay: Added state checker for panel replay state
  2021-10-07 15:57 [Intel-gfx] [PATCH v2 0/4] Panel replay phase1 implementation Animesh Manna
                   ` (2 preceding siblings ...)
  2021-10-07 15:57 ` [Intel-gfx] [PATCH v2 3/4] drm/i915/panelreplay: enable/disable " Animesh Manna
@ 2021-10-07 15:57 ` Animesh Manna
  2021-10-07 17:52   ` Jani Nikula
  2021-10-07 16:47 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Panel replay phase1 implementation (rev2) Patchwork
  2021-10-07 17:13 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
  5 siblings, 1 reply; 15+ messages in thread
From: Animesh Manna @ 2021-10-07 15:57 UTC (permalink / raw)
  To: intel-gfx
  Cc: gwan-gyeong.mun, mika.kahola, jani.nikula, manasi.d.navare,
	jose.souza, Animesh Manna

has_panel_replay flag is used to check panel replay state
which is part of crtc_state structure.

Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 1 +
 drivers/gpu/drm/i915/display/intel_psr.c     | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 4f0badb11bbb..a30b6fe87dfc 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8136,6 +8136,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 			PIPE_CONF_CHECK_BOOL(has_psr);
 			PIPE_CONF_CHECK_BOOL(has_psr2);
 			PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
+			PIPE_CONF_CHECK_BOOL(has_panel_replay);
 			PIPE_CONF_CHECK_I(dc3co_exitline);
 		}
 	}
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 197cab7551c6..756f3c775e71 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1050,6 +1050,8 @@ void intel_psr_get_config(struct intel_encoder *encoder,
 	 */
 	pipe_config->has_psr = true;
 	pipe_config->has_psr2 = intel_dp->psr.psr2_enabled;
+	pipe_config->has_panel_replay = intel_dp->psr.enabled &&
+					intel_dp_is_edp(intel_dp);
 	pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
 
 	if (!intel_dp->psr.psr2_enabled)
-- 
2.29.0


^ permalink raw reply related	[flat|nested] 15+ messages in thread

* Re: [Intel-gfx] [PATCH v2 4/4] drm/i915/panelreplay: Added state checker for panel replay state
  2021-10-07 15:57 ` [Intel-gfx] [PATCH v2 4/4] drm/i915/panelreplay: Added state checker for panel replay state Animesh Manna
@ 2021-10-07 17:52   ` Jani Nikula
  0 siblings, 0 replies; 15+ messages in thread
From: Jani Nikula @ 2021-10-07 17:52 UTC (permalink / raw)
  To: Animesh Manna, intel-gfx
  Cc: gwan-gyeong.mun, mika.kahola, manasi.d.navare, jose.souza, Animesh Manna

On Thu, 07 Oct 2021, Animesh Manna <animesh.manna@intel.com> wrote:
> has_panel_replay flag is used to check panel replay state
> which is part of crtc_state structure.
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 1 +
>  drivers/gpu/drm/i915/display/intel_psr.c     | 2 ++
>  2 files changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 4f0badb11bbb..a30b6fe87dfc 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -8136,6 +8136,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  			PIPE_CONF_CHECK_BOOL(has_psr);
>  			PIPE_CONF_CHECK_BOOL(has_psr2);
>  			PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
> +			PIPE_CONF_CHECK_BOOL(has_panel_replay);
>  			PIPE_CONF_CHECK_I(dc3co_exitline);
>  		}
>  	}
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 197cab7551c6..756f3c775e71 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1050,6 +1050,8 @@ void intel_psr_get_config(struct intel_encoder *encoder,
>  	 */
>  	pipe_config->has_psr = true;
>  	pipe_config->has_psr2 = intel_dp->psr.psr2_enabled;
> +	pipe_config->has_panel_replay = intel_dp->psr.enabled &&
> +					intel_dp_is_edp(intel_dp);

Get config is supposed to read the config from hardware, and then the
state checker compares sw and hw states. This seems off.

BR,
Jani.

>  	pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
>  
>  	if (!intel_dp->psr.psr2_enabled)

-- 
Jani Nikula, Intel Open Source Graphics Center

^ permalink raw reply	[flat|nested] 15+ messages in thread

* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Panel replay phase1 implementation (rev2)
  2021-10-07 15:57 [Intel-gfx] [PATCH v2 0/4] Panel replay phase1 implementation Animesh Manna
                   ` (3 preceding siblings ...)
  2021-10-07 15:57 ` [Intel-gfx] [PATCH v2 4/4] drm/i915/panelreplay: Added state checker for panel replay state Animesh Manna
@ 2021-10-07 16:47 ` Patchwork
  2021-10-07 17:13 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
  5 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2021-10-07 16:47 UTC (permalink / raw)
  To: Animesh Manna; +Cc: intel-gfx

== Series Details ==

Series: Panel replay phase1 implementation (rev2)
URL   : https://patchwork.freedesktop.org/series/94470/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
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+ 
+ 
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT  0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #def



^ permalink raw reply	[flat|nested] 15+ messages in thread

* [Intel-gfx] ✗ Fi.CI.BAT: failure for Panel replay phase1 implementation (rev2)
  2021-10-07 15:57 [Intel-gfx] [PATCH v2 0/4] Panel replay phase1 implementation Animesh Manna
                   ` (4 preceding siblings ...)
  2021-10-07 16:47 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Panel replay phase1 implementation (rev2) Patchwork
@ 2021-10-07 17:13 ` Patchwork
  5 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2021-10-07 17:13 UTC (permalink / raw)
  To: Manna, Animesh; +Cc: intel-gfx

[-- Attachment #1: Type: text/plain, Size: 5975 bytes --]

== Series Details ==

Series: Panel replay phase1 implementation (rev2)
URL   : https://patchwork.freedesktop.org/series/94470/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_10695 -> Patchwork_21280
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_21280 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_21280, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21280/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_21280:

### IGT changes ###

#### Possible regressions ####

  * igt@debugfs_test@read_all_entries:
    - fi-icl-u2:          [PASS][1] -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10695/fi-icl-u2/igt@debugfs_test@read_all_entries.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21280/fi-icl-u2/igt@debugfs_test@read_all_entries.html

  * igt@runner@aborted:
    - fi-tgl-u2:          NOTRUN -> [FAIL][3]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21280/fi-tgl-u2/igt@runner@aborted.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@runner@aborted:
    - {fi-jsl-1}:         NOTRUN -> [FAIL][4]
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21280/fi-jsl-1/igt@runner@aborted.html
    - {fi-ehl-2}:         NOTRUN -> [FAIL][5]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21280/fi-ehl-2/igt@runner@aborted.html

  
Known issues
------------

  Here are the changes found in Patchwork_21280 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@debugfs_test@read_all_entries:
    - fi-kbl-r:           [PASS][6] -> [DMESG-WARN][7] ([i915#262])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10695/fi-kbl-r/igt@debugfs_test@read_all_entries.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21280/fi-kbl-r/igt@debugfs_test@read_all_entries.html

  * igt@i915_selftest@live@execlists:
    - fi-bsw-nick:        [PASS][8] -> [INCOMPLETE][9] ([i915#2940])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10695/fi-bsw-nick/igt@i915_selftest@live@execlists.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21280/fi-bsw-nick/igt@i915_selftest@live@execlists.html

  * igt@runner@aborted:
    - fi-skl-6600u:       NOTRUN -> [FAIL][10] ([i915#3363])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21280/fi-skl-6600u/igt@runner@aborted.html
    - fi-icl-u2:          NOTRUN -> [FAIL][11] ([i915#1814] / [i915#3363])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21280/fi-icl-u2/igt@runner@aborted.html
    - fi-bsw-nick:        NOTRUN -> [FAIL][12] ([fdo#109271] / [i915#1436] / [i915#3428])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21280/fi-bsw-nick/igt@runner@aborted.html
    - fi-kbl-r:           NOTRUN -> [FAIL][13] ([i915#1814] / [i915#3363])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21280/fi-kbl-r/igt@runner@aborted.html
    - fi-bdw-5557u:       NOTRUN -> [FAIL][14] ([i915#1602] / [i915#2029])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21280/fi-bdw-5557u/igt@runner@aborted.html
    - fi-kbl-soraka:      NOTRUN -> [FAIL][15] ([i915#1569] / [i915#192] / [i915#193] / [i915#194] / [i915#3363])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21280/fi-kbl-soraka/igt@runner@aborted.html
    - fi-cml-u2:          NOTRUN -> [FAIL][16] ([i915#3363])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21280/fi-cml-u2/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569
  [i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
  [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814
  [i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192
  [i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193
  [i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194
  [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
  [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
  [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
  [i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
  [i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428


Participating hosts (44 -> 37)
------------------------------

  Missing    (7): fi-ilk-m540 bat-dg1-6 fi-hsw-4200u fi-tgl-1115g4 fi-bsw-cyan fi-ctg-p8600 bat-jsl-1 


Build changes
-------------

  * Linux: CI_DRM_10695 -> Patchwork_21280

  CI-20190529: 20190529
  CI_DRM_10695: aca2978a75f0c9c55d0d5c1f98ecd659d3e6cee9 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6235: 65dd7d484d5d09de196def254afebf41dfde1052 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_21280: f2df1988637134c898cf6b553820a61a784ecfdf @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

f2df19886371 drm/i915/panelreplay: Added state checker for panel replay state
f333185d8137 drm/i915/panelreplay: enable/disable panel replay
023c444261e9 drm/i915/panelreplay: Initializaton and compute config for panel replay
5ffd348d0e67 drm/i915/panelreplay: HAS_PR() macro added for panel replay

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21280/index.html

[-- Attachment #2: Type: text/html, Size: 7203 bytes --]

^ permalink raw reply	[flat|nested] 15+ messages in thread

end of thread, other threads:[~2021-10-08  9:18 UTC | newest]

Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-10-07 15:57 [Intel-gfx] [PATCH v2 0/4] Panel replay phase1 implementation Animesh Manna
2021-10-07 15:57 ` [Intel-gfx] [PATCH v2 1/4] drm/i915/panelreplay: HAS_PR() macro added for panel replay Animesh Manna
2021-10-07 16:39   ` Ville Syrjälä
2021-10-07 16:56     ` Manna, Animesh
2021-10-07 16:59     ` Jani Nikula
2021-10-07 15:57 ` [Intel-gfx] [PATCH v2 2/4] drm/i915/panelreplay: Initializaton and compute config " Animesh Manna
2021-10-07 17:41   ` Jani Nikula
2021-10-08  9:18     ` Manna, Animesh
2021-10-07 17:41   ` Jani Nikula
2021-10-07 15:57 ` [Intel-gfx] [PATCH v2 3/4] drm/i915/panelreplay: enable/disable " Animesh Manna
2021-10-07 17:44   ` Jani Nikula
2021-10-07 15:57 ` [Intel-gfx] [PATCH v2 4/4] drm/i915/panelreplay: Added state checker for panel replay state Animesh Manna
2021-10-07 17:52   ` Jani Nikula
2021-10-07 16:47 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Panel replay phase1 implementation (rev2) Patchwork
2021-10-07 17:13 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork

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