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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: alistair.francis@wdc.com, frederic.petrot@univ-grenoble-alpes.fr,
	qemu-riscv@nongnu.org, fabien.portas@grenoble-inp.org
Subject: [PATCH 11/13] target/riscv: Adjust trans_rev8_32 for riscv64
Date: Thu,  7 Oct 2021 10:47:20 -0700	[thread overview]
Message-ID: <20211007174722.929993-12-richard.henderson@linaro.org> (raw)
In-Reply-To: <20211007174722.929993-1-richard.henderson@linaro.org>

When target_long is 64-bit, we still want a 32-bit bswap for rev8.
Since this opcode is specific to RV32, we need not conditionalize.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/insn_trans/trans_rvb.c.inc | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 66dd51de49..c62eea433a 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -232,11 +232,16 @@ static bool trans_rol(DisasContext *ctx, arg_rol *a)
     return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
 }
 
+static void gen_rev8_32(TCGv ret, TCGv src1)
+{
+    tcg_gen_bswap32_tl(ret, src1, TCG_BSWAP_OS);
+}
+
 static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
 {
     REQUIRE_32BIT(ctx);
     REQUIRE_ZBB(ctx);
-    return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
+    return gen_unary(ctx, a, EXT_NONE, gen_rev8_32);
 }
 
 static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
-- 
2.25.1



WARNING: multiple messages have this Message-ID (diff)
From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
	frederic.petrot@univ-grenoble-alpes.fr,
	fabien.portas@grenoble-inp.org
Subject: [PATCH 11/13] target/riscv: Adjust trans_rev8_32 for riscv64
Date: Thu,  7 Oct 2021 10:47:20 -0700	[thread overview]
Message-ID: <20211007174722.929993-12-richard.henderson@linaro.org> (raw)
In-Reply-To: <20211007174722.929993-1-richard.henderson@linaro.org>

When target_long is 64-bit, we still want a 32-bit bswap for rev8.
Since this opcode is specific to RV32, we need not conditionalize.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/insn_trans/trans_rvb.c.inc | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index 66dd51de49..c62eea433a 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -232,11 +232,16 @@ static bool trans_rol(DisasContext *ctx, arg_rol *a)
     return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
 }
 
+static void gen_rev8_32(TCGv ret, TCGv src1)
+{
+    tcg_gen_bswap32_tl(ret, src1, TCG_BSWAP_OS);
+}
+
 static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
 {
     REQUIRE_32BIT(ctx);
     REQUIRE_ZBB(ctx);
-    return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
+    return gen_unary(ctx, a, EXT_NONE, gen_rev8_32);
 }
 
 static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
-- 
2.25.1



  parent reply	other threads:[~2021-10-07 17:53 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-07 17:47 [RFC PATCH 00/13] target/riscv: Rationalize XLEN and operand length Richard Henderson
2021-10-07 17:47 ` Richard Henderson
2021-10-07 17:47 ` [PATCH 01/13] target/riscv: Move cpu_get_tb_cpu_state out of line Richard Henderson
2021-10-07 17:47   ` Richard Henderson
2021-10-08  2:28   ` Alistair Francis
2021-10-08  2:28     ` Alistair Francis
2021-10-13 12:13   ` LIU Zhiwei
2021-10-13 12:13     ` LIU Zhiwei
2021-10-07 17:47 ` [PATCH 02/13] target/riscv: Create RISCVMXL enumeration Richard Henderson
2021-10-07 17:47   ` Richard Henderson
2021-10-11 23:28   ` Alistair Francis
2021-10-11 23:28     ` Alistair Francis
2021-10-13 12:18   ` LIU Zhiwei
2021-10-13 12:18     ` LIU Zhiwei
2021-10-07 17:47 ` [PATCH 03/13] target/riscv: Split misa.mxl and misa.ext Richard Henderson
2021-10-07 17:47   ` Richard Henderson
2021-10-07 17:47 ` [PATCH 04/13] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl Richard Henderson
2021-10-07 17:47   ` Richard Henderson
2021-10-13 16:46   ` Frédéric Pétrot
2021-10-13 16:46     ` Frédéric Pétrot
2021-10-13 16:54     ` Richard Henderson
2021-10-13 16:54       ` Richard Henderson
2021-10-07 17:47 ` [PATCH 05/13] target/riscv: Add MXL/SXL/UXL to TB_FLAGS Richard Henderson
2021-10-07 17:47   ` Richard Henderson
2021-10-07 17:47 ` [PATCH 06/13] target/riscv: Use REQUIRE_64BIT in amo_check64 Richard Henderson
2021-10-07 17:47   ` Richard Henderson
2021-10-07 17:47 ` [PATCH 07/13] target/riscv: Properly check SEW in amo_op Richard Henderson
2021-10-07 17:47   ` Richard Henderson
2021-10-07 17:47 ` [PATCH 08/13] target/riscv: Replace is_32bit with get_xl/get_xlen Richard Henderson
2021-10-07 17:47   ` Richard Henderson
2021-10-07 17:47 ` [PATCH 09/13] target/riscv: Replace DisasContext.w with DisasContext.ol Richard Henderson
2021-10-07 17:47   ` Richard Henderson
2021-10-07 17:47 ` [PATCH 10/13] target/riscv: Use gen_arith_per_ol for RVM Richard Henderson
2021-10-07 17:47   ` Richard Henderson
2021-10-13 11:54   ` LIU Zhiwei
2021-10-13 11:54     ` LIU Zhiwei
2021-10-07 17:47 ` Richard Henderson [this message]
2021-10-07 17:47   ` [PATCH 11/13] target/riscv: Adjust trans_rev8_32 for riscv64 Richard Henderson
2021-10-13 11:45   ` LIU Zhiwei
2021-10-13 11:45     ` LIU Zhiwei
2021-10-07 17:47 ` [PATCH 12/13] target/riscv: Use gen_unary_per_ol for RVB Richard Henderson
2021-10-07 17:47   ` Richard Henderson
2021-10-13  8:31   ` LIU Zhiwei
2021-10-13  8:31     ` LIU Zhiwei
2021-10-07 17:47 ` [PATCH 13/13] target/riscv: Use gen_shift*_per_ol for RVB, RVI Richard Henderson
2021-10-07 17:47   ` Richard Henderson
2021-10-13 11:24   ` LIU Zhiwei
2021-10-13 11:24     ` LIU Zhiwei
2021-10-10 15:17 ` [RFC PATCH 00/13] target/riscv: Rationalize XLEN and operand length Frédéric Pétrot
2021-10-10 15:17   ` Frédéric Pétrot

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