* [PATCH v11, 0/2] soc: mediatek: mmsys: add mt8192 mmsys support
@ 2021-10-08 2:05 ` Yongqiang Niu
0 siblings, 0 replies; 15+ messages in thread
From: Yongqiang Niu @ 2021-10-08 2:05 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: Rob Herring, Matthias Brugger, Philipp Zabel, David Airlie,
Daniel Vetter, Jassi Brar, Yongqiang Niu, Fabien Parent,
Dennis YC Hsieh, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
Hsin-Yi Wang
base v5.15
Yongqiang Niu (2):
soc: mediatek: mmsys: add comp OVL_2L2/POSTMASK/RDMA4
soc: mediatek: mmsys: Add mt8192 mmsys routing table
drivers/soc/mediatek/mt8192-mmsys.h | 77 ++++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 11 ++++
include/linux/soc/mediatek/mtk-mmsys.h | 3 +
3 files changed, 91 insertions(+)
create mode 100644 drivers/soc/mediatek/mt8192-mmsys.h
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v11, 0/2] soc: mediatek: mmsys: add mt8192 mmsys support
@ 2021-10-08 2:05 ` Yongqiang Niu
0 siblings, 0 replies; 15+ messages in thread
From: Yongqiang Niu @ 2021-10-08 2:05 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: Rob Herring, Matthias Brugger, Philipp Zabel, David Airlie,
Daniel Vetter, Jassi Brar, Yongqiang Niu, Fabien Parent,
Dennis YC Hsieh, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
Hsin-Yi Wang
base v5.15
Yongqiang Niu (2):
soc: mediatek: mmsys: add comp OVL_2L2/POSTMASK/RDMA4
soc: mediatek: mmsys: Add mt8192 mmsys routing table
drivers/soc/mediatek/mt8192-mmsys.h | 77 ++++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 11 ++++
include/linux/soc/mediatek/mtk-mmsys.h | 3 +
3 files changed, 91 insertions(+)
create mode 100644 drivers/soc/mediatek/mt8192-mmsys.h
--
2.25.1
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v11, 1/2] soc: mediatek: mmsys: add comp OVL_2L2/POSTMASK/RDMA4
2021-10-08 2:05 ` Yongqiang Niu
(?)
@ 2021-10-08 2:05 ` Yongqiang Niu
-1 siblings, 0 replies; 15+ messages in thread
From: Yongqiang Niu @ 2021-10-08 2:05 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: Rob Herring, Matthias Brugger, Philipp Zabel, David Airlie,
Daniel Vetter, Jassi Brar, Yongqiang Niu, Fabien Parent,
Dennis YC Hsieh, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
Hsin-Yi Wang, Enric Balletbo i Serra
This patch add some more ddp component
OVL_2L2 is ovl which include 2 layers overlay
POSTMASK control round corner for display frame
RDMA4 read dma buffer
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
include/linux/soc/mediatek/mtk-mmsys.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 2228bf6133da..4bba275e235a 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -29,13 +29,16 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_OVL0,
DDP_COMPONENT_OVL_2L0,
DDP_COMPONENT_OVL_2L1,
+ DDP_COMPONENT_OVL_2L2,
DDP_COMPONENT_OVL1,
+ DDP_COMPONENT_POSTMASK0,
DDP_COMPONENT_PWM0,
DDP_COMPONENT_PWM1,
DDP_COMPONENT_PWM2,
DDP_COMPONENT_RDMA0,
DDP_COMPONENT_RDMA1,
DDP_COMPONENT_RDMA2,
+ DDP_COMPONENT_RDMA4,
DDP_COMPONENT_UFOE,
DDP_COMPONENT_WDMA0,
DDP_COMPONENT_WDMA1,
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v11, 1/2] soc: mediatek: mmsys: add comp OVL_2L2/POSTMASK/RDMA4
@ 2021-10-08 2:05 ` Yongqiang Niu
0 siblings, 0 replies; 15+ messages in thread
From: Yongqiang Niu @ 2021-10-08 2:05 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: Rob Herring, Matthias Brugger, Philipp Zabel, David Airlie,
Daniel Vetter, Jassi Brar, Yongqiang Niu, Fabien Parent,
Dennis YC Hsieh, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
Hsin-Yi Wang, Enric Balletbo i Serra
This patch add some more ddp component
OVL_2L2 is ovl which include 2 layers overlay
POSTMASK control round corner for display frame
RDMA4 read dma buffer
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
include/linux/soc/mediatek/mtk-mmsys.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 2228bf6133da..4bba275e235a 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -29,13 +29,16 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_OVL0,
DDP_COMPONENT_OVL_2L0,
DDP_COMPONENT_OVL_2L1,
+ DDP_COMPONENT_OVL_2L2,
DDP_COMPONENT_OVL1,
+ DDP_COMPONENT_POSTMASK0,
DDP_COMPONENT_PWM0,
DDP_COMPONENT_PWM1,
DDP_COMPONENT_PWM2,
DDP_COMPONENT_RDMA0,
DDP_COMPONENT_RDMA1,
DDP_COMPONENT_RDMA2,
+ DDP_COMPONENT_RDMA4,
DDP_COMPONENT_UFOE,
DDP_COMPONENT_WDMA0,
DDP_COMPONENT_WDMA1,
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v11, 1/2] soc: mediatek: mmsys: add comp OVL_2L2/POSTMASK/RDMA4
@ 2021-10-08 2:05 ` Yongqiang Niu
0 siblings, 0 replies; 15+ messages in thread
From: Yongqiang Niu @ 2021-10-08 2:05 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: Rob Herring, Matthias Brugger, Philipp Zabel, David Airlie,
Daniel Vetter, Jassi Brar, Yongqiang Niu, Fabien Parent,
Dennis YC Hsieh, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
Hsin-Yi Wang, Enric Balletbo i Serra
This patch add some more ddp component
OVL_2L2 is ovl which include 2 layers overlay
POSTMASK control round corner for display frame
RDMA4 read dma buffer
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
include/linux/soc/mediatek/mtk-mmsys.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 2228bf6133da..4bba275e235a 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -29,13 +29,16 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_OVL0,
DDP_COMPONENT_OVL_2L0,
DDP_COMPONENT_OVL_2L1,
+ DDP_COMPONENT_OVL_2L2,
DDP_COMPONENT_OVL1,
+ DDP_COMPONENT_POSTMASK0,
DDP_COMPONENT_PWM0,
DDP_COMPONENT_PWM1,
DDP_COMPONENT_PWM2,
DDP_COMPONENT_RDMA0,
DDP_COMPONENT_RDMA1,
DDP_COMPONENT_RDMA2,
+ DDP_COMPONENT_RDMA4,
DDP_COMPONENT_UFOE,
DDP_COMPONENT_WDMA0,
DDP_COMPONENT_WDMA1,
--
2.25.1
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v11, 2/2] soc: mediatek: mmsys: Add mt8192 mmsys routing table
2021-10-08 2:05 ` Yongqiang Niu
(?)
@ 2021-10-08 2:05 ` Yongqiang Niu
-1 siblings, 0 replies; 15+ messages in thread
From: Yongqiang Niu @ 2021-10-08 2:05 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: Rob Herring, Matthias Brugger, Philipp Zabel, David Airlie,
Daniel Vetter, Jassi Brar, Yongqiang Niu, Fabien Parent,
Dennis YC Hsieh, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
Hsin-Yi Wang, Enric Balletbo i Serra
mt8192 has different routing registers than mt8183
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
---
drivers/soc/mediatek/mt8192-mmsys.h | 77 +++++++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 11 +++++
2 files changed, 88 insertions(+)
create mode 100644 drivers/soc/mediatek/mt8192-mmsys.h
diff --git a/drivers/soc/mediatek/mt8192-mmsys.h b/drivers/soc/mediatek/mt8192-mmsys.h
new file mode 100644
index 000000000000..7ea1531ee8af
--- /dev/null
+++ b/drivers/soc/mediatek/mt8192-mmsys.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8192_MMSYS_H
+#define __SOC_MEDIATEK_MT8192_MMSYS_H
+
+#define MT8192_MMSYS_OVL_MOUT_EN 0xf04
+#define MT8192_DISP_OVL1_2L_MOUT_EN 0xf08
+#define MT8192_DISP_OVL0_2L_MOUT_EN 0xf18
+#define MT8192_DISP_OVL0_MOUT_EN 0xf1c
+#define MT8192_DISP_RDMA0_SEL_IN 0xf2c
+#define MT8192_DISP_RDMA0_SOUT_SEL 0xf30
+#define MT8192_DISP_CCORR0_SOUT_SEL 0xf34
+#define MT8192_DISP_AAL0_SEL_IN 0xf38
+#define MT8192_DISP_DITHER0_MOUT_EN 0xf3c
+#define MT8192_DISP_DSI0_SEL_IN 0xf40
+#define MT8192_DISP_OVL2_2L_MOUT_EN 0xf4c
+
+#define MT8192_DISP_OVL0_GO_BLEND BIT(0)
+#define MT8192_DITHER0_MOUT_IN_DSI0 BIT(0)
+#define MT8192_OVL0_MOUT_EN_DISP_RDMA0 BIT(0)
+#define MT8192_OVL2_2L_MOUT_EN_RDMA4 BIT(0)
+#define MT8192_DISP_OVL0_GO_BG BIT(1)
+#define MT8192_DISP_OVL0_2L_GO_BLEND BIT(2)
+#define MT8192_DISP_OVL0_2L_GO_BG BIT(3)
+#define MT8192_OVL1_2L_MOUT_EN_RDMA1 BIT(4)
+#define MT8192_OVL0_MOUT_EN_OVL0_2L BIT(4)
+#define MT8192_RDMA0_SEL_IN_OVL0_2L 0x3
+#define MT8192_RDMA0_SOUT_COLOR0 0x1
+#define MT8192_CCORR0_SOUT_AAL0 0x1
+#define MT8192_AAL0_SEL_IN_CCORR0 0x1
+#define MT8192_DSI0_SEL_IN_DITHER0 0x1
+
+static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
+ {
+ DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
+ MT8192_DISP_OVL0_2L_MOUT_EN, MT8192_OVL0_MOUT_EN_DISP_RDMA0,
+ MT8192_OVL0_MOUT_EN_DISP_RDMA0
+ }, {
+ DDP_COMPONENT_OVL_2L2, DDP_COMPONENT_RDMA4,
+ MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4,
+ MT8192_OVL2_2L_MOUT_EN_RDMA4
+ }, {
+ DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0,
+ MT8192_DITHER0_MOUT_IN_DSI0
+ }, {
+ DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
+ MT8192_DISP_RDMA0_SEL_IN, MT8192_RDMA0_SEL_IN_OVL0_2L,
+ MT8192_RDMA0_SEL_IN_OVL0_2L
+ }, {
+ DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0,
+ MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0,
+ MT8192_AAL0_SEL_IN_CCORR0
+ }, {
+ DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0,
+ MT8192_DSI0_SEL_IN_DITHER0
+ }, {
+ DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
+ MT8192_DISP_RDMA0_SOUT_SEL, MT8192_RDMA0_SOUT_COLOR0,
+ MT8192_RDMA0_SOUT_COLOR0
+ }, {
+ DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0,
+ MT8192_DISP_CCORR0_SOUT_SEL, MT8192_CCORR0_SOUT_AAL0,
+ MT8192_CCORR0_SOUT_AAL0
+ }, {
+ DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,
+ MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_GO_BG,
+ MT8192_DISP_OVL0_GO_BG,
+ }, {
+ DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
+ MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_2L_GO_BLEND,
+ MT8192_DISP_OVL0_2L_GO_BLEND,
+ }
+};
+
+#endif /* __SOC_MEDIATEK_MT8192_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index a78e88f27b62..5ecfe09a5751 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -13,6 +13,7 @@
#include "mtk-mmsys.h"
#include "mt8167-mmsys.h"
#include "mt8183-mmsys.h"
+#include "mt8192-mmsys.h"
#include "mt8365-mmsys.h"
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
@@ -53,6 +54,12 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
};
+static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
+ .clk_driver = "clk-mt8192-mm",
+ .routes = mmsys_mt8192_routing_table,
+ .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
+};
+
static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
.clk_driver = "clk-mt8365-mm",
.routes = mt8365_mmsys_routing_table,
@@ -167,6 +174,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
.compatible = "mediatek,mt8183-mmsys",
.data = &mt8183_mmsys_driver_data,
},
+ {
+ .compatible = "mediatek,mt8192-mmsys",
+ .data = &mt8192_mmsys_driver_data,
+ },
{
.compatible = "mediatek,mt8365-mmsys",
.data = &mt8365_mmsys_driver_data,
--
2.25.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v11, 2/2] soc: mediatek: mmsys: Add mt8192 mmsys routing table
@ 2021-10-08 2:05 ` Yongqiang Niu
0 siblings, 0 replies; 15+ messages in thread
From: Yongqiang Niu @ 2021-10-08 2:05 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: Rob Herring, Matthias Brugger, Philipp Zabel, David Airlie,
Daniel Vetter, Jassi Brar, Yongqiang Niu, Fabien Parent,
Dennis YC Hsieh, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
Hsin-Yi Wang, Enric Balletbo i Serra
mt8192 has different routing registers than mt8183
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
---
drivers/soc/mediatek/mt8192-mmsys.h | 77 +++++++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 11 +++++
2 files changed, 88 insertions(+)
create mode 100644 drivers/soc/mediatek/mt8192-mmsys.h
diff --git a/drivers/soc/mediatek/mt8192-mmsys.h b/drivers/soc/mediatek/mt8192-mmsys.h
new file mode 100644
index 000000000000..7ea1531ee8af
--- /dev/null
+++ b/drivers/soc/mediatek/mt8192-mmsys.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8192_MMSYS_H
+#define __SOC_MEDIATEK_MT8192_MMSYS_H
+
+#define MT8192_MMSYS_OVL_MOUT_EN 0xf04
+#define MT8192_DISP_OVL1_2L_MOUT_EN 0xf08
+#define MT8192_DISP_OVL0_2L_MOUT_EN 0xf18
+#define MT8192_DISP_OVL0_MOUT_EN 0xf1c
+#define MT8192_DISP_RDMA0_SEL_IN 0xf2c
+#define MT8192_DISP_RDMA0_SOUT_SEL 0xf30
+#define MT8192_DISP_CCORR0_SOUT_SEL 0xf34
+#define MT8192_DISP_AAL0_SEL_IN 0xf38
+#define MT8192_DISP_DITHER0_MOUT_EN 0xf3c
+#define MT8192_DISP_DSI0_SEL_IN 0xf40
+#define MT8192_DISP_OVL2_2L_MOUT_EN 0xf4c
+
+#define MT8192_DISP_OVL0_GO_BLEND BIT(0)
+#define MT8192_DITHER0_MOUT_IN_DSI0 BIT(0)
+#define MT8192_OVL0_MOUT_EN_DISP_RDMA0 BIT(0)
+#define MT8192_OVL2_2L_MOUT_EN_RDMA4 BIT(0)
+#define MT8192_DISP_OVL0_GO_BG BIT(1)
+#define MT8192_DISP_OVL0_2L_GO_BLEND BIT(2)
+#define MT8192_DISP_OVL0_2L_GO_BG BIT(3)
+#define MT8192_OVL1_2L_MOUT_EN_RDMA1 BIT(4)
+#define MT8192_OVL0_MOUT_EN_OVL0_2L BIT(4)
+#define MT8192_RDMA0_SEL_IN_OVL0_2L 0x3
+#define MT8192_RDMA0_SOUT_COLOR0 0x1
+#define MT8192_CCORR0_SOUT_AAL0 0x1
+#define MT8192_AAL0_SEL_IN_CCORR0 0x1
+#define MT8192_DSI0_SEL_IN_DITHER0 0x1
+
+static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
+ {
+ DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
+ MT8192_DISP_OVL0_2L_MOUT_EN, MT8192_OVL0_MOUT_EN_DISP_RDMA0,
+ MT8192_OVL0_MOUT_EN_DISP_RDMA0
+ }, {
+ DDP_COMPONENT_OVL_2L2, DDP_COMPONENT_RDMA4,
+ MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4,
+ MT8192_OVL2_2L_MOUT_EN_RDMA4
+ }, {
+ DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0,
+ MT8192_DITHER0_MOUT_IN_DSI0
+ }, {
+ DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
+ MT8192_DISP_RDMA0_SEL_IN, MT8192_RDMA0_SEL_IN_OVL0_2L,
+ MT8192_RDMA0_SEL_IN_OVL0_2L
+ }, {
+ DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0,
+ MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0,
+ MT8192_AAL0_SEL_IN_CCORR0
+ }, {
+ DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0,
+ MT8192_DSI0_SEL_IN_DITHER0
+ }, {
+ DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
+ MT8192_DISP_RDMA0_SOUT_SEL, MT8192_RDMA0_SOUT_COLOR0,
+ MT8192_RDMA0_SOUT_COLOR0
+ }, {
+ DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0,
+ MT8192_DISP_CCORR0_SOUT_SEL, MT8192_CCORR0_SOUT_AAL0,
+ MT8192_CCORR0_SOUT_AAL0
+ }, {
+ DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,
+ MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_GO_BG,
+ MT8192_DISP_OVL0_GO_BG,
+ }, {
+ DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
+ MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_2L_GO_BLEND,
+ MT8192_DISP_OVL0_2L_GO_BLEND,
+ }
+};
+
+#endif /* __SOC_MEDIATEK_MT8192_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index a78e88f27b62..5ecfe09a5751 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -13,6 +13,7 @@
#include "mtk-mmsys.h"
#include "mt8167-mmsys.h"
#include "mt8183-mmsys.h"
+#include "mt8192-mmsys.h"
#include "mt8365-mmsys.h"
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
@@ -53,6 +54,12 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
};
+static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
+ .clk_driver = "clk-mt8192-mm",
+ .routes = mmsys_mt8192_routing_table,
+ .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
+};
+
static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
.clk_driver = "clk-mt8365-mm",
.routes = mt8365_mmsys_routing_table,
@@ -167,6 +174,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
.compatible = "mediatek,mt8183-mmsys",
.data = &mt8183_mmsys_driver_data,
},
+ {
+ .compatible = "mediatek,mt8192-mmsys",
+ .data = &mt8192_mmsys_driver_data,
+ },
{
.compatible = "mediatek,mt8365-mmsys",
.data = &mt8365_mmsys_driver_data,
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v11, 2/2] soc: mediatek: mmsys: Add mt8192 mmsys routing table
@ 2021-10-08 2:05 ` Yongqiang Niu
0 siblings, 0 replies; 15+ messages in thread
From: Yongqiang Niu @ 2021-10-08 2:05 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: Rob Herring, Matthias Brugger, Philipp Zabel, David Airlie,
Daniel Vetter, Jassi Brar, Yongqiang Niu, Fabien Parent,
Dennis YC Hsieh, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
Hsin-Yi Wang, Enric Balletbo i Serra
mt8192 has different routing registers than mt8183
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
---
drivers/soc/mediatek/mt8192-mmsys.h | 77 +++++++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 11 +++++
2 files changed, 88 insertions(+)
create mode 100644 drivers/soc/mediatek/mt8192-mmsys.h
diff --git a/drivers/soc/mediatek/mt8192-mmsys.h b/drivers/soc/mediatek/mt8192-mmsys.h
new file mode 100644
index 000000000000..7ea1531ee8af
--- /dev/null
+++ b/drivers/soc/mediatek/mt8192-mmsys.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8192_MMSYS_H
+#define __SOC_MEDIATEK_MT8192_MMSYS_H
+
+#define MT8192_MMSYS_OVL_MOUT_EN 0xf04
+#define MT8192_DISP_OVL1_2L_MOUT_EN 0xf08
+#define MT8192_DISP_OVL0_2L_MOUT_EN 0xf18
+#define MT8192_DISP_OVL0_MOUT_EN 0xf1c
+#define MT8192_DISP_RDMA0_SEL_IN 0xf2c
+#define MT8192_DISP_RDMA0_SOUT_SEL 0xf30
+#define MT8192_DISP_CCORR0_SOUT_SEL 0xf34
+#define MT8192_DISP_AAL0_SEL_IN 0xf38
+#define MT8192_DISP_DITHER0_MOUT_EN 0xf3c
+#define MT8192_DISP_DSI0_SEL_IN 0xf40
+#define MT8192_DISP_OVL2_2L_MOUT_EN 0xf4c
+
+#define MT8192_DISP_OVL0_GO_BLEND BIT(0)
+#define MT8192_DITHER0_MOUT_IN_DSI0 BIT(0)
+#define MT8192_OVL0_MOUT_EN_DISP_RDMA0 BIT(0)
+#define MT8192_OVL2_2L_MOUT_EN_RDMA4 BIT(0)
+#define MT8192_DISP_OVL0_GO_BG BIT(1)
+#define MT8192_DISP_OVL0_2L_GO_BLEND BIT(2)
+#define MT8192_DISP_OVL0_2L_GO_BG BIT(3)
+#define MT8192_OVL1_2L_MOUT_EN_RDMA1 BIT(4)
+#define MT8192_OVL0_MOUT_EN_OVL0_2L BIT(4)
+#define MT8192_RDMA0_SEL_IN_OVL0_2L 0x3
+#define MT8192_RDMA0_SOUT_COLOR0 0x1
+#define MT8192_CCORR0_SOUT_AAL0 0x1
+#define MT8192_AAL0_SEL_IN_CCORR0 0x1
+#define MT8192_DSI0_SEL_IN_DITHER0 0x1
+
+static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
+ {
+ DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
+ MT8192_DISP_OVL0_2L_MOUT_EN, MT8192_OVL0_MOUT_EN_DISP_RDMA0,
+ MT8192_OVL0_MOUT_EN_DISP_RDMA0
+ }, {
+ DDP_COMPONENT_OVL_2L2, DDP_COMPONENT_RDMA4,
+ MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4,
+ MT8192_OVL2_2L_MOUT_EN_RDMA4
+ }, {
+ DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0,
+ MT8192_DITHER0_MOUT_IN_DSI0
+ }, {
+ DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
+ MT8192_DISP_RDMA0_SEL_IN, MT8192_RDMA0_SEL_IN_OVL0_2L,
+ MT8192_RDMA0_SEL_IN_OVL0_2L
+ }, {
+ DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0,
+ MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0,
+ MT8192_AAL0_SEL_IN_CCORR0
+ }, {
+ DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0,
+ MT8192_DSI0_SEL_IN_DITHER0
+ }, {
+ DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
+ MT8192_DISP_RDMA0_SOUT_SEL, MT8192_RDMA0_SOUT_COLOR0,
+ MT8192_RDMA0_SOUT_COLOR0
+ }, {
+ DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0,
+ MT8192_DISP_CCORR0_SOUT_SEL, MT8192_CCORR0_SOUT_AAL0,
+ MT8192_CCORR0_SOUT_AAL0
+ }, {
+ DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,
+ MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_GO_BG,
+ MT8192_DISP_OVL0_GO_BG,
+ }, {
+ DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
+ MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_2L_GO_BLEND,
+ MT8192_DISP_OVL0_2L_GO_BLEND,
+ }
+};
+
+#endif /* __SOC_MEDIATEK_MT8192_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index a78e88f27b62..5ecfe09a5751 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -13,6 +13,7 @@
#include "mtk-mmsys.h"
#include "mt8167-mmsys.h"
#include "mt8183-mmsys.h"
+#include "mt8192-mmsys.h"
#include "mt8365-mmsys.h"
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
@@ -53,6 +54,12 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
};
+static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
+ .clk_driver = "clk-mt8192-mm",
+ .routes = mmsys_mt8192_routing_table,
+ .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
+};
+
static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
.clk_driver = "clk-mt8365-mm",
.routes = mt8365_mmsys_routing_table,
@@ -167,6 +174,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
.compatible = "mediatek,mt8183-mmsys",
.data = &mt8183_mmsys_driver_data,
},
+ {
+ .compatible = "mediatek,mt8192-mmsys",
+ .data = &mt8192_mmsys_driver_data,
+ },
{
.compatible = "mediatek,mt8365-mmsys",
.data = &mt8365_mmsys_driver_data,
--
2.25.1
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v11, 0/2] soc: mediatek: mmsys: add mt8192 mmsys support
2021-10-08 2:05 ` Yongqiang Niu
(?)
@ 2021-10-08 11:37 ` Matthias Brugger
-1 siblings, 0 replies; 15+ messages in thread
From: Matthias Brugger @ 2021-10-08 11:37 UTC (permalink / raw)
To: Yongqiang Niu, Chun-Kuang Hu
Cc: Rob Herring, Philipp Zabel, David Airlie, Daniel Vetter,
Jassi Brar, Fabien Parent, Dennis YC Hsieh, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group, Hsin-Yi Wang
On 08/10/2021 04:05, Yongqiang Niu wrote:
> base v5.15
>
> Yongqiang Niu (2):
> soc: mediatek: mmsys: add comp OVL_2L2/POSTMASK/RDMA4
> soc: mediatek: mmsys: Add mt8192 mmsys routing table
I'm a bit puzzled that you keep on sending this series while I accepted an older
one long time ago:
https://lore.kernel.org/lkml/e4afa712-9936-15fc-ad43-576948758f6c@gmail.com/
As you don't provide a changelog I'm not able to find out what has changed. I
also asked you to double check if the fixup I did was correct, but you never
answered.
If there are anything to fix for this series that's not in my tree yet, please
send a follow-up patch.
Regards,
Matthias
>
> drivers/soc/mediatek/mt8192-mmsys.h | 77 ++++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.c | 11 ++++
> include/linux/soc/mediatek/mtk-mmsys.h | 3 +
> 3 files changed, 91 insertions(+)
> create mode 100644 drivers/soc/mediatek/mt8192-mmsys.h
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v11, 0/2] soc: mediatek: mmsys: add mt8192 mmsys support
@ 2021-10-08 11:37 ` Matthias Brugger
0 siblings, 0 replies; 15+ messages in thread
From: Matthias Brugger @ 2021-10-08 11:37 UTC (permalink / raw)
To: Yongqiang Niu, Chun-Kuang Hu
Cc: Rob Herring, Philipp Zabel, David Airlie, Daniel Vetter,
Jassi Brar, Fabien Parent, Dennis YC Hsieh, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group, Hsin-Yi Wang
On 08/10/2021 04:05, Yongqiang Niu wrote:
> base v5.15
>
> Yongqiang Niu (2):
> soc: mediatek: mmsys: add comp OVL_2L2/POSTMASK/RDMA4
> soc: mediatek: mmsys: Add mt8192 mmsys routing table
I'm a bit puzzled that you keep on sending this series while I accepted an older
one long time ago:
https://lore.kernel.org/lkml/e4afa712-9936-15fc-ad43-576948758f6c@gmail.com/
As you don't provide a changelog I'm not able to find out what has changed. I
also asked you to double check if the fixup I did was correct, but you never
answered.
If there are anything to fix for this series that's not in my tree yet, please
send a follow-up patch.
Regards,
Matthias
>
> drivers/soc/mediatek/mt8192-mmsys.h | 77 ++++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.c | 11 ++++
> include/linux/soc/mediatek/mtk-mmsys.h | 3 +
> 3 files changed, 91 insertions(+)
> create mode 100644 drivers/soc/mediatek/mt8192-mmsys.h
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v11, 0/2] soc: mediatek: mmsys: add mt8192 mmsys support
@ 2021-10-08 11:37 ` Matthias Brugger
0 siblings, 0 replies; 15+ messages in thread
From: Matthias Brugger @ 2021-10-08 11:37 UTC (permalink / raw)
To: Yongqiang Niu, Chun-Kuang Hu
Cc: Rob Herring, Philipp Zabel, David Airlie, Daniel Vetter,
Jassi Brar, Fabien Parent, Dennis YC Hsieh, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group, Hsin-Yi Wang
On 08/10/2021 04:05, Yongqiang Niu wrote:
> base v5.15
>
> Yongqiang Niu (2):
> soc: mediatek: mmsys: add comp OVL_2L2/POSTMASK/RDMA4
> soc: mediatek: mmsys: Add mt8192 mmsys routing table
I'm a bit puzzled that you keep on sending this series while I accepted an older
one long time ago:
https://lore.kernel.org/lkml/e4afa712-9936-15fc-ad43-576948758f6c@gmail.com/
As you don't provide a changelog I'm not able to find out what has changed. I
also asked you to double check if the fixup I did was correct, but you never
answered.
If there are anything to fix for this series that's not in my tree yet, please
send a follow-up patch.
Regards,
Matthias
>
> drivers/soc/mediatek/mt8192-mmsys.h | 77 ++++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.c | 11 ++++
> include/linux/soc/mediatek/mtk-mmsys.h | 3 +
> 3 files changed, 91 insertions(+)
> create mode 100644 drivers/soc/mediatek/mt8192-mmsys.h
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v11, 0/2] soc: mediatek: mmsys: add mt8192 mmsys support
2021-10-08 11:37 ` Matthias Brugger
(?)
@ 2021-11-08 1:54 ` yongqiang.niu
-1 siblings, 0 replies; 15+ messages in thread
From: yongqiang.niu @ 2021-11-08 1:54 UTC (permalink / raw)
To: Matthias Brugger, Chun-Kuang Hu
Cc: Rob Herring, Philipp Zabel, David Airlie, Daniel Vetter,
Jassi Brar, Fabien Parent, Dennis YC Hsieh, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group, Hsin-Yi Wang
On Fri, 2021-10-08 at 13:37 +0200, Matthias Brugger wrote:
>
> On 08/10/2021 04:05, Yongqiang Niu wrote:
> > base v5.15
> >
> > Yongqiang Niu (2):
> > soc: mediatek: mmsys: add comp OVL_2L2/POSTMASK/RDMA4
> > soc: mediatek: mmsys: Add mt8192 mmsys routing table
>
> I'm a bit puzzled that you keep on sending this series while I
> accepted an older
> one long time ago:
>
https://lore.kernel.org/lkml/e4afa712-9936-15fc-ad43-576948758f6c@gmail.com/
>
> As you don't provide a changelog I'm not able to find out what has
> changed. I
> also asked you to double check if the fixup I did was correct, but
> you never
> answered.
>
> If there are anything to fix for this series that's not in my tree
> yet, please
> send a follow-up patch.
>
> Regards,
> Matthias
>
the fixup you have add is correct.
this version only adjust the header filer include sequence in mtk-
mmsys.c
original version
#include "mt8365-mmsys.h"
#include "mt8192-mmsys.h"
new version
#include "mt8192-mmsys.h"
#include "mt8365-mmsys.h"
> >
> > drivers/soc/mediatek/mt8192-mmsys.h | 77
> > ++++++++++++++++++++++++++
> > drivers/soc/mediatek/mtk-mmsys.c | 11 ++++
> > include/linux/soc/mediatek/mtk-mmsys.h | 3 +
> > 3 files changed, 91 insertions(+)
> > create mode 100644 drivers/soc/mediatek/mt8192-mmsys.h
> >
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v11, 0/2] soc: mediatek: mmsys: add mt8192 mmsys support
@ 2021-11-08 1:54 ` yongqiang.niu
0 siblings, 0 replies; 15+ messages in thread
From: yongqiang.niu @ 2021-11-08 1:54 UTC (permalink / raw)
To: Matthias Brugger, Chun-Kuang Hu
Cc: Rob Herring, Philipp Zabel, David Airlie, Daniel Vetter,
Jassi Brar, Fabien Parent, Dennis YC Hsieh, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, dri-devel,
Project_Global_Chrome_Upstream_Group, Hsin-Yi Wang
On Fri, 2021-10-08 at 13:37 +0200, Matthias Brugger wrote:
>
> On 08/10/2021 04:05, Yongqiang Niu wrote:
> > base v5.15
> >
> > Yongqiang Niu (2):
> > soc: mediatek: mmsys: add comp OVL_2L2/POSTMASK/RDMA4
> > soc: mediatek: mmsys: Add mt8192 mmsys routing table
>
> I'm a bit puzzled that you keep on sending this series while I
> accepted an older
> one long time ago:
>
https://lore.kernel.org/lkml/e4afa712-9936-15fc-ad43-576948758f6c@gmail.com/
>
> As you don't provide a changelog I'm not able to find out what has
> changed. I
> also asked you to double check if the fixup I did was correct, but
> you never
> answered.
>
> If there are anything to fix for this series that's not in my tree
> yet, please
> send a follow-up patch.
>
> Regards,
> Matthias
>
the fixup you have add is correct.
this version only adjust the header filer include sequence in mtk-
mmsys.c
original version
#include "mt8365-mmsys.h"
#include "mt8192-mmsys.h"
new version
#include "mt8192-mmsys.h"
#include "mt8365-mmsys.h"
> >
> > drivers/soc/mediatek/mt8192-mmsys.h | 77
> > ++++++++++++++++++++++++++
> > drivers/soc/mediatek/mtk-mmsys.c | 11 ++++
> > include/linux/soc/mediatek/mtk-mmsys.h | 3 +
> > 3 files changed, 91 insertions(+)
> > create mode 100644 drivers/soc/mediatek/mt8192-mmsys.h
> >
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v11, 0/2] soc: mediatek: mmsys: add mt8192 mmsys support
@ 2021-11-08 1:54 ` yongqiang.niu
0 siblings, 0 replies; 15+ messages in thread
From: yongqiang.niu @ 2021-11-08 1:54 UTC (permalink / raw)
To: Matthias Brugger, Chun-Kuang Hu
Cc: devicetree, Project_Global_Chrome_Upstream_Group, David Airlie,
Jassi Brar, linux-kernel, dri-devel, Dennis YC Hsieh,
Fabien Parent, Rob Herring, linux-mediatek, Hsin-Yi Wang,
linux-arm-kernel
On Fri, 2021-10-08 at 13:37 +0200, Matthias Brugger wrote:
>
> On 08/10/2021 04:05, Yongqiang Niu wrote:
> > base v5.15
> >
> > Yongqiang Niu (2):
> > soc: mediatek: mmsys: add comp OVL_2L2/POSTMASK/RDMA4
> > soc: mediatek: mmsys: Add mt8192 mmsys routing table
>
> I'm a bit puzzled that you keep on sending this series while I
> accepted an older
> one long time ago:
>
https://lore.kernel.org/lkml/e4afa712-9936-15fc-ad43-576948758f6c@gmail.com/
>
> As you don't provide a changelog I'm not able to find out what has
> changed. I
> also asked you to double check if the fixup I did was correct, but
> you never
> answered.
>
> If there are anything to fix for this series that's not in my tree
> yet, please
> send a follow-up patch.
>
> Regards,
> Matthias
>
the fixup you have add is correct.
this version only adjust the header filer include sequence in mtk-
mmsys.c
original version
#include "mt8365-mmsys.h"
#include "mt8192-mmsys.h"
new version
#include "mt8192-mmsys.h"
#include "mt8365-mmsys.h"
> >
> > drivers/soc/mediatek/mt8192-mmsys.h | 77
> > ++++++++++++++++++++++++++
> > drivers/soc/mediatek/mtk-mmsys.c | 11 ++++
> > include/linux/soc/mediatek/mtk-mmsys.h | 3 +
> > 3 files changed, 91 insertions(+)
> > create mode 100644 drivers/soc/mediatek/mt8192-mmsys.h
> >
^ permalink raw reply [flat|nested] 15+ messages in thread