[PATCH v7 06/11] KVM: arm64: Simplify masking out MTE in feature id reg

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From: Fuad Tabba <tabba@google.com>
To: kvmarm@lists.cs.columbia.edu
Cc: maz@kernel.org, will@kernel.org, james.morse@arm.com,
	alexandru.elisei@arm.com, suzuki.poulose@arm.com,
	mark.rutland@arm.com, christoffer.dall@arm.com,
	pbonzini@redhat.com, drjones@redhat.com, oupton@google.com,
	qperret@google.com, kvm@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, kernel-team@android.com,
	tabba@google.com
Subject: [PATCH v7 06/11] KVM: arm64: Simplify masking out MTE in feature id reg
Date: Fri,  8 Oct 2021 16:58:27 +0100	[thread overview]
Message-ID: <20211008155832.1415010-7-tabba@google.com> (raw)
In-Reply-To: <20211008155832.1415010-1-tabba@google.com>

Simplify code for hiding MTE support in feature id register when
MTE is not enabled/supported by KVM.

No functional change intended.

Signed-off-by: Fuad Tabba <tabba@google.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
---
 arch/arm64/kvm/sys_regs.c | 10 ++--------
 1 file changed, 2 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 1d46e185f31e..447acce9ca84 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -1077,14 +1077,8 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu,
 		val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_CSV3), (u64)vcpu->kvm->arch.pfr0_csv3);
 		break;
 	case SYS_ID_AA64PFR1_EL1:
-		val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_MTE);
-		if (kvm_has_mte(vcpu->kvm)) {
-			u64 pfr, mte;
-
-			pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1);
-			mte = cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR1_MTE_SHIFT);
-			val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR1_MTE), mte);
-		}
+		if (!kvm_has_mte(vcpu->kvm))
+			val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_MTE);
 		break;
 	case SYS_ID_AA64ISAR1_EL1:
 		if (!vcpu_has_ptrauth(vcpu))
-- 
2.33.0.882.g93a45727a2-goog

WARNING: multiple messages have this Message-ID (diff)

From: Fuad Tabba <tabba@google.com>
To: kvmarm@lists.cs.columbia.edu
Cc: kernel-team@android.com, kvm@vger.kernel.org, maz@kernel.org,
	pbonzini@redhat.com, will@kernel.org,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v7 06/11] KVM: arm64: Simplify masking out MTE in feature id reg
Date: Fri,  8 Oct 2021 16:58:27 +0100	[thread overview]
Message-ID: <20211008155832.1415010-7-tabba@google.com> (raw)
In-Reply-To: <20211008155832.1415010-1-tabba@google.com>

Simplify code for hiding MTE support in feature id register when
MTE is not enabled/supported by KVM.

No functional change intended.

Signed-off-by: Fuad Tabba <tabba@google.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
---
 arch/arm64/kvm/sys_regs.c | 10 ++--------
 1 file changed, 2 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 1d46e185f31e..447acce9ca84 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -1077,14 +1077,8 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu,
 		val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_CSV3), (u64)vcpu->kvm->arch.pfr0_csv3);
 		break;
 	case SYS_ID_AA64PFR1_EL1:
-		val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_MTE);
-		if (kvm_has_mte(vcpu->kvm)) {
-			u64 pfr, mte;
-
-			pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1);
-			mte = cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR1_MTE_SHIFT);
-			val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR1_MTE), mte);
-		}
+		if (!kvm_has_mte(vcpu->kvm))
+			val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_MTE);
 		break;
 	case SYS_ID_AA64ISAR1_EL1:
 		if (!vcpu_has_ptrauth(vcpu))
-- 
2.33.0.882.g93a45727a2-goog

_______________________________________________
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kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm

WARNING: multiple messages have this Message-ID (diff)

From: Fuad Tabba <tabba@google.com>
To: kvmarm@lists.cs.columbia.edu
Cc: maz@kernel.org, will@kernel.org, james.morse@arm.com,
	 alexandru.elisei@arm.com, suzuki.poulose@arm.com,
	mark.rutland@arm.com,  christoffer.dall@arm.com,
	pbonzini@redhat.com, drjones@redhat.com,  oupton@google.com,
	qperret@google.com, kvm@vger.kernel.org,
	 linux-arm-kernel@lists.infradead.org, kernel-team@android.com,
	 tabba@google.com
Subject: [PATCH v7 06/11] KVM: arm64: Simplify masking out MTE in feature id reg
Date: Fri,  8 Oct 2021 16:58:27 +0100	[thread overview]
Message-ID: <20211008155832.1415010-7-tabba@google.com> (raw)
In-Reply-To: <20211008155832.1415010-1-tabba@google.com>

Simplify code for hiding MTE support in feature id register when
MTE is not enabled/supported by KVM.

No functional change intended.

Signed-off-by: Fuad Tabba <tabba@google.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
---
 arch/arm64/kvm/sys_regs.c | 10 ++--------
 1 file changed, 2 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 1d46e185f31e..447acce9ca84 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -1077,14 +1077,8 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu,
 		val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_CSV3), (u64)vcpu->kvm->arch.pfr0_csv3);
 		break;
 	case SYS_ID_AA64PFR1_EL1:
-		val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_MTE);
-		if (kvm_has_mte(vcpu->kvm)) {
-			u64 pfr, mte;
-
-			pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1);
-			mte = cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR1_MTE_SHIFT);
-			val |= FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR1_MTE), mte);
-		}
+		if (!kvm_has_mte(vcpu->kvm))
+			val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_MTE);
 		break;
 	case SYS_ID_AA64ISAR1_EL1:
 		if (!vcpu_has_ptrauth(vcpu))
-- 
2.33.0.882.g93a45727a2-goog


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

next prev parent reply	other threads:[~2021-10-08 15:58 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-08 15:58 [PATCH v7 00/11] KVM: arm64: Fixed features for protected VMs Fuad Tabba
2021-10-08 15:58 ` Fuad Tabba
2021-10-08 15:58 ` Fuad Tabba
2021-10-08 15:58 ` [PATCH v7 01/11] KVM: arm64: Move __get_fault_info() and co into their own include file Fuad Tabba
2021-10-08 15:58   ` Fuad Tabba
2021-10-08 15:58   ` Fuad Tabba
2021-10-08 15:58 ` [PATCH v7 02/11] KVM: arm64: Don't include switch.h into nvhe/kvm-main.c Fuad Tabba
2021-10-08 15:58   ` Fuad Tabba
2021-10-08 15:58   ` Fuad Tabba
2021-10-08 15:58 ` [PATCH v7 03/11] KVM: arm64: Move early handlers to per-EC handlers Fuad Tabba
2021-10-08 15:58   ` Fuad Tabba
2021-10-08 15:58   ` Fuad Tabba
2021-10-08 15:58 ` [PATCH v7 04/11] KVM: arm64: Pass struct kvm " Fuad Tabba
2021-10-08 15:58   ` Fuad Tabba
2021-10-08 15:58   ` Fuad Tabba
2021-10-08 15:58 ` [PATCH v7 05/11] KVM: arm64: Add missing field descriptor for MDCR_EL2 Fuad Tabba
2021-10-08 15:58   ` Fuad Tabba
2021-10-08 15:58   ` Fuad Tabba
2021-10-08 15:58 ` Fuad Tabba [this message]
2021-10-08 15:58   ` [PATCH v7 06/11] KVM: arm64: Simplify masking out MTE in feature id reg Fuad Tabba
2021-10-08 15:58   ` Fuad Tabba
2021-10-08 15:58 ` [PATCH v7 07/11] KVM: arm64: Add handlers for protected VM System Registers Fuad Tabba
2021-10-08 15:58   ` Fuad Tabba
2021-10-08 15:58   ` Fuad Tabba
2021-10-10  0:43   ` kernel test robot
2021-10-10  0:43     ` kernel test robot
2021-10-08 15:58 ` [PATCH v7 08/11] KVM: arm64: Initialize trap registers for protected VMs Fuad Tabba
2021-10-08 15:58   ` Fuad Tabba
2021-10-08 15:58   ` Fuad Tabba
2021-10-10  1:52   ` kernel test robot
2021-10-10  1:52     ` kernel test robot
2021-10-08 15:58 ` [PATCH v7 09/11] KVM: arm64: Move sanitized copies of CPU features Fuad Tabba
2021-10-08 15:58   ` Fuad Tabba
2021-10-08 15:58   ` Fuad Tabba
2021-10-08 15:58 ` [PATCH v7 10/11] KVM: arm64: Trap access to pVM restricted features Fuad Tabba
2021-10-08 15:58   ` Fuad Tabba
2021-10-08 15:58   ` Fuad Tabba
2021-10-08 15:58 ` [PATCH v7 11/11] KVM: arm64: Handle protected guests at 32 bits Fuad Tabba
2021-10-08 15:58   ` Fuad Tabba
2021-10-08 15:58   ` Fuad Tabba

find likely ancestor, descendant, or conflicting patches for this message:
dfblob:1d46e185f31 dfblob:1d46e185f31 dfblob:1d46e185f31
dfblob:447acce9ca8 dfblob:447acce9ca8 dfblob:447acce9ca8
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