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From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, will@kernel.org,
	catalin.marinas@arm.com, mathieu.poirier@linaro.org,
	mike.leach@linaro.org, leo.yan@linaro.org,
	anshuman.khandual@arm.com, coresight@lists.linaro.org,
	maz@kernel.org, james.morse@arm.com, mark.rutland@arm.com,
	lcherian@marvell.com, Suzuki K Poulose <suzuki.poulose@arm.com>
Subject: [PATCH v3 08/16] coresight: trbe: Allow driver to choose a different alignment
Date: Fri,  8 Oct 2021 19:28:58 +0100	[thread overview]
Message-ID: <20211008182906.1688009-9-suzuki.poulose@arm.com> (raw)
In-Reply-To: <20211008182906.1688009-1-suzuki.poulose@arm.com>

The TRBE hardware mandates a minimum alignment for the TRBPTR_EL1,
advertised via the TRBIDR_EL1. This is used by the driver to
align the buffer write head. This patch allows the driver to
choose a different alignment from that of the hardware, by
decoupling the alignment tracking. This will be useful for
working around errata.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Leo Yan <leo.yan@linaro.org>
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 drivers/hwtracing/coresight/coresight-trbe.c | 18 +++++++++++++++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c
index 58796ff425a4..f8c04c428780 100644
--- a/drivers/hwtracing/coresight/coresight-trbe.c
+++ b/drivers/hwtracing/coresight/coresight-trbe.c
@@ -67,8 +67,18 @@ struct trbe_buf {
 	struct trbe_cpudata *cpudata;
 };
 
+/*
+ * struct trbe_cpudata: TRBE instance specific data
+ * @trbe_flag		- TRBE dirty/access flag support
+ * @trbe_hw_align	- Actual TRBE alignment required for TRBPTR_EL1.
+ * @trbe_align		- Software alignment used for the TRBPTR_EL1,
+ * @cpu			- CPU this TRBE belongs to.
+ * @mode		- Mode of current operation. (perf/disabled)
+ * @drvdata		- TRBE specific drvdata
+ */
 struct trbe_cpudata {
 	bool trbe_flag;
+	u64 trbe_hw_align;
 	u64 trbe_align;
 	int cpu;
 	enum cs_mode mode;
@@ -875,7 +885,7 @@ static ssize_t align_show(struct device *dev, struct device_attribute *attr, cha
 {
 	struct trbe_cpudata *cpudata = dev_get_drvdata(dev);
 
-	return sprintf(buf, "%llx\n", cpudata->trbe_align);
+	return sprintf(buf, "%llx\n", cpudata->trbe_hw_align);
 }
 static DEVICE_ATTR_RO(align);
 
@@ -963,11 +973,13 @@ static void arm_trbe_probe_cpu(void *info)
 		goto cpu_clear;
 	}
 
-	cpudata->trbe_align = 1ULL << get_trbe_address_align(trbidr);
-	if (cpudata->trbe_align > SZ_2K) {
+	cpudata->trbe_hw_align = 1ULL << get_trbe_address_align(trbidr);
+	if (cpudata->trbe_hw_align > SZ_2K) {
 		pr_err("Unsupported alignment on cpu %d\n", cpu);
 		goto cpu_clear;
 	}
+
+	cpudata->trbe_align = cpudata->trbe_hw_align;
 	cpudata->trbe_flag = get_trbe_flag_update(trbidr);
 	cpudata->cpu = cpu;
 	cpudata->drvdata = drvdata;
-- 
2.25.4


WARNING: multiple messages have this Message-ID (diff)
From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, will@kernel.org,
	catalin.marinas@arm.com, mathieu.poirier@linaro.org,
	mike.leach@linaro.org, leo.yan@linaro.org,
	anshuman.khandual@arm.com, coresight@lists.linaro.org,
	maz@kernel.org, james.morse@arm.com, mark.rutland@arm.com,
	lcherian@marvell.com, Suzuki K Poulose <suzuki.poulose@arm.com>
Subject: [PATCH v3 08/16] coresight: trbe: Allow driver to choose a different alignment
Date: Fri,  8 Oct 2021 19:28:58 +0100	[thread overview]
Message-ID: <20211008182906.1688009-9-suzuki.poulose@arm.com> (raw)
In-Reply-To: <20211008182906.1688009-1-suzuki.poulose@arm.com>

The TRBE hardware mandates a minimum alignment for the TRBPTR_EL1,
advertised via the TRBIDR_EL1. This is used by the driver to
align the buffer write head. This patch allows the driver to
choose a different alignment from that of the hardware, by
decoupling the alignment tracking. This will be useful for
working around errata.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Leo Yan <leo.yan@linaro.org>
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 drivers/hwtracing/coresight/coresight-trbe.c | 18 +++++++++++++++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c
index 58796ff425a4..f8c04c428780 100644
--- a/drivers/hwtracing/coresight/coresight-trbe.c
+++ b/drivers/hwtracing/coresight/coresight-trbe.c
@@ -67,8 +67,18 @@ struct trbe_buf {
 	struct trbe_cpudata *cpudata;
 };
 
+/*
+ * struct trbe_cpudata: TRBE instance specific data
+ * @trbe_flag		- TRBE dirty/access flag support
+ * @trbe_hw_align	- Actual TRBE alignment required for TRBPTR_EL1.
+ * @trbe_align		- Software alignment used for the TRBPTR_EL1,
+ * @cpu			- CPU this TRBE belongs to.
+ * @mode		- Mode of current operation. (perf/disabled)
+ * @drvdata		- TRBE specific drvdata
+ */
 struct trbe_cpudata {
 	bool trbe_flag;
+	u64 trbe_hw_align;
 	u64 trbe_align;
 	int cpu;
 	enum cs_mode mode;
@@ -875,7 +885,7 @@ static ssize_t align_show(struct device *dev, struct device_attribute *attr, cha
 {
 	struct trbe_cpudata *cpudata = dev_get_drvdata(dev);
 
-	return sprintf(buf, "%llx\n", cpudata->trbe_align);
+	return sprintf(buf, "%llx\n", cpudata->trbe_hw_align);
 }
 static DEVICE_ATTR_RO(align);
 
@@ -963,11 +973,13 @@ static void arm_trbe_probe_cpu(void *info)
 		goto cpu_clear;
 	}
 
-	cpudata->trbe_align = 1ULL << get_trbe_address_align(trbidr);
-	if (cpudata->trbe_align > SZ_2K) {
+	cpudata->trbe_hw_align = 1ULL << get_trbe_address_align(trbidr);
+	if (cpudata->trbe_hw_align > SZ_2K) {
 		pr_err("Unsupported alignment on cpu %d\n", cpu);
 		goto cpu_clear;
 	}
+
+	cpudata->trbe_align = cpudata->trbe_hw_align;
 	cpudata->trbe_flag = get_trbe_flag_update(trbidr);
 	cpudata->cpu = cpu;
 	cpudata->drvdata = drvdata;
-- 
2.25.4


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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2021-10-08 18:29 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-08 18:28 [PATCH v3 00/16] arm64: Self-hosted trace related errata workarounds Suzuki K Poulose
2021-10-08 18:28 ` Suzuki K Poulose
2021-10-08 18:28 ` [PATCH v3 01/16] arm64: Add Neoverse-N2, Cortex-A710 CPU part definition Suzuki K Poulose
2021-10-08 18:28   ` Suzuki K Poulose
2021-10-08 18:28 ` [PATCH v3 02/16] arm64: errata: Add detection for TRBE overwrite in FILL mode Suzuki K Poulose
2021-10-08 18:28   ` Suzuki K Poulose
2021-10-08 18:28 ` [PATCH v3 03/16] arm64: errata: Add workaround for TSB flush failures Suzuki K Poulose
2021-10-08 18:28   ` Suzuki K Poulose
2021-10-11 10:20   ` Will Deacon
2021-10-11 10:20     ` Will Deacon
2021-10-08 18:28 ` [PATCH v3 04/16] arm64: errata: Add detection for TRBE write to out-of-range Suzuki K Poulose
2021-10-08 18:28   ` Suzuki K Poulose
2021-10-08 18:28 ` [PATCH v3 05/16] coresight: trbe: Add a helper to calculate the trace generated Suzuki K Poulose
2021-10-08 18:28   ` Suzuki K Poulose
2021-10-08 18:28 ` [PATCH v3 06/16] coresight: trbe: Add a helper to pad a given buffer area Suzuki K Poulose
2021-10-08 18:28   ` Suzuki K Poulose
2021-10-08 18:28 ` [PATCH v3 07/16] coresight: trbe: Decouple buffer base from the hardware base Suzuki K Poulose
2021-10-08 18:28   ` Suzuki K Poulose
2021-10-08 18:28 ` Suzuki K Poulose [this message]
2021-10-08 18:28   ` [PATCH v3 08/16] coresight: trbe: Allow driver to choose a different alignment Suzuki K Poulose
2021-10-08 18:28 ` [PATCH v3 09/16] coresight: trbe: Add infrastructure for Errata handling Suzuki K Poulose
2021-10-08 18:28   ` Suzuki K Poulose
2021-10-08 18:29 ` [PATCH v3 10/16] coresight: trbe: Workaround TRBE errata overwrite in FILL mode Suzuki K Poulose
2021-10-08 18:29   ` Suzuki K Poulose
2021-10-08 18:29 ` [PATCH v3 11/16] coresight: trbe: Add a helper to determine the minimum buffer size Suzuki K Poulose
2021-10-08 18:29   ` Suzuki K Poulose
2021-10-08 18:29 ` [PATCH v3 12/16] coresight: trbe: Make sure we have enough space Suzuki K Poulose
2021-10-08 18:29   ` Suzuki K Poulose
2021-10-08 18:29 ` [PATCH v3 13/16] coresight: trbe: Work around write to out of range Suzuki K Poulose
2021-10-08 18:29   ` Suzuki K Poulose
2021-10-08 18:29 ` [PATCH v3 14/16] arm64: errata: Advertise workaround for TRBE overwrite in FILL mode Suzuki K Poulose
2021-10-08 18:29   ` Suzuki K Poulose
2021-10-08 18:29 ` [PATCH v3 15/16] arm64: errata: Advertise the workaround for TSB flush failures Suzuki K Poulose
2021-10-08 18:29   ` Suzuki K Poulose
2021-10-11 10:18   ` Will Deacon
2021-10-11 10:18     ` Will Deacon
2021-10-11 12:32     ` Suzuki K Poulose
2021-10-11 12:32       ` Suzuki K Poulose
2021-10-08 18:29 ` [PATCH v3 16/16] arm64: errata: Advertise TRBE erratum workaround for write to out-of-range address Suzuki K Poulose
2021-10-08 18:29   ` Suzuki K Poulose

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