All of lore.kernel.org
 help / color / mirror / Atom feed
From: "José Roberto de Souza" <jose.souza@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: "José Roberto de Souza" <jose.souza@intel.com>
Subject: [Intel-gfx] [PATCH] drm/i915/icl: Fix read of memory frequency
Date: Fri,  8 Oct 2021 13:58:55 -0700	[thread overview]
Message-ID: <20211008205855.36778-1-jose.souza@intel.com> (raw)

All display 9 and display 10 platforms has only 4 bits for the memory
frequency but display 11 platforms it changes to 8 bits.

Display 9 platforms has another register in bits 7:4 that prevents us
to have a single mask.
Also adding new mask with the current name in CRWebViewer, not
sure why current mask is named like this.

Fixes: f8112cb9574b ("drm/i915/gen11+: Only load DRAM information from pcode")
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h   | 1 +
 drivers/gpu/drm/i915/intel_dram.c | 7 +++++--
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a897f4abea0c3..041f7dc9e0d94 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11148,6 +11148,7 @@ enum skl_power_gate {
 #define SKL_MEMORY_FREQ_MULTIPLIER_HZ		266666666
 #define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5E04)
 #define  SKL_REQ_DATA_MASK			(0xF << 0)
+#define  ICL_FREQ_MASK				(0xFF << 0)
 #define  DG1_GEAR_TYPE				REG_BIT(16)
 
 #define SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5000)
diff --git a/drivers/gpu/drm/i915/intel_dram.c b/drivers/gpu/drm/i915/intel_dram.c
index 30a0cab5eff46..558589b1202d6 100644
--- a/drivers/gpu/drm/i915/intel_dram.c
+++ b/drivers/gpu/drm/i915/intel_dram.c
@@ -257,8 +257,11 @@ skl_get_dram_info(struct drm_i915_private *i915)
 
 	val = intel_uncore_read(&i915->uncore,
 				SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
-	mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *
-				    SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
+	if (DISPLAY_VER(i915) == 11)
+		val &= ICL_FREQ_MASK;
+	else
+		val &= SKL_REQ_DATA_MASK;
+	mem_freq_khz = DIV_ROUND_UP(val * SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
 
 	if (dram_info->num_channels * mem_freq_khz == 0) {
 		drm_info(&i915->drm,
-- 
2.33.0


             reply	other threads:[~2021-10-08 20:53 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-08 20:58 José Roberto de Souza [this message]
2021-10-08 21:18 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/icl: Fix read of memory frequency Patchwork
2021-10-08 21:47 ` [Intel-gfx] [PATCH] " Souza, Jose
2021-10-08 21:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2021-10-09  0:59 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-10-12 21:20 ` [Intel-gfx] [PATCH] " Matt Roper
2021-10-12 21:23   ` Souza, Jose
2021-10-12 21:40     ` Matt Roper

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20211008205855.36778-1-jose.souza@intel.com \
    --to=jose.souza@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.