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* [net-next PATCH v3 00/13] Multiple improvement for qca8337 switch
@ 2021-10-10  1:55 Ansuel Smith
  2021-10-10  1:55 ` [net-next PATCH v3 01/13] net: dsa: qca8k: add mac_power_sel support Ansuel Smith
                   ` (12 more replies)
  0 siblings, 13 replies; 16+ messages in thread
From: Ansuel Smith @ 2021-10-10  1:55 UTC (permalink / raw)
  To: Andrew Lunn, Vivien Didelot, Florian Fainelli, Vladimir Oltean,
	David S. Miller, Jakub Kicinski, Rob Herring, Russell King,
	netdev, devicetree, linux-kernel
  Cc: Ansuel Smith

This series is the final step of a long process of porting 80+ devices
to use the new qca8k driver instead of the hacky qca one based on never
merged swconfig platform.
Some background to justify all these additions.
QCA used a special binding to declare raw initval to set the swich. I
made a script to convert all these magic values and convert 80+ dts and
scan all the needed "unsupported regs". We find a baseline where we
manage to find the common and used regs so in theory hopefully we don't
have to add anymore things.
We discovered lots of things with this, especially about how differently
qca8327 works compared to qca8337.

In short, we found that qca8327 have some problem with suspend/resume for
their internal phy. It instead sets some dedicated regs that suspend the
phy without setting the standard bit. First 4 patch are to fix this.
There is also a patch about preferring master. This is directly from the
original driver and it seems to be needed to prevent some problem with
the pause frame.

Every ipq806x target sets the mac power sel and this specific reg
regulates the output voltage of the regulator. Without this some
instability can occur.

Some configuration (for some reason) swap mac6 with mac0. We add support
for this.
Also, we discovered that some device doesn't work at all with pll enabled
for sgmii line. In the original code this was based on the switch
revision. In later revision the pll regs were decided based on the switch
type (disabled for qca8327 and enabled for qca8337) but still some
device had that disabled in the initval regs.
Considering we found at least one qca8337 device that required pll
disabled to work (no traffic problem) we decided to introduce a binding
to enable pll and set it only with that.

Lastly, we add support for led open drain that require the power-on-sel
to set. Also, some device have only the power-on-sel set in the initval
so we add also support for that. This is needed for the correct function
of the switch leds.
Qca8327 have a special reg in the pws regs that set it to a reduced
48pin layout. This is needed or the switch doesn't work.

These are all the special configuration we find on all these devices that
are from various targets. Mostly ath79, ipq806x and bcm53xx.

Changes v3:
- Drop phy patches (proposed separateley)
- Drop special pwr binding. Rework to ipq806x specific
- Better describe compatible and add serial print on switch chip
- Drop mac exchange. Rework falling edge and move it to mac_config
- Add support for port 6 cpu port. Drop hardcoded cpu port to port0
- Improve port stability with sgmii. QCA source have intenal delay also
  for sgmii
- Add warning with pll enabled on wrong configuration

Changes v2:
- Reword Documentation patch to dt-bindings
- Propose first 2 phy patch to net
- Better describe and add hint on how to use all the new
  bindings 
- Rework delay scan function and move to phylink mac_config
- Drop package48 wrong binding
- Introduce support for qca8328 switch
- Fix wrong binding name power-on-sel
- Return error on wrong config with led open drain and 
  ignore-power-on-sel not set

Ansuel Smith (13):
  net: dsa: qca8k: add mac_power_sel support
  net: dsa: qca8k: add support for sgmii falling edge
  dt-bindings: net: dsa: qca8k: Add MAC swap and clock phase properties
  drivers: net: dsa: qca8k: add support for cpu port 6
  dt-bindings: net: dsa: qca8k: Document support for CPU port 6
  net: dsa: qca8k: move rgmii delay detection to phylink mac_config
  net: dsa: qca8k: add explicit SGMII PLL enable
  dt-bindings: net: dsa: qca8k: Document qca,sgmii-enable-pll
  drivers: net: dsa: qca8k: add support for pws config reg
  dt-bindings: net: dsa: qca8k: document open drain binding
  drivers: net: dsa: qca8k: add support for QCA8328
  dt-bindings: net: dsa: qca8k: document support for qca8328
  drivers: net: dsa: qca8k: set internal delay also for sgmii

 .../devicetree/bindings/net/dsa/qca8k.txt     |  38 ++-
 drivers/net/dsa/qca8k.c                       | 285 +++++++++++++-----
 drivers/net/dsa/qca8k.h                       |  21 +-
 3 files changed, 262 insertions(+), 82 deletions(-)

-- 
2.32.0


^ permalink raw reply	[flat|nested] 16+ messages in thread
* [net-next PATCH v3 01/13] net: dsa: qca8k: add mac_power_sel support
  2021-10-10  1:55 [net-next PATCH v3 00/13] Multiple improvement for qca8337 switch Ansuel Smith
@ 2021-10-10  1:55 ` Ansuel Smith
  2021-10-10  1:55 ` [net-next PATCH v3 02/13] net: dsa: qca8k: add support for sgmii falling edge Ansuel Smith
                   ` (11 subsequent siblings)
  12 siblings, 0 replies; 16+ messages in thread
From: Ansuel Smith @ 2021-10-10  1:55 UTC (permalink / raw)
  To: Andrew Lunn, Vivien Didelot, Florian Fainelli, Vladimir Oltean,
	David S. Miller, Jakub Kicinski, Rob Herring, Russell King,
	netdev, devicetree, linux-kernel
  Cc: Ansuel Smith

Add missing mac power sel support needed for ipq8064/5 SoC that require
1.8v for the internal regulator port instead of the default 1.5v.
If other device needs this, consider adding a dedicated binding to
support this.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
 drivers/net/dsa/qca8k.c | 31 +++++++++++++++++++++++++++++++
 drivers/net/dsa/qca8k.h |  5 +++++
 2 files changed, 36 insertions(+)

diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
index bda5a9bf4f52..a892b897cd0d 100644
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -950,6 +950,33 @@ qca8k_setup_of_rgmii_delay(struct qca8k_priv *priv)
 	return 0;
 }
 
+static int
+qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv)
+{
+	u32 mask = 0;
+	int ret = 0;
+
+	/* SoC specific settings for ipq8064.
+	 * If more device require this consider adding
+	 * a dedicated binding.
+	 */
+	if (of_machine_is_compatible("qcom,ipq8064"))
+		mask |= QCA8K_MAC_PWR_RGMII0_1_8V;
+
+	/* SoC specific settings for ipq8065 */
+	if (of_machine_is_compatible("qcom,ipq8065"))
+		mask |= QCA8K_MAC_PWR_RGMII1_1_8V;
+
+	if (mask) {
+		ret = qca8k_rmw(priv, QCA8K_REG_MAC_PWR_SEL,
+				QCA8K_MAC_PWR_RGMII0_1_8V |
+				QCA8K_MAC_PWR_RGMII1_1_8V,
+				mask);
+	}
+
+	return ret;
+}
+
 static int
 qca8k_setup(struct dsa_switch *ds)
 {
@@ -979,6 +1006,10 @@ qca8k_setup(struct dsa_switch *ds)
 	if (ret)
 		return ret;
 
+	ret = qca8k_setup_mac_pwr_sel(priv);
+	if (ret)
+		return ret;
+
 	/* Enable CPU Port */
 	ret = qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,
 			    QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h
index ed3b05ad6745..fc7db94cc0c9 100644
--- a/drivers/net/dsa/qca8k.h
+++ b/drivers/net/dsa/qca8k.h
@@ -100,6 +100,11 @@
 #define   QCA8K_SGMII_MODE_CTRL_PHY			(1 << 22)
 #define   QCA8K_SGMII_MODE_CTRL_MAC			(2 << 22)
 
+/* MAC_PWR_SEL registers */
+#define QCA8K_REG_MAC_PWR_SEL				0x0e4
+#define   QCA8K_MAC_PWR_RGMII1_1_8V			BIT(18)
+#define   QCA8K_MAC_PWR_RGMII0_1_8V			BIT(19)
+
 /* EEE control registers */
 #define QCA8K_REG_EEE_CTRL				0x100
 #define  QCA8K_REG_EEE_CTRL_LPI_EN(_i)			((_i + 1) * 2)
-- 
2.32.0


^ permalink raw reply related	[flat|nested] 16+ messages in thread
* [net-next PATCH v3 02/13] net: dsa: qca8k: add support for sgmii falling edge
  2021-10-10  1:55 [net-next PATCH v3 00/13] Multiple improvement for qca8337 switch Ansuel Smith
  2021-10-10  1:55 ` [net-next PATCH v3 01/13] net: dsa: qca8k: add mac_power_sel support Ansuel Smith
@ 2021-10-10  1:55 ` Ansuel Smith
  2021-10-10  6:12     ` kernel test robot
  2021-10-10  1:55 ` [net-next PATCH v3 03/13] dt-bindings: net: dsa: qca8k: Add MAC swap and clock phase properties Ansuel Smith
                   ` (10 subsequent siblings)
  12 siblings, 1 reply; 16+ messages in thread
From: Ansuel Smith @ 2021-10-10  1:55 UTC (permalink / raw)
  To: Andrew Lunn, Vivien Didelot, Florian Fainelli, Vladimir Oltean,
	David S. Miller, Jakub Kicinski, Rob Herring, Russell King,
	netdev, devicetree, linux-kernel
  Cc: Ansuel Smith, Matthew Hagan

Add support for this in the qca8k driver. Also add support for SGMII
rx/tx clock falling edge. This is only present for pad0, pad5 and
pad6 have these bit reserved from Documentation. Add a comment that this
is hardcoded to PAD0 as qca8327/28/34/37 have an unique sgmii line and
setting falling in port0 applies to both configuration with sgmii used
for port0 or port6.

Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
 drivers/net/dsa/qca8k.c | 25 +++++++++++++++++++++++++
 drivers/net/dsa/qca8k.h |  3 +++
 2 files changed, 28 insertions(+)

diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
index a892b897cd0d..863eeac6eace 100644
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -1172,6 +1172,7 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
 			 const struct phylink_link_state *state)
 {
 	struct qca8k_priv *priv = ds->priv;
+	struct dsa_port *dp;
 	u32 reg, val;
 	int ret;
 
@@ -1240,6 +1241,8 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
 		break;
 	case PHY_INTERFACE_MODE_SGMII:
 	case PHY_INTERFACE_MODE_1000BASEX:
+		dp = dsa_to_port(ds, port);
+
 		/* Enable SGMII on the port */
 		qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
 
@@ -1274,6 +1277,28 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
 		}
 
 		qca8k_write(priv, QCA8K_REG_SGMII_CTRL, val);
+
+		/* For qca8327/qca8328/qca8334/qca8338 sgmii is unique and
+		 * falling edge is set writing in the PORT0 PAD reg
+		 */
+		if (priv->switch_id == PHY_ID_QCA8327 ||
+		    priv->switch_id == PHY_ID_QCA8337)
+			reg = QCA8K_REG_PORT0_PAD_CTRL;
+
+		val = 0;
+
+		/* SGMII Clock phase configuration */
+		if (of_property_read_bool(dp->dn, "qca,sgmii-rxclk-falling-edge"))
+			val |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE;
+
+		if (of_property_read_bool(dp->dn, "qca,sgmii-txclk-falling-edge"))
+			val |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE;
+
+		if (val)
+			ret = qca8k_rmw(priv, reg,
+					QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE |
+					QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE,
+					val);
 		break;
 	default:
 		dev_err(ds->dev, "xMII mode %s not supported for port %d\n",
diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h
index fc7db94cc0c9..3fded69a6839 100644
--- a/drivers/net/dsa/qca8k.h
+++ b/drivers/net/dsa/qca8k.h
@@ -35,6 +35,9 @@
 #define   QCA8K_MASK_CTRL_DEVICE_ID_MASK		GENMASK(15, 8)
 #define   QCA8K_MASK_CTRL_DEVICE_ID(x)			((x) >> 8)
 #define QCA8K_REG_PORT0_PAD_CTRL			0x004
+#define   QCA8K_PORT0_PAD_CTRL_MAC06_EXCHG		BIT(31)
+#define   QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE	BIT(19)
+#define   QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE	BIT(18)
 #define QCA8K_REG_PORT5_PAD_CTRL			0x008
 #define QCA8K_REG_PORT6_PAD_CTRL			0x00c
 #define   QCA8K_PORT_PAD_RGMII_EN			BIT(26)
-- 
2.32.0


^ permalink raw reply related	[flat|nested] 16+ messages in thread
* [net-next PATCH v3 03/13] dt-bindings: net: dsa: qca8k: Add MAC swap and clock phase properties
  2021-10-10  1:55 [net-next PATCH v3 00/13] Multiple improvement for qca8337 switch Ansuel Smith
  2021-10-10  1:55 ` [net-next PATCH v3 01/13] net: dsa: qca8k: add mac_power_sel support Ansuel Smith
  2021-10-10  1:55 ` [net-next PATCH v3 02/13] net: dsa: qca8k: add support for sgmii falling edge Ansuel Smith
@ 2021-10-10  1:55 ` Ansuel Smith
  2021-10-10  1:55 ` [net-next PATCH v3 04/13] drivers: net: dsa: qca8k: add support for cpu port 6 Ansuel Smith
                   ` (9 subsequent siblings)
  12 siblings, 0 replies; 16+ messages in thread
From: Ansuel Smith @ 2021-10-10  1:55 UTC (permalink / raw)
  To: Andrew Lunn, Vivien Didelot, Florian Fainelli, Vladimir Oltean,
	David S. Miller, Jakub Kicinski, Rob Herring, Russell King,
	netdev, devicetree, linux-kernel
  Cc: Ansuel Smith, Matthew Hagan

Add names and descriptions of additional PORT0_PAD_CTRL properties.
qca,sgmii-(rx|tx)clk-falling-edge are for setting the respective clock
phase to failling edge.

Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
 Documentation/devicetree/bindings/net/dsa/qca8k.txt | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/dsa/qca8k.txt b/Documentation/devicetree/bindings/net/dsa/qca8k.txt
index 8c73f67c43ca..cc214e655442 100644
--- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt
+++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt
@@ -37,6 +37,10 @@ A CPU port node has the following optional node:
                           managed entity. See
                           Documentation/devicetree/bindings/net/fixed-link.txt
                           for details.
+- qca,sgmii-rxclk-falling-edge: Set the receive clock phase to falling edge.
+                                Mostly used in qca8327 with CPU port 0 set to
+                                sgmii.
+- qca,sgmii-txclk-falling-edge: Set the transmit clock phase to falling edge.
 
 For QCA8K the 'fixed-link' sub-node supports only the following properties:
 
-- 
2.32.0


^ permalink raw reply related	[flat|nested] 16+ messages in thread
* [net-next PATCH v3 04/13] drivers: net: dsa: qca8k: add support for cpu port 6
  2021-10-10  1:55 [net-next PATCH v3 00/13] Multiple improvement for qca8337 switch Ansuel Smith
                   ` (2 preceding siblings ...)
  2021-10-10  1:55 ` [net-next PATCH v3 03/13] dt-bindings: net: dsa: qca8k: Add MAC swap and clock phase properties Ansuel Smith
@ 2021-10-10  1:55 ` Ansuel Smith
  2021-10-10  1:55 ` [net-next PATCH v3 05/13] dt-bindings: net: dsa: qca8k: Document support for CPU " Ansuel Smith
                   ` (8 subsequent siblings)
  12 siblings, 0 replies; 16+ messages in thread
From: Ansuel Smith @ 2021-10-10  1:55 UTC (permalink / raw)
  To: Andrew Lunn, Vivien Didelot, Florian Fainelli, Vladimir Oltean,
	David S. Miller, Jakub Kicinski, Rob Herring, Russell King,
	netdev, devicetree, linux-kernel
  Cc: Ansuel Smith

Currently CPU port is always hardcoded to port 0. This switch have 2 CPU
port. The original intention of this driver seems to be use the
mac06_exchange bit to swap MAC0 with MAC6 in the strange configuration
where device have connected only the CPU port 6. To skip the
introduction of a new binding, rework the driver to address the
secondary CPU port as primary and drop any reference of hardcoded port.
With configuration of mac06 exchange, just skip the definition of port0
and define the CPU port as a secondary. The driver will autoconfigure
the switch to use that as the primary CPU port.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
 drivers/net/dsa/qca8k.c | 50 +++++++++++++++++++++++++++++------------
 drivers/net/dsa/qca8k.h |  2 --
 2 files changed, 36 insertions(+), 16 deletions(-)

diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
index 863eeac6eace..91334fa23183 100644
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -977,17 +977,34 @@ qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv)
 	return ret;
 }
 
+static int qca8k_find_cpu_port(struct dsa_switch *ds)
+{
+	struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
+
+	/* Find the connected cpu port. Valid port are 0 or 6 */
+	if (dsa_is_cpu_port(ds, 0))
+		return 0;
+
+	dev_dbg(priv->dev, "port 0 is not the CPU port. Checking port 6");
+
+	if (dsa_is_cpu_port(ds, 6))
+		return 6;
+
+	return -EINVAL;
+}
+
 static int
 qca8k_setup(struct dsa_switch *ds)
 {
 	struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
+	u8 cpu_port;
 	int ret, i;
 	u32 mask;
 
-	/* Make sure that port 0 is the cpu port */
-	if (!dsa_is_cpu_port(ds, 0)) {
-		dev_err(priv->dev, "port 0 is not the CPU port");
-		return -EINVAL;
+	cpu_port = qca8k_find_cpu_port(ds);
+	if (cpu_port < 0) {
+		dev_err(priv->dev, "No cpu port configured in both cpu port0 and port6");
+		return cpu_port;
 	}
 
 	mutex_init(&priv->reg_mutex);
@@ -1024,7 +1041,7 @@ qca8k_setup(struct dsa_switch *ds)
 		dev_warn(priv->dev, "mib init failed");
 
 	/* Enable QCA header mode on the cpu port */
-	ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(QCA8K_CPU_PORT),
+	ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(cpu_port),
 			  QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S |
 			  QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S);
 	if (ret) {
@@ -1046,10 +1063,10 @@ qca8k_setup(struct dsa_switch *ds)
 
 	/* Forward all unknown frames to CPU port for Linux processing */
 	ret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
-			  BIT(0) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S |
-			  BIT(0) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S |
-			  BIT(0) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S |
-			  BIT(0) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S);
+			  BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S |
+			  BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S |
+			  BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S |
+			  BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S);
 	if (ret)
 		return ret;
 
@@ -1057,7 +1074,7 @@ qca8k_setup(struct dsa_switch *ds)
 	for (i = 0; i < QCA8K_NUM_PORTS; i++) {
 		/* CPU port gets connected to all user ports of the switch */
 		if (dsa_is_cpu_port(ds, i)) {
-			ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT),
+			ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(cpu_port),
 					QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds));
 			if (ret)
 				return ret;
@@ -1069,7 +1086,7 @@ qca8k_setup(struct dsa_switch *ds)
 
 			ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
 					QCA8K_PORT_LOOKUP_MEMBER,
-					BIT(QCA8K_CPU_PORT));
+					BIT(cpu_port));
 			if (ret)
 				return ret;
 
@@ -1578,9 +1595,12 @@ static int
 qca8k_port_bridge_join(struct dsa_switch *ds, int port, struct net_device *br)
 {
 	struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
-	int port_mask = BIT(QCA8K_CPU_PORT);
+	int port_mask, cpu_port;
 	int i, ret;
 
+	cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
+	port_mask = BIT(cpu_port);
+
 	for (i = 1; i < QCA8K_NUM_PORTS; i++) {
 		if (dsa_to_port(ds, i)->bridge_dev != br)
 			continue;
@@ -1607,7 +1627,9 @@ static void
 qca8k_port_bridge_leave(struct dsa_switch *ds, int port, struct net_device *br)
 {
 	struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
-	int i;
+	int cpu_port, i;
+
+	cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
 
 	for (i = 1; i < QCA8K_NUM_PORTS; i++) {
 		if (dsa_to_port(ds, i)->bridge_dev != br)
@@ -1624,7 +1646,7 @@ qca8k_port_bridge_leave(struct dsa_switch *ds, int port, struct net_device *br)
 	 * this port
 	 */
 	qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
-		  QCA8K_PORT_LOOKUP_MEMBER, BIT(QCA8K_CPU_PORT));
+		  QCA8K_PORT_LOOKUP_MEMBER, BIT(cpu_port));
 }
 
 static int
diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h
index 3fded69a6839..5df0f0ef6526 100644
--- a/drivers/net/dsa/qca8k.h
+++ b/drivers/net/dsa/qca8k.h
@@ -24,8 +24,6 @@
 
 #define QCA8K_NUM_FDB_RECORDS				2048
 
-#define QCA8K_CPU_PORT					0
-
 #define QCA8K_PORT_VID_DEF				1
 
 /* Global control registers */
-- 
2.32.0


^ permalink raw reply related	[flat|nested] 16+ messages in thread
* [net-next PATCH v3 05/13] dt-bindings: net: dsa: qca8k: Document support for CPU port 6
  2021-10-10  1:55 [net-next PATCH v3 00/13] Multiple improvement for qca8337 switch Ansuel Smith
                   ` (3 preceding siblings ...)
  2021-10-10  1:55 ` [net-next PATCH v3 04/13] drivers: net: dsa: qca8k: add support for cpu port 6 Ansuel Smith
@ 2021-10-10  1:55 ` Ansuel Smith
  2021-10-10  1:55 ` [net-next PATCH v3 06/13] net: dsa: qca8k: move rgmii delay detection to phylink mac_config Ansuel Smith
                   ` (7 subsequent siblings)
  12 siblings, 0 replies; 16+ messages in thread
From: Ansuel Smith @ 2021-10-10  1:55 UTC (permalink / raw)
  To: Andrew Lunn, Vivien Didelot, Florian Fainelli, Vladimir Oltean,
	David S. Miller, Jakub Kicinski, Rob Herring, Russell King,
	netdev, devicetree, linux-kernel
  Cc: Ansuel Smith

The switch now support CPU port to be set 6 instead of be hardcoded to
0. Document support for it and describe logic selection.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
 Documentation/devicetree/bindings/net/dsa/qca8k.txt | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/net/dsa/qca8k.txt b/Documentation/devicetree/bindings/net/dsa/qca8k.txt
index cc214e655442..aeb206556f54 100644
--- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt
+++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt
@@ -29,7 +29,11 @@ the mdio MASTER is used as communication.
 Don't use mixed external and internal mdio-bus configurations, as this is
 not supported by the hardware.
 
-The CPU port of this switch is always port 0.
+This switch support 2 CPU port. Normally and advised configuration is with
+CPU port set to port 0. It is also possible to set the CPU port to port 6
+if the device requires it. The driver will configure the switch to the defined
+port. With both CPU port declared the first CPU port is selected as primary
+and the secondary CPU ignored.
 
 A CPU port node has the following optional node:
 
-- 
2.32.0


^ permalink raw reply related	[flat|nested] 16+ messages in thread
* [net-next PATCH v3 06/13] net: dsa: qca8k: move rgmii delay detection to phylink mac_config
  2021-10-10  1:55 [net-next PATCH v3 00/13] Multiple improvement for qca8337 switch Ansuel Smith
                   ` (4 preceding siblings ...)
  2021-10-10  1:55 ` [net-next PATCH v3 05/13] dt-bindings: net: dsa: qca8k: Document support for CPU " Ansuel Smith
@ 2021-10-10  1:55 ` Ansuel Smith
  2021-10-10  1:55 ` [net-next PATCH v3 07/13] net: dsa: qca8k: add explicit SGMII PLL enable Ansuel Smith
                   ` (6 subsequent siblings)
  12 siblings, 0 replies; 16+ messages in thread
From: Ansuel Smith @ 2021-10-10  1:55 UTC (permalink / raw)
  To: Andrew Lunn, Vivien Didelot, Florian Fainelli, Vladimir Oltean,
	David S. Miller, Jakub Kicinski, Rob Herring, Russell King,
	netdev, devicetree, linux-kernel
  Cc: Ansuel Smith

Future proof commit. This switch have 2 CPU port and one valid
configuration is first CPU port set to sgmii and second CPU port set to
regmii-id. The current implementation detects delay only for CPU port
zero set to rgmii and doesn't count any delay set in a secondary CPU
port. Drop the current delay scan function and move it to the phylink
mac_config to generilize and implicitly add support for secondary CPU
port set to rgmii-id.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
 drivers/net/dsa/qca8k.c | 121 +++++++++++++++-------------------------
 drivers/net/dsa/qca8k.h |   2 -
 2 files changed, 44 insertions(+), 79 deletions(-)

diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
index 91334fa23183..043980a5db7f 100644
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -888,68 +888,6 @@ qca8k_setup_mdio_bus(struct qca8k_priv *priv)
 	return 0;
 }
 
-static int
-qca8k_setup_of_rgmii_delay(struct qca8k_priv *priv)
-{
-	struct device_node *port_dn;
-	phy_interface_t mode;
-	struct dsa_port *dp;
-	u32 val;
-
-	/* CPU port is already checked */
-	dp = dsa_to_port(priv->ds, 0);
-
-	port_dn = dp->dn;
-
-	/* Check if port 0 is set to the correct type */
-	of_get_phy_mode(port_dn, &mode);
-	if (mode != PHY_INTERFACE_MODE_RGMII_ID &&
-	    mode != PHY_INTERFACE_MODE_RGMII_RXID &&
-	    mode != PHY_INTERFACE_MODE_RGMII_TXID) {
-		return 0;
-	}
-
-	switch (mode) {
-	case PHY_INTERFACE_MODE_RGMII_ID:
-	case PHY_INTERFACE_MODE_RGMII_RXID:
-		if (of_property_read_u32(port_dn, "rx-internal-delay-ps", &val))
-			val = 2;
-		else
-			/* Switch regs accept value in ns, convert ps to ns */
-			val = val / 1000;
-
-		if (val > QCA8K_MAX_DELAY) {
-			dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ns, setting to the max value");
-			val = 3;
-		}
-
-		priv->rgmii_rx_delay = val;
-		/* Stop here if we need to check only for rx delay */
-		if (mode != PHY_INTERFACE_MODE_RGMII_ID)
-			break;
-
-		fallthrough;
-	case PHY_INTERFACE_MODE_RGMII_TXID:
-		if (of_property_read_u32(port_dn, "tx-internal-delay-ps", &val))
-			val = 1;
-		else
-			/* Switch regs accept value in ns, convert ps to ns */
-			val = val / 1000;
-
-		if (val > QCA8K_MAX_DELAY) {
-			dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ns, setting to the max value");
-			val = 3;
-		}
-
-		priv->rgmii_tx_delay = val;
-		break;
-	default:
-		return 0;
-	}
-
-	return 0;
-}
-
 static int
 qca8k_setup_mac_pwr_sel(struct qca8k_priv *priv)
 {
@@ -1019,10 +957,6 @@ qca8k_setup(struct dsa_switch *ds)
 	if (ret)
 		return ret;
 
-	ret = qca8k_setup_of_rgmii_delay(priv);
-	if (ret)
-		return ret;
-
 	ret = qca8k_setup_mac_pwr_sel(priv);
 	if (ret)
 		return ret;
@@ -1190,7 +1124,7 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
 {
 	struct qca8k_priv *priv = ds->priv;
 	struct dsa_port *dp;
-	u32 reg, val;
+	u32 reg, val, delay;
 	int ret;
 
 	switch (port) {
@@ -1241,17 +1175,50 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
 	case PHY_INTERFACE_MODE_RGMII_ID:
 	case PHY_INTERFACE_MODE_RGMII_TXID:
 	case PHY_INTERFACE_MODE_RGMII_RXID:
-		/* RGMII_ID needs internal delay. This is enabled through
-		 * PORT5_PAD_CTRL for all ports, rather than individual port
-		 * registers
+		dp = dsa_to_port(ds, port);
+		val = QCA8K_PORT_PAD_RGMII_EN;
+
+		if (state->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+		    state->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
+			if (of_property_read_u32(dp->dn, "tx-internal-delay-ps", &delay))
+				delay = 1;
+			else
+				/* Switch regs accept value in ns, convert ps to ns */
+				delay = delay / 1000;
+
+			if (delay > QCA8K_MAX_DELAY) {
+				dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ns, setting to the max value");
+				delay = 3;
+			}
+
+			val |= QCA8K_PORT_PAD_RGMII_TX_DELAY(delay) |
+			       QCA8K_PORT_PAD_RGMII_TX_DELAY_EN;
+		}
+
+		if (state->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+		    state->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
+			if (of_property_read_u32(dp->dn, "rx-internal-delay-ps", &delay))
+				delay = 2;
+			else
+				/* Switch regs accept value in ns, convert ps to ns */
+				delay = delay / 1000;
+
+			if (delay > QCA8K_MAX_DELAY) {
+				dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ns, setting to the max value");
+				delay = 3;
+			}
+
+			val |= QCA8K_PORT_PAD_RGMII_RX_DELAY(delay) |
+			       QCA8K_PORT_PAD_RGMII_RX_DELAY_EN;
+		}
+
+		/* Set RGMII delay based on the selected values */
+		qca8k_write(priv, reg, val);
+
+		/* QCA8337 requires to set rgmii rx delay for all ports.
+		 * This is enabled through PORT5_PAD_CTRL for all ports,
+		 * rather than individual port registers.
 		 */
-		qca8k_write(priv, reg,
-			    QCA8K_PORT_PAD_RGMII_EN |
-			    QCA8K_PORT_PAD_RGMII_TX_DELAY(priv->rgmii_tx_delay) |
-			    QCA8K_PORT_PAD_RGMII_RX_DELAY(priv->rgmii_rx_delay) |
-			    QCA8K_PORT_PAD_RGMII_TX_DELAY_EN |
-			    QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
-		/* QCA8337 requires to set rgmii rx delay */
 		if (priv->switch_id == QCA8K_ID_QCA8337)
 			qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
 				    QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h
index 5df0f0ef6526..a790b27bc310 100644
--- a/drivers/net/dsa/qca8k.h
+++ b/drivers/net/dsa/qca8k.h
@@ -259,8 +259,6 @@ struct qca8k_match_data {
 struct qca8k_priv {
 	u8 switch_id;
 	u8 switch_revision;
-	u8 rgmii_tx_delay;
-	u8 rgmii_rx_delay;
 	bool legacy_phy_port_mapping;
 	struct regmap *regmap;
 	struct mii_bus *bus;
-- 
2.32.0


^ permalink raw reply related	[flat|nested] 16+ messages in thread
* [net-next PATCH v3 07/13] net: dsa: qca8k: add explicit SGMII PLL enable
  2021-10-10  1:55 [net-next PATCH v3 00/13] Multiple improvement for qca8337 switch Ansuel Smith
                   ` (5 preceding siblings ...)
  2021-10-10  1:55 ` [net-next PATCH v3 06/13] net: dsa: qca8k: move rgmii delay detection to phylink mac_config Ansuel Smith
@ 2021-10-10  1:55 ` Ansuel Smith
  2021-10-10  1:55 ` [net-next PATCH v3 08/13] dt-bindings: net: dsa: qca8k: Document qca,sgmii-enable-pll Ansuel Smith
                   ` (5 subsequent siblings)
  12 siblings, 0 replies; 16+ messages in thread
From: Ansuel Smith @ 2021-10-10  1:55 UTC (permalink / raw)
  To: Andrew Lunn, Vivien Didelot, Florian Fainelli, Vladimir Oltean,
	David S. Miller, Jakub Kicinski, Rob Herring, Russell King,
	netdev, devicetree, linux-kernel
  Cc: Ansuel Smith

Support enabling PLL on the SGMII CPU port. Some device require this
special configuration or no traffic is transmitted and the switch
doesn't work at all. A dedicated binding is added to the CPU node
port to apply the correct reg on mac config.
Fail to correctly configure sgmii with qca8327 switch and warn if pll is
used on qca8337 with a revision greater than 1.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
 drivers/net/dsa/qca8k.c | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
index 043980a5db7f..b73b92ebd72e 100644
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -1245,8 +1245,20 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
 		if (ret)
 			return;
 
-		val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |
-			QCA8K_SGMII_EN_TX | QCA8K_SGMII_EN_SD;
+		val |= QCA8K_SGMII_EN_SD;
+
+		if (of_property_read_bool(dp->dn, "qca,sgmii-enable-pll")) {
+			if (priv->switch_id == QCA8K_ID_QCA8327) {
+				dev_err(priv->dev, "SGMII PLL should NOT be enabled for qca8327. Aborting enabling");
+				return;
+			}
+
+			if (priv->switch_revision < 2)
+				dev_warn(priv->dev, "SGMII PLL should NOT be enabled for qca8337 with revision 2 or more.");
+
+			val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |
+			       QCA8K_SGMII_EN_TX;
+		}
 
 		if (dsa_is_cpu_port(ds, port)) {
 			/* CPU port, we're talking to the CPU MAC, be a PHY */
-- 
2.32.0


^ permalink raw reply related	[flat|nested] 16+ messages in thread
* [net-next PATCH v3 08/13] dt-bindings: net: dsa: qca8k: Document qca,sgmii-enable-pll
  2021-10-10  1:55 [net-next PATCH v3 00/13] Multiple improvement for qca8337 switch Ansuel Smith
                   ` (6 preceding siblings ...)
  2021-10-10  1:55 ` [net-next PATCH v3 07/13] net: dsa: qca8k: add explicit SGMII PLL enable Ansuel Smith
@ 2021-10-10  1:55 ` Ansuel Smith
  2021-10-10  1:55 ` [net-next PATCH v3 09/13] drivers: net: dsa: qca8k: add support for pws config reg Ansuel Smith
                   ` (4 subsequent siblings)
  12 siblings, 0 replies; 16+ messages in thread
From: Ansuel Smith @ 2021-10-10  1:55 UTC (permalink / raw)
  To: Andrew Lunn, Vivien Didelot, Florian Fainelli, Vladimir Oltean,
	David S. Miller, Jakub Kicinski, Rob Herring, Russell King,
	netdev, devicetree, linux-kernel
  Cc: Ansuel Smith

Document qca,sgmii-enable-pll binding used in the CPU nodes to
enable SGMII PLL on MAC config.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
 Documentation/devicetree/bindings/net/dsa/qca8k.txt | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/dsa/qca8k.txt b/Documentation/devicetree/bindings/net/dsa/qca8k.txt
index aeb206556f54..05a8ddfb5483 100644
--- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt
+++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt
@@ -45,6 +45,16 @@ A CPU port node has the following optional node:
                                 Mostly used in qca8327 with CPU port 0 set to
                                 sgmii.
 - qca,sgmii-txclk-falling-edge: Set the transmit clock phase to falling edge.
+- qca,sgmii-enable-pll  : For SGMII CPU port, explicitly enable PLL, TX and RX
+                          chain along with Signal Detection.
+                          This should NOT be enabled for qca8327. If enabled with
+                          qca8327 the sgmii port won't correctly init and an err
+                          is printed.
+                          This can be required for qca8337 switch with revision 2.
+                          A warning is displayed when used with revision greater
+                          2.
+                          With CPU port set to sgmii and qca8337 it is advised
+                          to set this unless a communication problem is observed.
 
 For QCA8K the 'fixed-link' sub-node supports only the following properties:
 
-- 
2.32.0


^ permalink raw reply related	[flat|nested] 16+ messages in thread
* [net-next PATCH v3 09/13] drivers: net: dsa: qca8k: add support for pws config reg
  2021-10-10  1:55 [net-next PATCH v3 00/13] Multiple improvement for qca8337 switch Ansuel Smith
                   ` (7 preceding siblings ...)
  2021-10-10  1:55 ` [net-next PATCH v3 08/13] dt-bindings: net: dsa: qca8k: Document qca,sgmii-enable-pll Ansuel Smith
@ 2021-10-10  1:55 ` Ansuel Smith
  2021-10-10  1:56 ` [net-next PATCH v3 10/13] dt-bindings: net: dsa: qca8k: document open drain binding Ansuel Smith
                   ` (3 subsequent siblings)
  12 siblings, 0 replies; 16+ messages in thread
From: Ansuel Smith @ 2021-10-10  1:55 UTC (permalink / raw)
  To: Andrew Lunn, Vivien Didelot, Florian Fainelli, Vladimir Oltean,
	David S. Miller, Jakub Kicinski, Rob Herring, Russell King,
	netdev, devicetree, linux-kernel
  Cc: Ansuel Smith

Some qca8327 switch require to force the ignore of power on sel
strapping. Some switch require to set the led open drain mode in regs
instead of using strapping. While most of the device implements this
using the correct way using pin strapping, there are still some broken
device that require to be set using sw regs.
Introduce a new binding and support these special configuration.
As led open drain require to ignore pin strapping to work, the probe
fails with EINVAL error with incorrect configuration.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
 drivers/net/dsa/qca8k.c | 39 +++++++++++++++++++++++++++++++++++++++
 drivers/net/dsa/qca8k.h |  6 ++++++
 2 files changed, 45 insertions(+)

diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
index b73b92ebd72e..3e2274cb82cd 100644
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -931,6 +931,41 @@ static int qca8k_find_cpu_port(struct dsa_switch *ds)
 	return -EINVAL;
 }
 
+static int
+qca8k_setup_of_pws_reg(struct qca8k_priv *priv)
+{
+	struct device_node *node = priv->dev->of_node;
+	u32 val = 0;
+	int ret;
+
+	/* QCA8327 require to set to the correct mode.
+	 * His bigger brother QCA8328 have the 172 pin layout.
+	 * Should be applied by default but we set this just to make sure.
+	 */
+	if (priv->switch_id == QCA8K_ID_QCA8327) {
+		ret = qca8k_rmw(priv, QCA8K_REG_PWS, QCA8327_PWS_PACKAGE148_EN,
+				QCA8327_PWS_PACKAGE148_EN);
+		if (ret)
+			return ret;
+	}
+
+	if (of_property_read_bool(node, "qca,ignore-power-on-sel"))
+		val |= QCA8K_PWS_POWER_ON_SEL;
+
+	if (of_property_read_bool(node, "qca,led-open-drain")) {
+		if (!(val & QCA8K_PWS_POWER_ON_SEL)) {
+			dev_err(priv->dev, "qca,led-open-drain require qca,ignore-power-on-sel to be set.");
+			return -EINVAL;
+		}
+
+		val |= QCA8K_PWS_LED_OPEN_EN_CSR;
+	}
+
+	return qca8k_rmw(priv, QCA8K_REG_PWS,
+			QCA8K_PWS_LED_OPEN_EN_CSR | QCA8K_PWS_POWER_ON_SEL,
+			val);
+}
+
 static int
 qca8k_setup(struct dsa_switch *ds)
 {
@@ -957,6 +992,10 @@ qca8k_setup(struct dsa_switch *ds)
 	if (ret)
 		return ret;
 
+	ret = qca8k_setup_of_pws_reg(priv);
+	if (ret)
+		return ret;
+
 	ret = qca8k_setup_mac_pwr_sel(priv);
 	if (ret)
 		return ret;
diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h
index a790b27bc310..535a4515e7b9 100644
--- a/drivers/net/dsa/qca8k.h
+++ b/drivers/net/dsa/qca8k.h
@@ -46,6 +46,12 @@
 #define   QCA8K_MAX_DELAY				3
 #define   QCA8K_PORT_PAD_SGMII_EN			BIT(7)
 #define QCA8K_REG_PWS					0x010
+#define   QCA8K_PWS_POWER_ON_SEL			BIT(31)
+/* This reg is only valid for QCA832x and toggle the package
+ * type from 176 pin (by default) to 148 pin used on QCA8327
+ */
+#define   QCA8327_PWS_PACKAGE148_EN			BIT(30)
+#define   QCA8K_PWS_LED_OPEN_EN_CSR			BIT(24)
 #define   QCA8K_PWS_SERDES_AEN_DIS			BIT(7)
 #define QCA8K_REG_MODULE_EN				0x030
 #define   QCA8K_MODULE_EN_MIB				BIT(0)
-- 
2.32.0


^ permalink raw reply related	[flat|nested] 16+ messages in thread
* [net-next PATCH v3 10/13] dt-bindings: net: dsa: qca8k: document open drain binding
  2021-10-10  1:55 [net-next PATCH v3 00/13] Multiple improvement for qca8337 switch Ansuel Smith
                   ` (8 preceding siblings ...)
  2021-10-10  1:55 ` [net-next PATCH v3 09/13] drivers: net: dsa: qca8k: add support for pws config reg Ansuel Smith
@ 2021-10-10  1:56 ` Ansuel Smith
  2021-10-10  1:56 ` [net-next PATCH v3 11/13] drivers: net: dsa: qca8k: add support for QCA8328 Ansuel Smith
                   ` (2 subsequent siblings)
  12 siblings, 0 replies; 16+ messages in thread
From: Ansuel Smith @ 2021-10-10  1:56 UTC (permalink / raw)
  To: Andrew Lunn, Vivien Didelot, Florian Fainelli, Vladimir Oltean,
	David S. Miller, Jakub Kicinski, Rob Herring, Russell King,
	netdev, devicetree, linux-kernel
  Cc: Ansuel Smith

Document new binding qca,power_on_sel used to enable Power-on-strapping
select reg and qca,led_open_drain to set led to open drain mode.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
 Documentation/devicetree/bindings/net/dsa/qca8k.txt | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/dsa/qca8k.txt b/Documentation/devicetree/bindings/net/dsa/qca8k.txt
index 05a8ddfb5483..71cd45818430 100644
--- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt
+++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt
@@ -13,6 +13,17 @@ Required properties:
 Optional properties:
 
 - reset-gpios: GPIO to be used to reset the whole device
+- qca,ignore-power-on-sel: Ignore power on pin strapping to configure led open
+                           drain or eeprom presence. This is needed for broken
+                           device that have wrong configuration or when the oem
+                           decided to not use pin strapping and fallback to sw
+                           regs.
+- qca,led-open-drain: Set leds to open-drain mode. This require the
+                      qca,ignore-power-on-sel to be set or the driver will fail
+                      to probe. This is needed if the oem doesn't use pin
+                      strapping to set this mode and prefer to set it using sw
+                      regs. The pin strapping related to led open drain mode is
+                      the pin B68 for QCA832x and B49 for QCA833x
 
 Subnodes:
 
-- 
2.32.0


^ permalink raw reply related	[flat|nested] 16+ messages in thread
* [net-next PATCH v3 11/13] drivers: net: dsa: qca8k: add support for QCA8328
  2021-10-10  1:55 [net-next PATCH v3 00/13] Multiple improvement for qca8337 switch Ansuel Smith
                   ` (9 preceding siblings ...)
  2021-10-10  1:56 ` [net-next PATCH v3 10/13] dt-bindings: net: dsa: qca8k: document open drain binding Ansuel Smith
@ 2021-10-10  1:56 ` Ansuel Smith
  2021-10-10  1:56 ` [net-next PATCH v3 12/13] dt-bindings: net: dsa: qca8k: document support for qca8328 Ansuel Smith
  2021-10-10  1:56 ` [net-next PATCH v3 13/13] drivers: net: dsa: qca8k: set internal delay also for sgmii Ansuel Smith
  12 siblings, 0 replies; 16+ messages in thread
From: Ansuel Smith @ 2021-10-10  1:56 UTC (permalink / raw)
  To: Andrew Lunn, Vivien Didelot, Florian Fainelli, Vladimir Oltean,
	David S. Miller, Jakub Kicinski, Rob Herring, Russell King,
	netdev, devicetree, linux-kernel
  Cc: Ansuel Smith

QCA8328 switch is the bigger brother of the qca8327. Same regs different
chip. Change the function to set the correct pin layout and introduce a
new match_data to differentiate the 2 switch as they have the same ID
and their internal PHY have the same ID.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
 drivers/net/dsa/qca8k.c | 19 ++++++++++++++++---
 drivers/net/dsa/qca8k.h |  1 +
 2 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
index 3e2274cb82cd..7c68c272ce3a 100644
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -935,6 +935,7 @@ static int
 qca8k_setup_of_pws_reg(struct qca8k_priv *priv)
 {
 	struct device_node *node = priv->dev->of_node;
+	const struct qca8k_match_data *data;
 	u32 val = 0;
 	int ret;
 
@@ -943,8 +944,14 @@ qca8k_setup_of_pws_reg(struct qca8k_priv *priv)
 	 * Should be applied by default but we set this just to make sure.
 	 */
 	if (priv->switch_id == QCA8K_ID_QCA8327) {
+		data = of_device_get_match_data(priv->dev);
+
+		/* Set the correct package of 148 pin for QCA8327 */
+		if (data->reduced_package)
+			val |= QCA8327_PWS_PACKAGE148_EN;
+
 		ret = qca8k_rmw(priv, QCA8K_REG_PWS, QCA8327_PWS_PACKAGE148_EN,
-				QCA8327_PWS_PACKAGE148_EN);
+				val);
 		if (ret)
 			return ret;
 	}
@@ -2018,7 +2025,12 @@ static int qca8k_resume(struct device *dev)
 static SIMPLE_DEV_PM_OPS(qca8k_pm_ops,
 			 qca8k_suspend, qca8k_resume);
 
-static const struct qca8k_match_data qca832x = {
+static const struct qca8k_match_data qca8327 = {
+	.id = QCA8K_ID_QCA8327,
+	.reduced_package = true,
+};
+
+static const struct qca8k_match_data qca8328 = {
 	.id = QCA8K_ID_QCA8327,
 };
 
@@ -2027,7 +2039,8 @@ static const struct qca8k_match_data qca833x = {
 };
 
 static const struct of_device_id qca8k_of_match[] = {
-	{ .compatible = "qca,qca8327", .data = &qca832x },
+	{ .compatible = "qca,qca8327", .data = &qca8327 },
+	{ .compatible = "qca,qca8328", .data = &qca8328 },
 	{ .compatible = "qca,qca8334", .data = &qca833x },
 	{ .compatible = "qca,qca8337", .data = &qca833x },
 	{ /* sentinel */ },
diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h
index 535a4515e7b9..c032db5e0d41 100644
--- a/drivers/net/dsa/qca8k.h
+++ b/drivers/net/dsa/qca8k.h
@@ -260,6 +260,7 @@ struct ar8xxx_port_status {
 
 struct qca8k_match_data {
 	u8 id;
+	bool reduced_package;
 };
 
 struct qca8k_priv {
-- 
2.32.0


^ permalink raw reply related	[flat|nested] 16+ messages in thread
* [net-next PATCH v3 12/13] dt-bindings: net: dsa: qca8k: document support for qca8328
  2021-10-10  1:55 [net-next PATCH v3 00/13] Multiple improvement for qca8337 switch Ansuel Smith
                   ` (10 preceding siblings ...)
  2021-10-10  1:56 ` [net-next PATCH v3 11/13] drivers: net: dsa: qca8k: add support for QCA8328 Ansuel Smith
@ 2021-10-10  1:56 ` Ansuel Smith
  2021-10-10  1:56 ` [net-next PATCH v3 13/13] drivers: net: dsa: qca8k: set internal delay also for sgmii Ansuel Smith
  12 siblings, 0 replies; 16+ messages in thread
From: Ansuel Smith @ 2021-10-10  1:56 UTC (permalink / raw)
  To: Andrew Lunn, Vivien Didelot, Florian Fainelli, Vladimir Oltean,
	David S. Miller, Jakub Kicinski, Rob Herring, Russell King,
	netdev, devicetree, linux-kernel
  Cc: Ansuel Smith

QCA8328 is the bigger brother of qca8327. Document the new compatible
binding and add some information to understand the various switch
compatible.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
 Documentation/devicetree/bindings/net/dsa/qca8k.txt | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/dsa/qca8k.txt b/Documentation/devicetree/bindings/net/dsa/qca8k.txt
index 71cd45818430..e6b580d815c2 100644
--- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt
+++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt
@@ -3,9 +3,10 @@
 Required properties:
 
 - compatible: should be one of:
-    "qca,qca8327"
-    "qca,qca8334"
-    "qca,qca8337"
+    "qca,qca8328": referenced as AR8328(N)-AK1(A/B) QFN 176 pin package
+    "qca,qca8327": referenced as AR8327(N)-AL1A DR-QFN 148 pin package
+    "qca,qca8334": referenced as QCA8334-AL3C QFN 88 pin package
+    "qca,qca8337": referenced as QCA8337N-AL3(B/C) DR-QFN 148 pin package
 
 - #size-cells: must be 0
 - #address-cells: must be 1
-- 
2.32.0


^ permalink raw reply related	[flat|nested] 16+ messages in thread
* [net-next PATCH v3 13/13] drivers: net: dsa: qca8k: set internal delay also for sgmii
  2021-10-10  1:55 [net-next PATCH v3 00/13] Multiple improvement for qca8337 switch Ansuel Smith
                   ` (11 preceding siblings ...)
  2021-10-10  1:56 ` [net-next PATCH v3 12/13] dt-bindings: net: dsa: qca8k: document support for qca8328 Ansuel Smith
@ 2021-10-10  1:56 ` Ansuel Smith
  12 siblings, 0 replies; 16+ messages in thread
From: Ansuel Smith @ 2021-10-10  1:56 UTC (permalink / raw)
  To: Andrew Lunn, Vivien Didelot, Florian Fainelli, Vladimir Oltean,
	David S. Miller, Jakub Kicinski, Rob Herring, Russell King,
	netdev, devicetree, linux-kernel
  Cc: Ansuel Smith

QCA original code report port instability and sa that SGMII also require
to set internal delay. Generalize the rgmii delay function and apply the
advised value if they are not defined in DT.

Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
 drivers/net/dsa/qca8k.c | 102 +++++++++++++++++++++++++---------------
 drivers/net/dsa/qca8k.h |   2 +
 2 files changed, 67 insertions(+), 37 deletions(-)

diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
index 7c68c272ce3a..21776826bf2e 100644
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -1164,13 +1164,67 @@ qca8k_setup(struct dsa_switch *ds)
 	return 0;
 }
 
+static void
+qca8k_mac_config_setup_internal_delay(struct qca8k_priv *priv, struct dsa_port *dp,
+				      u32 reg, const struct phylink_link_state *state)
+{
+	u32 delay, val = 0;
+	int ret;
+
+	if (state->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+	    state->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
+	    state->interface == PHY_INTERFACE_MODE_SGMII) {
+		if (of_property_read_u32(dp->dn, "tx-internal-delay-ps", &delay))
+			delay = 1;
+		else
+			/* Switch regs accept value in ns, convert ps to ns */
+			delay = delay / 1000;
+
+		if (delay > QCA8K_MAX_DELAY) {
+			dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ns, setting to the max value");
+			delay = 3;
+		}
+
+		val |= QCA8K_PORT_PAD_RGMII_TX_DELAY(delay) |
+			QCA8K_PORT_PAD_RGMII_TX_DELAY_EN;
+	}
+
+	if (state->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+	    state->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
+	    state->interface == PHY_INTERFACE_MODE_SGMII) {
+		if (of_property_read_u32(dp->dn, "rx-internal-delay-ps", &delay))
+			delay = 2;
+		else
+			/* Switch regs accept value in ns, convert ps to ns */
+			delay = delay / 1000;
+
+		if (delay > QCA8K_MAX_DELAY) {
+			dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ns, setting to the max value");
+			delay = 3;
+		}
+
+		val |= QCA8K_PORT_PAD_RGMII_RX_DELAY(delay) |
+			QCA8K_PORT_PAD_RGMII_RX_DELAY_EN;
+	}
+
+	/* Set RGMII delay based on the selected values */
+	ret = qca8k_rmw(priv, reg,
+			QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK |
+			QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK |
+			QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK |
+			QCA8K_PORT_PAD_RGMII_RX_DELAY_EN,
+			val);
+	if (ret)
+		dev_err(priv->dev, "Failed to set internal delay for CPU port %d", dp->index);
+}
+
 static void
 qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
 			 const struct phylink_link_state *state)
 {
 	struct qca8k_priv *priv = ds->priv;
 	struct dsa_port *dp;
-	u32 reg, val, delay;
+	u32 reg, val;
 	int ret;
 
 	switch (port) {
@@ -1222,44 +1276,11 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
 	case PHY_INTERFACE_MODE_RGMII_TXID:
 	case PHY_INTERFACE_MODE_RGMII_RXID:
 		dp = dsa_to_port(ds, port);
-		val = QCA8K_PORT_PAD_RGMII_EN;
-
-		if (state->interface == PHY_INTERFACE_MODE_RGMII_ID ||
-		    state->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
-			if (of_property_read_u32(dp->dn, "tx-internal-delay-ps", &delay))
-				delay = 1;
-			else
-				/* Switch regs accept value in ns, convert ps to ns */
-				delay = delay / 1000;
-
-			if (delay > QCA8K_MAX_DELAY) {
-				dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ns, setting to the max value");
-				delay = 3;
-			}
-
-			val |= QCA8K_PORT_PAD_RGMII_TX_DELAY(delay) |
-			       QCA8K_PORT_PAD_RGMII_TX_DELAY_EN;
-		}
 
-		if (state->interface == PHY_INTERFACE_MODE_RGMII_ID ||
-		    state->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
-			if (of_property_read_u32(dp->dn, "rx-internal-delay-ps", &delay))
-				delay = 2;
-			else
-				/* Switch regs accept value in ns, convert ps to ns */
-				delay = delay / 1000;
-
-			if (delay > QCA8K_MAX_DELAY) {
-				dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ns, setting to the max value");
-				delay = 3;
-			}
-
-			val |= QCA8K_PORT_PAD_RGMII_RX_DELAY(delay) |
-			       QCA8K_PORT_PAD_RGMII_RX_DELAY_EN;
-		}
+		qca8k_write(priv, reg, QCA8K_PORT_PAD_RGMII_EN);
 
-		/* Set RGMII delay based on the selected values */
-		qca8k_write(priv, reg, val);
+		/* Configure rgmii delay from dp or taking advised values */
+		qca8k_mac_config_setup_internal_delay(priv, dp, reg, state);
 
 		/* QCA8337 requires to set rgmii rx delay for all ports.
 		 * This is enabled through PORT5_PAD_CTRL for all ports,
@@ -1341,6 +1362,13 @@ qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
 					QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE |
 					QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE,
 					val);
+
+		/* From original code is reported port instability as SGMII also
+		 * require delay set. Apply advised values here or take them from DT.
+		 */
+		if (state->interface == PHY_INTERFACE_MODE_SGMII)
+			qca8k_mac_config_setup_internal_delay(priv, dp, reg, state);
+
 		break;
 	default:
 		dev_err(ds->dev, "xMII mode %s not supported for port %d\n",
diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h
index c032db5e0d41..92867001cc34 100644
--- a/drivers/net/dsa/qca8k.h
+++ b/drivers/net/dsa/qca8k.h
@@ -39,7 +39,9 @@
 #define QCA8K_REG_PORT5_PAD_CTRL			0x008
 #define QCA8K_REG_PORT6_PAD_CTRL			0x00c
 #define   QCA8K_PORT_PAD_RGMII_EN			BIT(26)
+#define   QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK		GENMASK(23, 22)
 #define   QCA8K_PORT_PAD_RGMII_TX_DELAY(x)		((x) << 22)
+#define   QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK		GENMASK(21, 20)
 #define   QCA8K_PORT_PAD_RGMII_RX_DELAY(x)		((x) << 20)
 #define	  QCA8K_PORT_PAD_RGMII_TX_DELAY_EN		BIT(25)
 #define   QCA8K_PORT_PAD_RGMII_RX_DELAY_EN		BIT(24)
-- 
2.32.0


^ permalink raw reply related	[flat|nested] 16+ messages in thread
* Re: [net-next PATCH v3 02/13] net: dsa: qca8k: add support for sgmii falling edge
  2021-10-10  1:55 ` [net-next PATCH v3 02/13] net: dsa: qca8k: add support for sgmii falling edge Ansuel Smith
@ 2021-10-10  6:12     ` kernel test robot
  0 siblings, 0 replies; 16+ messages in thread
From: kernel test robot @ 2021-10-10  6:12 UTC (permalink / raw)
  To: Ansuel Smith, Andrew Lunn, Vivien Didelot, Florian Fainelli,
	Vladimir Oltean, David S. Miller, Jakub Kicinski, Rob Herring,
	Russell King, devicetree
  Cc: llvm, kbuild-all, netdev

[-- Attachment #1: Type: text/plain, Size: 7362 bytes --]

Hi Ansuel,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on net-next/master]

url:    https://github.com/0day-ci/linux/commits/Ansuel-Smith/Multiple-improvement-for-qca8337-switch/20211010-095850
base:   https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git 7932d53162dc6550fc56b013da32c0975784647c
config: x86_64-randconfig-a012-20211010 (attached as .config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 903b30fea21f99d8f48fde4defcc838970e30ee1)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/0day-ci/linux/commit/b46afc1d065f0d5add5ea33eae1bf90247ae64c3
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Ansuel-Smith/Multiple-improvement-for-qca8337-switch/20211010-095850
        git checkout b46afc1d065f0d5add5ea33eae1bf90247ae64c3
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 ARCH=x86_64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> drivers/net/dsa/qca8k.c:1285:23: warning: result of comparison of constant 5099574 with expression of type 'u8' (aka 'unsigned char') is always false [-Wtautological-constant-out-of-range-compare]
                       priv->switch_id == PHY_ID_QCA8337)
                       ~~~~~~~~~~~~~~~ ^  ~~~~~~~~~~~~~~
   drivers/net/dsa/qca8k.c:1284:23: warning: result of comparison of constant 5099572 with expression of type 'u8' (aka 'unsigned char') is always false [-Wtautological-constant-out-of-range-compare]
                   if (priv->switch_id == PHY_ID_QCA8327 ||
                       ~~~~~~~~~~~~~~~ ^  ~~~~~~~~~~~~~~
   2 warnings generated.


vim +1285 drivers/net/dsa/qca8k.c

  1169	
  1170	static void
  1171	qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
  1172				 const struct phylink_link_state *state)
  1173	{
  1174		struct qca8k_priv *priv = ds->priv;
  1175		struct dsa_port *dp;
  1176		u32 reg, val;
  1177		int ret;
  1178	
  1179		switch (port) {
  1180		case 0: /* 1st CPU port */
  1181			if (state->interface != PHY_INTERFACE_MODE_RGMII &&
  1182			    state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
  1183			    state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
  1184			    state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
  1185			    state->interface != PHY_INTERFACE_MODE_SGMII)
  1186				return;
  1187	
  1188			reg = QCA8K_REG_PORT0_PAD_CTRL;
  1189			break;
  1190		case 1:
  1191		case 2:
  1192		case 3:
  1193		case 4:
  1194		case 5:
  1195			/* Internal PHY, nothing to do */
  1196			return;
  1197		case 6: /* 2nd CPU port / external PHY */
  1198			if (state->interface != PHY_INTERFACE_MODE_RGMII &&
  1199			    state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
  1200			    state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
  1201			    state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
  1202			    state->interface != PHY_INTERFACE_MODE_SGMII &&
  1203			    state->interface != PHY_INTERFACE_MODE_1000BASEX)
  1204				return;
  1205	
  1206			reg = QCA8K_REG_PORT6_PAD_CTRL;
  1207			break;
  1208		default:
  1209			dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
  1210			return;
  1211		}
  1212	
  1213		if (port != 6 && phylink_autoneg_inband(mode)) {
  1214			dev_err(ds->dev, "%s: in-band negotiation unsupported\n",
  1215				__func__);
  1216			return;
  1217		}
  1218	
  1219		switch (state->interface) {
  1220		case PHY_INTERFACE_MODE_RGMII:
  1221			/* RGMII mode means no delay so don't enable the delay */
  1222			qca8k_write(priv, reg, QCA8K_PORT_PAD_RGMII_EN);
  1223			break;
  1224		case PHY_INTERFACE_MODE_RGMII_ID:
  1225		case PHY_INTERFACE_MODE_RGMII_TXID:
  1226		case PHY_INTERFACE_MODE_RGMII_RXID:
  1227			/* RGMII_ID needs internal delay. This is enabled through
  1228			 * PORT5_PAD_CTRL for all ports, rather than individual port
  1229			 * registers
  1230			 */
  1231			qca8k_write(priv, reg,
  1232				    QCA8K_PORT_PAD_RGMII_EN |
  1233				    QCA8K_PORT_PAD_RGMII_TX_DELAY(priv->rgmii_tx_delay) |
  1234				    QCA8K_PORT_PAD_RGMII_RX_DELAY(priv->rgmii_rx_delay) |
  1235				    QCA8K_PORT_PAD_RGMII_TX_DELAY_EN |
  1236				    QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
  1237			/* QCA8337 requires to set rgmii rx delay */
  1238			if (priv->switch_id == QCA8K_ID_QCA8337)
  1239				qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
  1240					    QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
  1241			break;
  1242		case PHY_INTERFACE_MODE_SGMII:
  1243		case PHY_INTERFACE_MODE_1000BASEX:
  1244			dp = dsa_to_port(ds, port);
  1245	
  1246			/* Enable SGMII on the port */
  1247			qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
  1248	
  1249			/* Enable/disable SerDes auto-negotiation as necessary */
  1250			ret = qca8k_read(priv, QCA8K_REG_PWS, &val);
  1251			if (ret)
  1252				return;
  1253			if (phylink_autoneg_inband(mode))
  1254				val &= ~QCA8K_PWS_SERDES_AEN_DIS;
  1255			else
  1256				val |= QCA8K_PWS_SERDES_AEN_DIS;
  1257			qca8k_write(priv, QCA8K_REG_PWS, val);
  1258	
  1259			/* Configure the SGMII parameters */
  1260			ret = qca8k_read(priv, QCA8K_REG_SGMII_CTRL, &val);
  1261			if (ret)
  1262				return;
  1263	
  1264			val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |
  1265				QCA8K_SGMII_EN_TX | QCA8K_SGMII_EN_SD;
  1266	
  1267			if (dsa_is_cpu_port(ds, port)) {
  1268				/* CPU port, we're talking to the CPU MAC, be a PHY */
  1269				val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
  1270				val |= QCA8K_SGMII_MODE_CTRL_PHY;
  1271			} else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
  1272				val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
  1273				val |= QCA8K_SGMII_MODE_CTRL_MAC;
  1274			} else if (state->interface == PHY_INTERFACE_MODE_1000BASEX) {
  1275				val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
  1276				val |= QCA8K_SGMII_MODE_CTRL_BASEX;
  1277			}
  1278	
  1279			qca8k_write(priv, QCA8K_REG_SGMII_CTRL, val);
  1280	
  1281			/* For qca8327/qca8328/qca8334/qca8338 sgmii is unique and
  1282			 * falling edge is set writing in the PORT0 PAD reg
  1283			 */
  1284			if (priv->switch_id == PHY_ID_QCA8327 ||
> 1285			    priv->switch_id == PHY_ID_QCA8337)
  1286				reg = QCA8K_REG_PORT0_PAD_CTRL;
  1287	
  1288			val = 0;
  1289	
  1290			/* SGMII Clock phase configuration */
  1291			if (of_property_read_bool(dp->dn, "qca,sgmii-rxclk-falling-edge"))
  1292				val |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE;
  1293	
  1294			if (of_property_read_bool(dp->dn, "qca,sgmii-txclk-falling-edge"))
  1295				val |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE;
  1296	
  1297			if (val)
  1298				ret = qca8k_rmw(priv, reg,
  1299						QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE |
  1300						QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE,
  1301						val);
  1302			break;
  1303		default:
  1304			dev_err(ds->dev, "xMII mode %s not supported for port %d\n",
  1305				phy_modes(state->interface), port);
  1306			return;
  1307		}
  1308	}
  1309	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 33844 bytes --]

^ permalink raw reply	[flat|nested] 16+ messages in thread
* Re: [net-next PATCH v3 02/13] net: dsa: qca8k: add support for sgmii falling edge
@ 2021-10-10  6:12     ` kernel test robot
  0 siblings, 0 replies; 16+ messages in thread
From: kernel test robot @ 2021-10-10  6:12 UTC (permalink / raw)
  To: kbuild-all

[-- Attachment #1: Type: text/plain, Size: 7545 bytes --]

Hi Ansuel,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on net-next/master]

url:    https://github.com/0day-ci/linux/commits/Ansuel-Smith/Multiple-improvement-for-qca8337-switch/20211010-095850
base:   https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git 7932d53162dc6550fc56b013da32c0975784647c
config: x86_64-randconfig-a012-20211010 (attached as .config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 903b30fea21f99d8f48fde4defcc838970e30ee1)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/0day-ci/linux/commit/b46afc1d065f0d5add5ea33eae1bf90247ae64c3
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review Ansuel-Smith/Multiple-improvement-for-qca8337-switch/20211010-095850
        git checkout b46afc1d065f0d5add5ea33eae1bf90247ae64c3
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 ARCH=x86_64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> drivers/net/dsa/qca8k.c:1285:23: warning: result of comparison of constant 5099574 with expression of type 'u8' (aka 'unsigned char') is always false [-Wtautological-constant-out-of-range-compare]
                       priv->switch_id == PHY_ID_QCA8337)
                       ~~~~~~~~~~~~~~~ ^  ~~~~~~~~~~~~~~
   drivers/net/dsa/qca8k.c:1284:23: warning: result of comparison of constant 5099572 with expression of type 'u8' (aka 'unsigned char') is always false [-Wtautological-constant-out-of-range-compare]
                   if (priv->switch_id == PHY_ID_QCA8327 ||
                       ~~~~~~~~~~~~~~~ ^  ~~~~~~~~~~~~~~
   2 warnings generated.


vim +1285 drivers/net/dsa/qca8k.c

  1169	
  1170	static void
  1171	qca8k_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
  1172				 const struct phylink_link_state *state)
  1173	{
  1174		struct qca8k_priv *priv = ds->priv;
  1175		struct dsa_port *dp;
  1176		u32 reg, val;
  1177		int ret;
  1178	
  1179		switch (port) {
  1180		case 0: /* 1st CPU port */
  1181			if (state->interface != PHY_INTERFACE_MODE_RGMII &&
  1182			    state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
  1183			    state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
  1184			    state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
  1185			    state->interface != PHY_INTERFACE_MODE_SGMII)
  1186				return;
  1187	
  1188			reg = QCA8K_REG_PORT0_PAD_CTRL;
  1189			break;
  1190		case 1:
  1191		case 2:
  1192		case 3:
  1193		case 4:
  1194		case 5:
  1195			/* Internal PHY, nothing to do */
  1196			return;
  1197		case 6: /* 2nd CPU port / external PHY */
  1198			if (state->interface != PHY_INTERFACE_MODE_RGMII &&
  1199			    state->interface != PHY_INTERFACE_MODE_RGMII_ID &&
  1200			    state->interface != PHY_INTERFACE_MODE_RGMII_TXID &&
  1201			    state->interface != PHY_INTERFACE_MODE_RGMII_RXID &&
  1202			    state->interface != PHY_INTERFACE_MODE_SGMII &&
  1203			    state->interface != PHY_INTERFACE_MODE_1000BASEX)
  1204				return;
  1205	
  1206			reg = QCA8K_REG_PORT6_PAD_CTRL;
  1207			break;
  1208		default:
  1209			dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port);
  1210			return;
  1211		}
  1212	
  1213		if (port != 6 && phylink_autoneg_inband(mode)) {
  1214			dev_err(ds->dev, "%s: in-band negotiation unsupported\n",
  1215				__func__);
  1216			return;
  1217		}
  1218	
  1219		switch (state->interface) {
  1220		case PHY_INTERFACE_MODE_RGMII:
  1221			/* RGMII mode means no delay so don't enable the delay */
  1222			qca8k_write(priv, reg, QCA8K_PORT_PAD_RGMII_EN);
  1223			break;
  1224		case PHY_INTERFACE_MODE_RGMII_ID:
  1225		case PHY_INTERFACE_MODE_RGMII_TXID:
  1226		case PHY_INTERFACE_MODE_RGMII_RXID:
  1227			/* RGMII_ID needs internal delay. This is enabled through
  1228			 * PORT5_PAD_CTRL for all ports, rather than individual port
  1229			 * registers
  1230			 */
  1231			qca8k_write(priv, reg,
  1232				    QCA8K_PORT_PAD_RGMII_EN |
  1233				    QCA8K_PORT_PAD_RGMII_TX_DELAY(priv->rgmii_tx_delay) |
  1234				    QCA8K_PORT_PAD_RGMII_RX_DELAY(priv->rgmii_rx_delay) |
  1235				    QCA8K_PORT_PAD_RGMII_TX_DELAY_EN |
  1236				    QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
  1237			/* QCA8337 requires to set rgmii rx delay */
  1238			if (priv->switch_id == QCA8K_ID_QCA8337)
  1239				qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
  1240					    QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
  1241			break;
  1242		case PHY_INTERFACE_MODE_SGMII:
  1243		case PHY_INTERFACE_MODE_1000BASEX:
  1244			dp = dsa_to_port(ds, port);
  1245	
  1246			/* Enable SGMII on the port */
  1247			qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
  1248	
  1249			/* Enable/disable SerDes auto-negotiation as necessary */
  1250			ret = qca8k_read(priv, QCA8K_REG_PWS, &val);
  1251			if (ret)
  1252				return;
  1253			if (phylink_autoneg_inband(mode))
  1254				val &= ~QCA8K_PWS_SERDES_AEN_DIS;
  1255			else
  1256				val |= QCA8K_PWS_SERDES_AEN_DIS;
  1257			qca8k_write(priv, QCA8K_REG_PWS, val);
  1258	
  1259			/* Configure the SGMII parameters */
  1260			ret = qca8k_read(priv, QCA8K_REG_SGMII_CTRL, &val);
  1261			if (ret)
  1262				return;
  1263	
  1264			val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |
  1265				QCA8K_SGMII_EN_TX | QCA8K_SGMII_EN_SD;
  1266	
  1267			if (dsa_is_cpu_port(ds, port)) {
  1268				/* CPU port, we're talking to the CPU MAC, be a PHY */
  1269				val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
  1270				val |= QCA8K_SGMII_MODE_CTRL_PHY;
  1271			} else if (state->interface == PHY_INTERFACE_MODE_SGMII) {
  1272				val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
  1273				val |= QCA8K_SGMII_MODE_CTRL_MAC;
  1274			} else if (state->interface == PHY_INTERFACE_MODE_1000BASEX) {
  1275				val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
  1276				val |= QCA8K_SGMII_MODE_CTRL_BASEX;
  1277			}
  1278	
  1279			qca8k_write(priv, QCA8K_REG_SGMII_CTRL, val);
  1280	
  1281			/* For qca8327/qca8328/qca8334/qca8338 sgmii is unique and
  1282			 * falling edge is set writing in the PORT0 PAD reg
  1283			 */
  1284			if (priv->switch_id == PHY_ID_QCA8327 ||
> 1285			    priv->switch_id == PHY_ID_QCA8337)
  1286				reg = QCA8K_REG_PORT0_PAD_CTRL;
  1287	
  1288			val = 0;
  1289	
  1290			/* SGMII Clock phase configuration */
  1291			if (of_property_read_bool(dp->dn, "qca,sgmii-rxclk-falling-edge"))
  1292				val |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE;
  1293	
  1294			if (of_property_read_bool(dp->dn, "qca,sgmii-txclk-falling-edge"))
  1295				val |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE;
  1296	
  1297			if (val)
  1298				ret = qca8k_rmw(priv, reg,
  1299						QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE |
  1300						QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE,
  1301						val);
  1302			break;
  1303		default:
  1304			dev_err(ds->dev, "xMII mode %s not supported for port %d\n",
  1305				phy_modes(state->interface), port);
  1306			return;
  1307		}
  1308	}
  1309	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org

[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 33844 bytes --]

^ permalink raw reply	[flat|nested] 16+ messages in thread
end of thread, other threads:[~2021-10-10  6:13 UTC | newest]

Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-10-10  1:55 [net-next PATCH v3 00/13] Multiple improvement for qca8337 switch Ansuel Smith
2021-10-10  1:55 ` [net-next PATCH v3 01/13] net: dsa: qca8k: add mac_power_sel support Ansuel Smith
2021-10-10  1:55 ` [net-next PATCH v3 02/13] net: dsa: qca8k: add support for sgmii falling edge Ansuel Smith
2021-10-10  6:12   ` kernel test robot
2021-10-10  6:12     ` kernel test robot
2021-10-10  1:55 ` [net-next PATCH v3 03/13] dt-bindings: net: dsa: qca8k: Add MAC swap and clock phase properties Ansuel Smith
2021-10-10  1:55 ` [net-next PATCH v3 04/13] drivers: net: dsa: qca8k: add support for cpu port 6 Ansuel Smith
2021-10-10  1:55 ` [net-next PATCH v3 05/13] dt-bindings: net: dsa: qca8k: Document support for CPU " Ansuel Smith
2021-10-10  1:55 ` [net-next PATCH v3 06/13] net: dsa: qca8k: move rgmii delay detection to phylink mac_config Ansuel Smith
2021-10-10  1:55 ` [net-next PATCH v3 07/13] net: dsa: qca8k: add explicit SGMII PLL enable Ansuel Smith
2021-10-10  1:55 ` [net-next PATCH v3 08/13] dt-bindings: net: dsa: qca8k: Document qca,sgmii-enable-pll Ansuel Smith
2021-10-10  1:55 ` [net-next PATCH v3 09/13] drivers: net: dsa: qca8k: add support for pws config reg Ansuel Smith
2021-10-10  1:56 ` [net-next PATCH v3 10/13] dt-bindings: net: dsa: qca8k: document open drain binding Ansuel Smith
2021-10-10  1:56 ` [net-next PATCH v3 11/13] drivers: net: dsa: qca8k: add support for QCA8328 Ansuel Smith
2021-10-10  1:56 ` [net-next PATCH v3 12/13] dt-bindings: net: dsa: qca8k: document support for qca8328 Ansuel Smith
2021-10-10  1:56 ` [net-next PATCH v3 13/13] drivers: net: dsa: qca8k: set internal delay also for sgmii Ansuel Smith

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