* [PATCH v3 0/5] Panel replay phase1 implementation
@ 2021-10-10 12:10 ` Animesh Manna
0 siblings, 0 replies; 31+ messages in thread
From: Animesh Manna @ 2021-10-10 12:10 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: gwan-gyeong.mun, mika.kahola, jani.nikula, manasi.d.navare,
jose.souza, Animesh Manna
Panel Replay is a power saving feature for DP 2.0 monitor and similar
to PSR on EDP.
These patches are basic enablement patches and reused psr
framework to add panel replay related new changes which
may need further fine tuning to fill the gap if there is any.
Note: The patches are not tested due to unavailability of monitor
Animesh Manna (5):
drm/i915/panelreplay: dpcd register definition for panelreplay
drm/i915/panelreplay: HAS_PR() macro added for panel replay
drm/i915/panelreplay: Initializaton and compute config for panel
replay
drm/i915/panelreplay: enable/disable panel replay
drm/i915/panelreplay: Added state checker for panel replay state
drivers/gpu/drm/i915/display/intel_display.c | 1 +
.../drm/i915/display/intel_display_types.h | 2 +
drivers/gpu/drm/i915/display/intel_dp.c | 43 ++++++++--
drivers/gpu/drm/i915/display/intel_psr.c | 84 ++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_psr.h | 3 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
include/drm/drm_dp_helper.h | 6 ++
8 files changed, 128 insertions(+), 13 deletions(-)
--
2.29.0
^ permalink raw reply [flat|nested] 31+ messages in thread
* [Intel-gfx] [PATCH v3 0/5] Panel replay phase1 implementation
@ 2021-10-10 12:10 ` Animesh Manna
0 siblings, 0 replies; 31+ messages in thread
From: Animesh Manna @ 2021-10-10 12:10 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: gwan-gyeong.mun, mika.kahola, jani.nikula, manasi.d.navare,
jose.souza, Animesh Manna
Panel Replay is a power saving feature for DP 2.0 monitor and similar
to PSR on EDP.
These patches are basic enablement patches and reused psr
framework to add panel replay related new changes which
may need further fine tuning to fill the gap if there is any.
Note: The patches are not tested due to unavailability of monitor
Animesh Manna (5):
drm/i915/panelreplay: dpcd register definition for panelreplay
drm/i915/panelreplay: HAS_PR() macro added for panel replay
drm/i915/panelreplay: Initializaton and compute config for panel
replay
drm/i915/panelreplay: enable/disable panel replay
drm/i915/panelreplay: Added state checker for panel replay state
drivers/gpu/drm/i915/display/intel_display.c | 1 +
.../drm/i915/display/intel_display_types.h | 2 +
drivers/gpu/drm/i915/display/intel_dp.c | 43 ++++++++--
drivers/gpu/drm/i915/display/intel_psr.c | 84 ++++++++++++++++++-
drivers/gpu/drm/i915/display/intel_psr.h | 3 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
include/drm/drm_dp_helper.h | 6 ++
8 files changed, 128 insertions(+), 13 deletions(-)
--
2.29.0
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v3 1/5] drm/i915/panelreplay: dpcd register definition for panelreplay
2021-10-10 12:10 ` [Intel-gfx] " Animesh Manna
@ 2021-10-10 12:10 ` Animesh Manna
-1 siblings, 0 replies; 31+ messages in thread
From: Animesh Manna @ 2021-10-10 12:10 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: gwan-gyeong.mun, mika.kahola, jani.nikula, manasi.d.navare,
jose.souza, Animesh Manna
DPCD register definition added to check and enable panel replay
capability of the sink.
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
include/drm/drm_dp_helper.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index b52df4db3e8f..8a2b929c3f88 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -541,6 +541,9 @@ struct drm_panel;
/* DFP Capability Extension */
#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+#define DP_PANEL_REPLAY_CAP 0x0b0
+# define PANEL_REPLAY_SUPPORT (1 << 0)
+
/* Link Configuration */
#define DP_LINK_BW_SET 0x100
# define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
@@ -709,6 +712,9 @@ struct drm_panel;
#define DP_BRANCH_DEVICE_CTRL 0x1a1
# define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0)
+#define PANEL_REPLAY_CONFIG 0x1b0
+# define PANEL_REPLAY_ENABLE (1 << 0)
+
#define DP_PAYLOAD_ALLOCATE_SET 0x1c0
#define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
#define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
--
2.29.0
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [Intel-gfx] [PATCH v3 1/5] drm/i915/panelreplay: dpcd register definition for panelreplay
@ 2021-10-10 12:10 ` Animesh Manna
0 siblings, 0 replies; 31+ messages in thread
From: Animesh Manna @ 2021-10-10 12:10 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: gwan-gyeong.mun, mika.kahola, jani.nikula, manasi.d.navare,
jose.souza, Animesh Manna
DPCD register definition added to check and enable panel replay
capability of the sink.
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
include/drm/drm_dp_helper.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index b52df4db3e8f..8a2b929c3f88 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -541,6 +541,9 @@ struct drm_panel;
/* DFP Capability Extension */
#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+#define DP_PANEL_REPLAY_CAP 0x0b0
+# define PANEL_REPLAY_SUPPORT (1 << 0)
+
/* Link Configuration */
#define DP_LINK_BW_SET 0x100
# define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
@@ -709,6 +712,9 @@ struct drm_panel;
#define DP_BRANCH_DEVICE_CTRL 0x1a1
# define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0)
+#define PANEL_REPLAY_CONFIG 0x1b0
+# define PANEL_REPLAY_ENABLE (1 << 0)
+
#define DP_PAYLOAD_ALLOCATE_SET 0x1c0
#define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
#define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
--
2.29.0
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v3 2/5] drm/i915/panelreplay: HAS_PR() macro added for panel replay
2021-10-10 12:10 ` [Intel-gfx] " Animesh Manna
@ 2021-10-10 12:10 ` Animesh Manna
-1 siblings, 0 replies; 31+ messages in thread
From: Animesh Manna @ 2021-10-10 12:10 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: gwan-gyeong.mun, mika.kahola, jani.nikula, manasi.d.navare,
jose.souza, Animesh Manna
Platforms having Display 13 and above will support panel
replay feature of DP 2.0 monitor. Added a HAS_PR() macro
to check for panel replay capability.
v1: Initial version.
v2: DISPLAY_VER macro used instead of has_pr flag. [Jose]
v3: HAS_PR renamed to HAS_PANEL_REPLAY. [Jani]
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 12256218634f..37313bf51a90 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1693,6 +1693,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
#define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
+#define HAS_PANEL_REPLAY(dev_priv) (DISPLAY_VER(dev_priv) >= 13)
#define HAS_PSR_HW_TRACKING(dev_priv) \
(INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
#define HAS_PSR2_SEL_FETCH(dev_priv) (GRAPHICS_VER(dev_priv) >= 12)
--
2.29.0
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [Intel-gfx] [PATCH v3 2/5] drm/i915/panelreplay: HAS_PR() macro added for panel replay
@ 2021-10-10 12:10 ` Animesh Manna
0 siblings, 0 replies; 31+ messages in thread
From: Animesh Manna @ 2021-10-10 12:10 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: gwan-gyeong.mun, mika.kahola, jani.nikula, manasi.d.navare,
jose.souza, Animesh Manna
Platforms having Display 13 and above will support panel
replay feature of DP 2.0 monitor. Added a HAS_PR() macro
to check for panel replay capability.
v1: Initial version.
v2: DISPLAY_VER macro used instead of has_pr flag. [Jose]
v3: HAS_PR renamed to HAS_PANEL_REPLAY. [Jani]
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 12256218634f..37313bf51a90 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1693,6 +1693,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
#define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
#define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
+#define HAS_PANEL_REPLAY(dev_priv) (DISPLAY_VER(dev_priv) >= 13)
#define HAS_PSR_HW_TRACKING(dev_priv) \
(INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
#define HAS_PSR2_SEL_FETCH(dev_priv) (GRAPHICS_VER(dev_priv) >= 12)
--
2.29.0
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v3 3/5] drm/i915/panelreplay: Initializaton and compute config for panel replay
2021-10-10 12:10 ` [Intel-gfx] " Animesh Manna
@ 2021-10-10 12:10 ` Animesh Manna
-1 siblings, 0 replies; 31+ messages in thread
From: Animesh Manna @ 2021-10-10 12:10 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: gwan-gyeong.mun, mika.kahola, jani.nikula, manasi.d.navare,
jose.souza, Animesh Manna
As panel replay feature similar to PSR feature of EDP panel, so currently
utilized existing psr framework for panel replay.
v1: RFC version.
v2: optimized code, pr_enabled and pr_dpcd variable removed. [Jose]
v3:
- code comments improved. [Jani]
- dpcd_readb used instead of dpcd_read. [Jani]
- panel-repaplay init/compute functions moved inside respective psr
function. [Jani]
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
.../drm/i915/display/intel_display_types.h | 2 +
drivers/gpu/drm/i915/display/intel_dp.c | 43 +++++++++++++----
drivers/gpu/drm/i915/display/intel_psr.c | 48 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_psr.h | 3 ++
4 files changed, 87 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 39e11eaec1a3..48f7d676ed2c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1070,6 +1070,7 @@ struct intel_crtc_state {
bool req_psr2_sdp_prior_scanline;
u32 dc3co_exitline;
u16 su_y_granularity;
+ bool has_panel_replay;
struct drm_dp_vsc_sdp psr_vsc;
/*
@@ -1531,6 +1532,7 @@ struct intel_psr {
bool irq_aux_error;
u16 su_w_granularity;
u16 su_y_granularity;
+ bool sink_panel_replay_support;
u32 dc3co_exitline;
u32 dc3co_exit_delay;
struct delayed_work dc3co_work;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 10fda20a5bd8..f58a7b72be14 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1587,12 +1587,22 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- /*
- * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
- * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
- * Colorimetry Format indication.
- */
- vsc->revision = 0x5;
+ if (crtc_state->has_panel_replay) {
+ /*
+ * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
+ * VSC SDP supporting 3D stereo, Panel Replay, and Pixel
+ * Encoding/Colorimetry Format indication.
+ */
+ vsc->revision = 0x7;
+ } else {
+ /*
+ * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
+ * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
+ * Colorimetry Format indication.
+ */
+ vsc->revision = 0x5;
+ }
+
vsc->length = 0x13;
/* DP 1.4a spec, Table 2-120 */
@@ -1701,6 +1711,21 @@ void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
vsc->revision = 0x4;
vsc->length = 0xe;
}
+ } else if (intel_dp->psr.enabled && !intel_dp_is_edp(intel_dp)) {
+ if (intel_dp->psr.colorimetry_support &&
+ intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
+ /* [Panel Replay with colorimetry info] */
+ intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
+ vsc);
+ } else {
+ /*
+ * [Panel Replay without colorimetry info]
+ * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
+ * VSC SDP supporting 3D stereo + Panel Replay.
+ */
+ vsc->revision = 0x6;
+ vsc->length = 0x10;
+ }
} else {
/*
* [PSR1]
@@ -2749,10 +2774,10 @@ static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
/*
- * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
- * per DP 1.4a spec.
+ * Revision 0x5 and 0x7 supports Pixel Encoding/Colorimetry Format as
+ * per DP 1.4a spec and DP 2.0 spec respectively.
*/
- if (vsc->revision != 0x5)
+ if (vsc->revision != 0x5 || vsc->revision != 0x7)
goto out;
/* VSC SDP Payload for DB16 through DB18 */
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 7a205fd5023b..91c2efe2f3ad 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -933,6 +933,21 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
return true;
}
+void intel_panel_replay_compute_config(struct intel_dp *intel_dp,
+ struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+
+ if (!intel_dp->psr.sink_panel_replay_support)
+ return;
+
+ crtc_state->has_panel_replay = true;
+ crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
+
+ if (HAS_PSR2_SEL_FETCH(i915))
+ intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state);
+}
+
void intel_psr_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state)
@@ -942,6 +957,8 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
&crtc_state->hw.adjusted_mode;
int psr_setup_time;
+ intel_panel_replay_compute_config(intel_dp, crtc_state);
+
/*
* Current PSR panels dont work reliably with VRR enabled
* So if VRR is enabled, do not enable PSR.
@@ -2170,6 +2187,35 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
}
}
+/**
+ * intel_panel_replay_init - Check for sink and source capability.
+ * @intel_dp: Intel DP
+ *
+ * This function is called after the initializing connector.
+ * (the initializing of connector treats the handling of connector capabilities)
+ * And it initializes basic panel replay stuff for each DP Encoder.
+ */
+void intel_panel_replay_init(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ u8 pr_dpcd = 0;
+
+ if (!(HAS_DP20(dev_priv) && HAS_PANEL_REPLAY(dev_priv)))
+ return;
+
+ drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP, &pr_dpcd);
+
+ if (!(pr_dpcd & PANEL_REPLAY_SUPPORT)) {
+ drm_dbg_kms(&dev_priv->drm,
+ "Panel replay is not supported by panel\n");
+ return;
+ }
+
+ drm_dbg_kms(&dev_priv->drm,
+ "Panel replay is supported by panel\n");
+ intel_dp->psr.sink_panel_replay_support = true;
+}
+
/**
* intel_psr_init - Init basic PSR work and mutex.
* @intel_dp: Intel DP
@@ -2183,6 +2229,8 @@ void intel_psr_init(struct intel_dp *intel_dp)
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ intel_panel_replay_init(intel_dp);
+
if (!HAS_PSR(dev_priv))
return;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index facffbacd357..c9d1c1f0b470 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -32,6 +32,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
unsigned frontbuffer_bits,
enum fb_op_origin origin);
void intel_psr_init(struct intel_dp *intel_dp);
+void intel_panel_replay_init(struct intel_dp *intel_dp);
void intel_psr_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state);
@@ -52,5 +53,7 @@ void intel_psr2_disable_plane_sel_fetch(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state);
void intel_psr_pause(struct intel_dp *intel_dp);
void intel_psr_resume(struct intel_dp *intel_dp);
+void intel_panel_replay_compute_config(struct intel_dp *intel_dp,
+ struct intel_crtc_state *crtc_state);
#endif /* __INTEL_PSR_H__ */
--
2.29.0
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [Intel-gfx] [PATCH v3 3/5] drm/i915/panelreplay: Initializaton and compute config for panel replay
@ 2021-10-10 12:10 ` Animesh Manna
0 siblings, 0 replies; 31+ messages in thread
From: Animesh Manna @ 2021-10-10 12:10 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: gwan-gyeong.mun, mika.kahola, jani.nikula, manasi.d.navare,
jose.souza, Animesh Manna
As panel replay feature similar to PSR feature of EDP panel, so currently
utilized existing psr framework for panel replay.
v1: RFC version.
v2: optimized code, pr_enabled and pr_dpcd variable removed. [Jose]
v3:
- code comments improved. [Jani]
- dpcd_readb used instead of dpcd_read. [Jani]
- panel-repaplay init/compute functions moved inside respective psr
function. [Jani]
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
.../drm/i915/display/intel_display_types.h | 2 +
drivers/gpu/drm/i915/display/intel_dp.c | 43 +++++++++++++----
drivers/gpu/drm/i915/display/intel_psr.c | 48 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_psr.h | 3 ++
4 files changed, 87 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 39e11eaec1a3..48f7d676ed2c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1070,6 +1070,7 @@ struct intel_crtc_state {
bool req_psr2_sdp_prior_scanline;
u32 dc3co_exitline;
u16 su_y_granularity;
+ bool has_panel_replay;
struct drm_dp_vsc_sdp psr_vsc;
/*
@@ -1531,6 +1532,7 @@ struct intel_psr {
bool irq_aux_error;
u16 su_w_granularity;
u16 su_y_granularity;
+ bool sink_panel_replay_support;
u32 dc3co_exitline;
u32 dc3co_exit_delay;
struct delayed_work dc3co_work;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 10fda20a5bd8..f58a7b72be14 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1587,12 +1587,22 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- /*
- * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
- * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
- * Colorimetry Format indication.
- */
- vsc->revision = 0x5;
+ if (crtc_state->has_panel_replay) {
+ /*
+ * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
+ * VSC SDP supporting 3D stereo, Panel Replay, and Pixel
+ * Encoding/Colorimetry Format indication.
+ */
+ vsc->revision = 0x7;
+ } else {
+ /*
+ * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
+ * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
+ * Colorimetry Format indication.
+ */
+ vsc->revision = 0x5;
+ }
+
vsc->length = 0x13;
/* DP 1.4a spec, Table 2-120 */
@@ -1701,6 +1711,21 @@ void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
vsc->revision = 0x4;
vsc->length = 0xe;
}
+ } else if (intel_dp->psr.enabled && !intel_dp_is_edp(intel_dp)) {
+ if (intel_dp->psr.colorimetry_support &&
+ intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
+ /* [Panel Replay with colorimetry info] */
+ intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
+ vsc);
+ } else {
+ /*
+ * [Panel Replay without colorimetry info]
+ * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
+ * VSC SDP supporting 3D stereo + Panel Replay.
+ */
+ vsc->revision = 0x6;
+ vsc->length = 0x10;
+ }
} else {
/*
* [PSR1]
@@ -2749,10 +2774,10 @@ static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
/*
- * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
- * per DP 1.4a spec.
+ * Revision 0x5 and 0x7 supports Pixel Encoding/Colorimetry Format as
+ * per DP 1.4a spec and DP 2.0 spec respectively.
*/
- if (vsc->revision != 0x5)
+ if (vsc->revision != 0x5 || vsc->revision != 0x7)
goto out;
/* VSC SDP Payload for DB16 through DB18 */
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 7a205fd5023b..91c2efe2f3ad 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -933,6 +933,21 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
return true;
}
+void intel_panel_replay_compute_config(struct intel_dp *intel_dp,
+ struct intel_crtc_state *crtc_state)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+
+ if (!intel_dp->psr.sink_panel_replay_support)
+ return;
+
+ crtc_state->has_panel_replay = true;
+ crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
+
+ if (HAS_PSR2_SEL_FETCH(i915))
+ intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state);
+}
+
void intel_psr_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state)
@@ -942,6 +957,8 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
&crtc_state->hw.adjusted_mode;
int psr_setup_time;
+ intel_panel_replay_compute_config(intel_dp, crtc_state);
+
/*
* Current PSR panels dont work reliably with VRR enabled
* So if VRR is enabled, do not enable PSR.
@@ -2170,6 +2187,35 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
}
}
+/**
+ * intel_panel_replay_init - Check for sink and source capability.
+ * @intel_dp: Intel DP
+ *
+ * This function is called after the initializing connector.
+ * (the initializing of connector treats the handling of connector capabilities)
+ * And it initializes basic panel replay stuff for each DP Encoder.
+ */
+void intel_panel_replay_init(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ u8 pr_dpcd = 0;
+
+ if (!(HAS_DP20(dev_priv) && HAS_PANEL_REPLAY(dev_priv)))
+ return;
+
+ drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP, &pr_dpcd);
+
+ if (!(pr_dpcd & PANEL_REPLAY_SUPPORT)) {
+ drm_dbg_kms(&dev_priv->drm,
+ "Panel replay is not supported by panel\n");
+ return;
+ }
+
+ drm_dbg_kms(&dev_priv->drm,
+ "Panel replay is supported by panel\n");
+ intel_dp->psr.sink_panel_replay_support = true;
+}
+
/**
* intel_psr_init - Init basic PSR work and mutex.
* @intel_dp: Intel DP
@@ -2183,6 +2229,8 @@ void intel_psr_init(struct intel_dp *intel_dp)
struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+ intel_panel_replay_init(intel_dp);
+
if (!HAS_PSR(dev_priv))
return;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index facffbacd357..c9d1c1f0b470 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -32,6 +32,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
unsigned frontbuffer_bits,
enum fb_op_origin origin);
void intel_psr_init(struct intel_dp *intel_dp);
+void intel_panel_replay_init(struct intel_dp *intel_dp);
void intel_psr_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state);
@@ -52,5 +53,7 @@ void intel_psr2_disable_plane_sel_fetch(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state);
void intel_psr_pause(struct intel_dp *intel_dp);
void intel_psr_resume(struct intel_dp *intel_dp);
+void intel_panel_replay_compute_config(struct intel_dp *intel_dp,
+ struct intel_crtc_state *crtc_state);
#endif /* __INTEL_PSR_H__ */
--
2.29.0
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v3 4/5] drm/i915/panelreplay: enable/disable panel replay
2021-10-10 12:10 ` [Intel-gfx] " Animesh Manna
@ 2021-10-10 12:10 ` Animesh Manna
-1 siblings, 0 replies; 31+ messages in thread
From: Animesh Manna @ 2021-10-10 12:10 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: gwan-gyeong.mun, mika.kahola, jani.nikula, manasi.d.navare,
jose.souza, Animesh Manna
TRANS_DP2_CTL register is programmed to enable panel replay from source
and sink is enabled through panel replay dpcd configuration address.
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 30 ++++++++++++++++++++----
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 27 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 91c2efe2f3ad..49f6242c2fde 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -370,8 +370,14 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u8 dpcd_val = DP_PSR_ENABLE;
- /* Enable ALPM at sink for psr2 */
+ if (intel_dp->psr.enabled && !intel_dp_is_edp(intel_dp)) {
+ drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG,
+ PANEL_REPLAY_ENABLE);
+ return;
+ }
+
if (intel_dp->psr.psr2_enabled) {
+ /* Enable ALPM at sink for psr2 */
drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
DP_ALPM_ENABLE |
DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
@@ -498,6 +504,17 @@ static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
return val;
}
+static void dg2_activate_panel_replay(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
+ ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE);
+
+ intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0,
+ TRANS_DP2_PANEL_REPLAY_ENABLE);
+}
+
static void hsw_activate_psr2(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -1069,8 +1086,10 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
drm_WARN_ON(&dev_priv->drm, intel_dp->psr.active);
lockdep_assert_held(&intel_dp->psr.lock);
- /* psr1 and psr2 are mutually exclusive.*/
- if (intel_dp->psr.psr2_enabled)
+ /* psr1, psr2 and panel-replay are mutually exclusive.*/
+ if (intel_dp->psr.enabled && !intel_dp_is_edp(intel_dp))
+ dg2_activate_panel_replay(intel_dp);
+ else if (intel_dp->psr.psr2_enabled)
hsw_activate_psr2(intel_dp);
else
hsw_activate_psr1(intel_dp);
@@ -1243,7 +1262,10 @@ static void intel_psr_exit(struct intel_dp *intel_dp)
return;
}
- if (intel_dp->psr.psr2_enabled) {
+ if (intel_dp->psr.enabled && !intel_dp_is_edp(intel_dp)) {
+ intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder),
+ TRANS_DP2_PANEL_REPLAY_ENABLE, 0);
+ } else if (intel_dp->psr.psr2_enabled) {
tgl_disallow_dc3co_on_psr2_exit(intel_dp);
val = intel_de_read(dev_priv,
EDP_PSR2_CTL(intel_dp->psr.transcoder));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a897f4abea0c..6cc6ebcd3bdb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4725,6 +4725,7 @@ enum {
#define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3)
#define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2)
#define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1)
+#define ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(31)
#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(28, 16)
#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(12, 0)
--
2.29.0
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [Intel-gfx] [PATCH v3 4/5] drm/i915/panelreplay: enable/disable panel replay
@ 2021-10-10 12:10 ` Animesh Manna
0 siblings, 0 replies; 31+ messages in thread
From: Animesh Manna @ 2021-10-10 12:10 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: gwan-gyeong.mun, mika.kahola, jani.nikula, manasi.d.navare,
jose.souza, Animesh Manna
TRANS_DP2_CTL register is programmed to enable panel replay from source
and sink is enabled through panel replay dpcd configuration address.
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 30 ++++++++++++++++++++----
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 27 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 91c2efe2f3ad..49f6242c2fde 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -370,8 +370,14 @@ static void intel_psr_enable_sink(struct intel_dp *intel_dp)
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
u8 dpcd_val = DP_PSR_ENABLE;
- /* Enable ALPM at sink for psr2 */
+ if (intel_dp->psr.enabled && !intel_dp_is_edp(intel_dp)) {
+ drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG,
+ PANEL_REPLAY_ENABLE);
+ return;
+ }
+
if (intel_dp->psr.psr2_enabled) {
+ /* Enable ALPM at sink for psr2 */
drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG,
DP_ALPM_ENABLE |
DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE);
@@ -498,6 +504,17 @@ static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp)
return val;
}
+static void dg2_activate_panel_replay(struct intel_dp *intel_dp)
+{
+ struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+
+ intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder),
+ ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE);
+
+ intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0,
+ TRANS_DP2_PANEL_REPLAY_ENABLE);
+}
+
static void hsw_activate_psr2(struct intel_dp *intel_dp)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
@@ -1069,8 +1086,10 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
drm_WARN_ON(&dev_priv->drm, intel_dp->psr.active);
lockdep_assert_held(&intel_dp->psr.lock);
- /* psr1 and psr2 are mutually exclusive.*/
- if (intel_dp->psr.psr2_enabled)
+ /* psr1, psr2 and panel-replay are mutually exclusive.*/
+ if (intel_dp->psr.enabled && !intel_dp_is_edp(intel_dp))
+ dg2_activate_panel_replay(intel_dp);
+ else if (intel_dp->psr.psr2_enabled)
hsw_activate_psr2(intel_dp);
else
hsw_activate_psr1(intel_dp);
@@ -1243,7 +1262,10 @@ static void intel_psr_exit(struct intel_dp *intel_dp)
return;
}
- if (intel_dp->psr.psr2_enabled) {
+ if (intel_dp->psr.enabled && !intel_dp_is_edp(intel_dp)) {
+ intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder),
+ TRANS_DP2_PANEL_REPLAY_ENABLE, 0);
+ } else if (intel_dp->psr.psr2_enabled) {
tgl_disallow_dc3co_on_psr2_exit(intel_dp);
val = intel_de_read(dev_priv,
EDP_PSR2_CTL(intel_dp->psr.transcoder));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a897f4abea0c..6cc6ebcd3bdb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4725,6 +4725,7 @@ enum {
#define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME REG_BIT(3)
#define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME REG_BIT(2)
#define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(1)
+#define ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE REG_BIT(31)
#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(28, 16)
#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val)
#define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK REG_GENMASK(12, 0)
--
2.29.0
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [PATCH v3 5/5] drm/i915/panelreplay: Added state checker for panel replay state
2021-10-10 12:10 ` [Intel-gfx] " Animesh Manna
@ 2021-10-10 12:10 ` Animesh Manna
-1 siblings, 0 replies; 31+ messages in thread
From: Animesh Manna @ 2021-10-10 12:10 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: gwan-gyeong.mun, mika.kahola, jani.nikula, manasi.d.navare,
jose.souza, Animesh Manna
has_panel_replay flag is used to check panel replay state
which is part of crtc_state structure.
v1: RFC version.
v2: has_panel_replay flag updated as per hw readout. [Jani]
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
drivers/gpu/drm/i915/display/intel_psr.c | 6 ++++++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 4f0badb11bbb..a30b6fe87dfc 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8136,6 +8136,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_BOOL(has_psr);
PIPE_CONF_CHECK_BOOL(has_psr2);
PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
+ PIPE_CONF_CHECK_BOOL(has_panel_replay);
PIPE_CONF_CHECK_I(dc3co_exitline);
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 49f6242c2fde..d1a30b82ce6f 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1054,6 +1054,12 @@ void intel_psr_get_config(struct intel_encoder *encoder,
pipe_config->has_psr2 = intel_dp->psr.psr2_enabled;
pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
+ if (HAS_PANEL_REPLAY(dev_priv) && HAS_DP20(dev_priv)) {
+ val = intel_de_read(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder));
+ if (val & TRANS_DP2_PANEL_REPLAY_ENABLE)
+ pipe_config->has_panel_replay = true;
+ }
+
if (!intel_dp->psr.psr2_enabled)
goto unlock;
--
2.29.0
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [Intel-gfx] [PATCH v3 5/5] drm/i915/panelreplay: Added state checker for panel replay state
@ 2021-10-10 12:10 ` Animesh Manna
0 siblings, 0 replies; 31+ messages in thread
From: Animesh Manna @ 2021-10-10 12:10 UTC (permalink / raw)
To: intel-gfx, dri-devel
Cc: gwan-gyeong.mun, mika.kahola, jani.nikula, manasi.d.navare,
jose.souza, Animesh Manna
has_panel_replay flag is used to check panel replay state
which is part of crtc_state structure.
v1: RFC version.
v2: has_panel_replay flag updated as per hw readout. [Jani]
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 1 +
drivers/gpu/drm/i915/display/intel_psr.c | 6 ++++++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 4f0badb11bbb..a30b6fe87dfc 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8136,6 +8136,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
PIPE_CONF_CHECK_BOOL(has_psr);
PIPE_CONF_CHECK_BOOL(has_psr2);
PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
+ PIPE_CONF_CHECK_BOOL(has_panel_replay);
PIPE_CONF_CHECK_I(dc3co_exitline);
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 49f6242c2fde..d1a30b82ce6f 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1054,6 +1054,12 @@ void intel_psr_get_config(struct intel_encoder *encoder,
pipe_config->has_psr2 = intel_dp->psr.psr2_enabled;
pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
+ if (HAS_PANEL_REPLAY(dev_priv) && HAS_DP20(dev_priv)) {
+ val = intel_de_read(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder));
+ if (val & TRANS_DP2_PANEL_REPLAY_ENABLE)
+ pipe_config->has_panel_replay = true;
+ }
+
if (!intel_dp->psr.psr2_enabled)
goto unlock;
--
2.29.0
^ permalink raw reply related [flat|nested] 31+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Panel replay phase1 implementation (rev3)
2021-10-10 12:10 ` [Intel-gfx] " Animesh Manna
` (5 preceding siblings ...)
(?)
@ 2021-10-10 12:50 ` Patchwork
-1 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2021-10-10 12:50 UTC (permalink / raw)
To: Animesh Manna; +Cc: intel-gfx
== Series Details ==
Series: Panel replay phase1 implementation (rev3)
URL : https://patchwork.freedesktop.org/series/94470/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
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+
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
+ #def
^ permalink raw reply [flat|nested] 31+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Panel replay phase1 implementation (rev3)
2021-10-10 12:10 ` [Intel-gfx] " Animesh Manna
` (6 preceding siblings ...)
(?)
@ 2021-10-10 13:19 ` Patchwork
-1 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2021-10-10 13:19 UTC (permalink / raw)
To: Animesh Manna; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 3673 bytes --]
== Series Details ==
Series: Panel replay phase1 implementation (rev3)
URL : https://patchwork.freedesktop.org/series/94470/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10706 -> Patchwork_21302
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/index.html
Known issues
------------
Here are the changes found in Patchwork_21302 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@cs-gfx:
- fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271]) +11 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/fi-kbl-soraka/igt@amdgpu/amd_basic@cs-gfx.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [PASS][2] -> [INCOMPLETE][3] ([i915#3921])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10706/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
- fi-kbl-soraka: [PASS][4] -> [DMESG-WARN][5] ([i915#1982])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10706/fi-kbl-soraka/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/fi-kbl-soraka/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
* igt@kms_flip@basic-plain-flip@c-dp2:
- fi-cfl-8109u: [PASS][6] -> [DMESG-WARN][7] ([i915#295])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10706/fi-cfl-8109u/igt@kms_flip@basic-plain-flip@c-dp2.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/fi-cfl-8109u/igt@kms_flip@basic-plain-flip@c-dp2.html
#### Possible fixes ####
* igt@i915_module_load@reload:
- {fi-tgl-dsi}: [DMESG-WARN][8] ([i915#1982]) -> [PASS][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10706/fi-tgl-dsi/igt@i915_module_load@reload.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/fi-tgl-dsi/igt@i915_module_load@reload.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
Participating hosts (39 -> 36)
------------------------------
Missing (3): fi-ilk-m540 fi-bsw-cyan fi-hsw-4200u
Build changes
-------------
* Linux: CI_DRM_10706 -> Patchwork_21302
CI-20190529: 20190529
CI_DRM_10706: 06c55d63636faa92633f3f4673437059dff94bfa @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6241: 426723f979380f18f9c07d36ebac3a52f760ba7e @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_21302: 2e0649d10c3b68737baa4f7410e87a2d1204dc22 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
2e0649d10c3b drm/i915/panelreplay: Added state checker for panel replay state
f8a9c0e7bea1 drm/i915/panelreplay: enable/disable panel replay
24116fc88ff5 drm/i915/panelreplay: Initializaton and compute config for panel replay
958b50451637 drm/i915/panelreplay: HAS_PR() macro added for panel replay
6a3ffaa466ae drm/i915/panelreplay: dpcd register definition for panelreplay
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/index.html
[-- Attachment #2: Type: text/html, Size: 4488 bytes --]
^ permalink raw reply [flat|nested] 31+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for Panel replay phase1 implementation (rev3)
2021-10-10 12:10 ` [Intel-gfx] " Animesh Manna
` (7 preceding siblings ...)
(?)
@ 2021-10-10 14:28 ` Patchwork
-1 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2021-10-10 14:28 UTC (permalink / raw)
To: Animesh Manna; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30264 bytes --]
== Series Details ==
Series: Panel replay phase1 implementation (rev3)
URL : https://patchwork.freedesktop.org/series/94470/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10706_full -> Patchwork_21302_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_21302_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@feature_discovery@display-3x:
- shard-tglb: NOTRUN -> [SKIP][1] ([i915#1839])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-tglb1/igt@feature_discovery@display-3x.html
* igt@gem_ctx_param@invalid-ctx-set:
- shard-skl: [PASS][2] -> [DMESG-WARN][3] ([i915#1982])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10706/shard-skl8/igt@gem_ctx_param@invalid-ctx-set.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-skl10/igt@gem_ctx_param@invalid-ctx-set.html
* igt@gem_ctx_persistence@smoketest:
- shard-snb: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#1099]) +4 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-snb7/igt@gem_ctx_persistence@smoketest.html
* igt@gem_eio@unwedge-stress:
- shard-snb: NOTRUN -> [FAIL][5] ([i915#3354])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-snb7/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][6] ([i915#2842])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-iclb1/igt@gem_exec_fair@basic-none@vcs1.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-glk: [PASS][7] -> [FAIL][8] ([i915#2842]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10706/shard-glk2/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-glk1/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-iclb: [PASS][9] -> [FAIL][10] ([i915#2842])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10706/shard-iclb3/igt@gem_exec_fair@basic-throttle@rcs0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-iclb1/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_flush@basic-batch-kernel-default-cmd:
- shard-snb: NOTRUN -> [SKIP][11] ([fdo#109271]) +324 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-snb7/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
* igt@gem_exec_params@no-blt:
- shard-tglb: NOTRUN -> [SKIP][12] ([fdo#109283])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-tglb1/igt@gem_exec_params@no-blt.html
* igt@gem_exec_params@secure-non-master:
- shard-tglb: NOTRUN -> [SKIP][13] ([fdo#112283])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-tglb1/igt@gem_exec_params@secure-non-master.html
* igt@gem_pxp@reject-modify-context-protection-off-3:
- shard-iclb: NOTRUN -> [SKIP][14] ([i915#4270])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-iclb8/igt@gem_pxp@reject-modify-context-protection-off-3.html
* igt@gem_pxp@reject-modify-context-protection-on:
- shard-tglb: NOTRUN -> [SKIP][15] ([i915#4270])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-tglb1/igt@gem_pxp@reject-modify-context-protection-on.html
* igt@gem_softpin@evict-snoop-interruptible:
- shard-tglb: NOTRUN -> [SKIP][16] ([fdo#109312])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-tglb5/igt@gem_softpin@evict-snoop-interruptible.html
- shard-iclb: NOTRUN -> [SKIP][17] ([fdo#109312])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-iclb2/igt@gem_softpin@evict-snoop-interruptible.html
* igt@gem_userptr_blits@vma-merge:
- shard-apl: NOTRUN -> [FAIL][18] ([i915#3318])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-apl6/igt@gem_userptr_blits@vma-merge.html
- shard-kbl: NOTRUN -> [FAIL][19] ([i915#3318])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-kbl6/igt@gem_userptr_blits@vma-merge.html
* igt@gen3_render_linear_blits:
- shard-iclb: NOTRUN -> [SKIP][20] ([fdo#109289]) +1 similar issue
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-iclb8/igt@gen3_render_linear_blits.html
* igt@gen7_exec_parse@basic-rejected:
- shard-tglb: NOTRUN -> [SKIP][21] ([fdo#109289])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-tglb2/igt@gen7_exec_parse@basic-rejected.html
* igt@gen9_exec_parse@allowed-all:
- shard-tglb: NOTRUN -> [SKIP][22] ([i915#2856])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-tglb5/igt@gen9_exec_parse@allowed-all.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [PASS][23] -> [DMESG-WARN][24] ([i915#1436] / [i915#716])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10706/shard-skl2/igt@gen9_exec_parse@allowed-single.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-skl5/igt@gen9_exec_parse@allowed-single.html
* igt@gen9_exec_parse@bb-start-param:
- shard-iclb: NOTRUN -> [SKIP][25] ([i915#2856])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-iclb8/igt@gen9_exec_parse@bb-start-param.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [PASS][26] -> [FAIL][27] ([i915#454])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10706/shard-iclb7/igt@i915_pm_dc@dc6-psr.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-iclb8/igt@i915_pm_dc@dc6-psr.html
* igt@i915_suspend@sysfs-reader:
- shard-apl: [PASS][28] -> [DMESG-WARN][29] ([i915#180]) +1 similar issue
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10706/shard-apl7/igt@i915_suspend@sysfs-reader.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-apl8/igt@i915_suspend@sysfs-reader.html
* igt@kms_big_fb@linear-32bpp-rotate-90:
- shard-iclb: NOTRUN -> [SKIP][30] ([fdo#110725] / [fdo#111614])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-iclb1/igt@kms_big_fb@linear-32bpp-rotate-90.html
- shard-tglb: NOTRUN -> [SKIP][31] ([fdo#111614]) +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-tglb2/igt@kms_big_fb@linear-32bpp-rotate-90.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-180:
- shard-glk: [PASS][32] -> [DMESG-WARN][33] ([i915#118])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10706/shard-glk7/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-glk2/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-kbl: NOTRUN -> [SKIP][34] ([fdo#109271] / [i915#3777])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-kbl7/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-apl: NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#3777]) +1 similar issue
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-apl2/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-0:
- shard-tglb: NOTRUN -> [SKIP][36] ([fdo#111615]) +1 similar issue
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-tglb2/igt@kms_big_fb@yf-tiled-64bpp-rotate-0.html
- shard-iclb: NOTRUN -> [SKIP][37] ([fdo#110723])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-iclb1/igt@kms_big_fb@yf-tiled-64bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-kbl: NOTRUN -> [SKIP][38] ([fdo#109271]) +111 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-kbl7/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][39] ([fdo#109271] / [i915#3886]) +6 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-apl1/igt@kms_ccs@pipe-a-crc-primary-rotation-180-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_mc_ccs:
- shard-iclb: NOTRUN -> [SKIP][40] ([fdo#109278] / [i915#3886]) +3 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-iclb2/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_mc_ccs.html
- shard-kbl: NOTRUN -> [SKIP][41] ([fdo#109271] / [i915#3886]) +5 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-kbl2/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
- shard-skl: NOTRUN -> [SKIP][42] ([fdo#109271] / [i915#3886]) +2 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-skl8/igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html
- shard-tglb: NOTRUN -> [SKIP][43] ([i915#3689] / [i915#3886]) +2 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-tglb5/igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-d-bad-rotation-90-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][44] ([i915#3689]) +2 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-tglb1/igt@kms_ccs@pipe-d-bad-rotation-90-yf_tiled_ccs.html
* igt@kms_chamelium@hdmi-aspect-ratio:
- shard-skl: NOTRUN -> [SKIP][45] ([fdo#109271] / [fdo#111827])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-skl8/igt@kms_chamelium@hdmi-aspect-ratio.html
* igt@kms_chamelium@hdmi-cmp-planar-formats:
- shard-iclb: NOTRUN -> [SKIP][46] ([fdo#109284] / [fdo#111827]) +3 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-iclb8/igt@kms_chamelium@hdmi-cmp-planar-formats.html
* igt@kms_chamelium@hdmi-edid-change-during-suspend:
- shard-apl: NOTRUN -> [SKIP][47] ([fdo#109271] / [fdo#111827]) +14 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-apl2/igt@kms_chamelium@hdmi-edid-change-during-suspend.html
* igt@kms_chamelium@hdmi-hpd-storm-disable:
- shard-kbl: NOTRUN -> [SKIP][48] ([fdo#109271] / [fdo#111827]) +11 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-kbl7/igt@kms_chamelium@hdmi-hpd-storm-disable.html
* igt@kms_color@pipe-d-ctm-0-25:
- shard-iclb: NOTRUN -> [SKIP][49] ([fdo#109278] / [i915#1149])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-iclb2/igt@kms_color@pipe-d-ctm-0-25.html
* igt@kms_color@pipe-d-invalid-ctm-matrix-sizes:
- shard-iclb: NOTRUN -> [SKIP][50] ([fdo#109278]) +17 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-iclb2/igt@kms_color@pipe-d-invalid-ctm-matrix-sizes.html
* igt@kms_color_chamelium@pipe-a-ctm-0-25:
- shard-snb: NOTRUN -> [SKIP][51] ([fdo#109271] / [fdo#111827]) +11 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-snb7/igt@kms_color_chamelium@pipe-a-ctm-0-25.html
* igt@kms_color_chamelium@pipe-b-ctm-limited-range:
- shard-tglb: NOTRUN -> [SKIP][52] ([fdo#109284] / [fdo#111827]) +4 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-tglb2/igt@kms_color_chamelium@pipe-b-ctm-limited-range.html
* igt@kms_content_protection@mei_interface:
- shard-tglb: NOTRUN -> [SKIP][53] ([fdo#111828])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-tglb1/igt@kms_content_protection@mei_interface.html
* igt@kms_content_protection@srm:
- shard-kbl: NOTRUN -> [TIMEOUT][54] ([i915#1319])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-kbl3/igt@kms_content_protection@srm.html
* igt@kms_cursor_crc@pipe-a-cursor-size-change:
- shard-iclb: NOTRUN -> [FAIL][55] ([i915#3444])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-iclb8/igt@kms_cursor_crc@pipe-a-cursor-size-change.html
* igt@kms_cursor_crc@pipe-b-cursor-max-size-random:
- shard-skl: NOTRUN -> [SKIP][56] ([fdo#109271]) +19 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-skl8/igt@kms_cursor_crc@pipe-b-cursor-max-size-random.html
* igt@kms_cursor_crc@pipe-c-cursor-32x32-rapid-movement:
- shard-tglb: NOTRUN -> [SKIP][57] ([i915#3319]) +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-tglb2/igt@kms_cursor_crc@pipe-c-cursor-32x32-rapid-movement.html
* igt@kms_cursor_crc@pipe-d-cursor-512x512-sliding:
- shard-tglb: NOTRUN -> [SKIP][58] ([fdo#109279] / [i915#3359]) +1 similar issue
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-tglb5/igt@kms_cursor_crc@pipe-d-cursor-512x512-sliding.html
* igt@kms_cursor_crc@pipe-d-cursor-max-size-rapid-movement:
- shard-tglb: NOTRUN -> [SKIP][59] ([i915#3359]) +2 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-tglb5/igt@kms_cursor_crc@pipe-d-cursor-max-size-rapid-movement.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
- shard-tglb: NOTRUN -> [SKIP][60] ([i915#4103])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-tglb1/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: [PASS][61] -> [INCOMPLETE][62] ([i915#180] / [i915#636])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10706/shard-kbl4/igt@kms_fbcon_fbt@fbc-suspend.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@2x-flip-vs-fences:
- shard-iclb: NOTRUN -> [SKIP][63] ([fdo#109274]) +2 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-iclb2/igt@kms_flip@2x-flip-vs-fences.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
- shard-kbl: [PASS][64] -> [DMESG-WARN][65] ([i915#180]) +4 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10706/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1:
- shard-skl: [PASS][66] -> [FAIL][67] ([i915#2122])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10706/shard-skl7/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-skl3/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile:
- shard-iclb: [PASS][68] -> [SKIP][69] ([i915#3701])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10706/shard-iclb4/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs:
- shard-apl: NOTRUN -> [SKIP][70] ([fdo#109271] / [i915#2672])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-apl2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-cpu:
- shard-iclb: NOTRUN -> [SKIP][71] ([fdo#109280]) +7 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt:
- shard-tglb: NOTRUN -> [SKIP][72] ([fdo#111825]) +19 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt.html
* igt@kms_invalid_mode@uint-max-clock:
- shard-snb: [PASS][73] -> [SKIP][74] ([fdo#109271])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10706/shard-snb2/igt@kms_invalid_mode@uint-max-clock.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-snb2/igt@kms_invalid_mode@uint-max-clock.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- shard-apl: NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#533]) +1 similar issue
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-apl2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-d:
- shard-skl: NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#533])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-skl8/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html
- shard-kbl: NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#533])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-kbl2/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-apl: NOTRUN -> [FAIL][78] ([fdo#108145] / [i915#265]) +3 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-apl3/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
- shard-kbl: NOTRUN -> [FAIL][79] ([fdo#108145] / [i915#265])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-kbl7/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][80] ([i915#265])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-apl1/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][81] -> [FAIL][82] ([fdo#108145] / [i915#265])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10706/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_plane_lowres@pipe-a-tiling-yf:
- shard-iclb: NOTRUN -> [SKIP][83] ([i915#3536])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-iclb2/igt@kms_plane_lowres@pipe-a-tiling-yf.html
- shard-tglb: NOTRUN -> [SKIP][84] ([fdo#112054])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-tglb5/igt@kms_plane_lowres@pipe-a-tiling-yf.html
* igt@kms_plane_lowres@pipe-d-tiling-x:
- shard-tglb: NOTRUN -> [SKIP][85] ([i915#3536]) +1 similar issue
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-tglb1/igt@kms_plane_lowres@pipe-d-tiling-x.html
* igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
- shard-kbl: NOTRUN -> [SKIP][86] ([fdo#109271] / [i915#2733])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-kbl3/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5:
- shard-tglb: NOTRUN -> [SKIP][87] ([i915#2920]) +1 similar issue
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-tglb5/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5.html
- shard-skl: NOTRUN -> [SKIP][88] ([fdo#109271] / [i915#658])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-skl8/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5.html
- shard-iclb: NOTRUN -> [SKIP][89] ([i915#2920])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-iclb2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-3:
- shard-apl: NOTRUN -> [SKIP][90] ([fdo#109271] / [i915#658]) +2 similar issues
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-apl6/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-3.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5:
- shard-kbl: NOTRUN -> [SKIP][91] ([fdo#109271] / [i915#658]) +1 similar issue
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-kbl3/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
* igt@kms_psr@psr2_cursor_mmap_gtt:
- shard-iclb: NOTRUN -> [SKIP][92] ([fdo#109441])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-iclb8/igt@kms_psr@psr2_cursor_mmap_gtt.html
* igt@kms_psr@psr2_cursor_plane_move:
- shard-iclb: [PASS][93] -> [SKIP][94] ([fdo#109441])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10706/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-iclb4/igt@kms_psr@psr2_cursor_plane_move.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [PASS][95] -> [DMESG-WARN][96] ([i915#180] / [i915#295])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10706/shard-kbl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-kbl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@kms_vblank@pipe-d-wait-forked-hang:
- shard-apl: NOTRUN -> [SKIP][97] ([fdo#109271]) +221 similar issues
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-apl3/igt@kms_vblank@pipe-d-wait-forked-hang.html
* igt@nouveau_crc@pipe-a-source-rg:
- shard-tglb: NOTRUN -> [SKIP][98] ([i915#2530])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-tglb1/igt@nouveau_crc@pipe-a-source-rg.html
* igt@nouveau_crc@pipe-d-source-outp-inactive:
- shard-iclb: NOTRUN -> [SKIP][99] ([fdo#109278] / [i915#2530])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-iclb8/igt@nouveau_crc@pipe-d-source-outp-inactive.html
* igt@prime_nv_pcopy@test1_micro:
- shard-tglb: NOTRUN -> [SKIP][100] ([fdo#109291]) +2 similar issues
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-tglb1/igt@prime_nv_pcopy@test1_micro.html
* igt@prime_nv_test@i915_import_pread_pwrite:
- shard-iclb: NOTRUN -> [SKIP][101] ([fdo#109291])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-iclb1/igt@prime_nv_test@i915_import_pread_pwrite.html
* igt@sysfs_clients@sema-10:
- shard-skl: NOTRUN -> [SKIP][102] ([fdo#109271] / [i915#2994])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-skl8/igt@sysfs_clients@sema-10.html
- shard-tglb: NOTRUN -> [SKIP][103] ([i915#2994]) +1 similar issue
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-tglb5/igt@sysfs_clients@sema-10.html
- shard-kbl: NOTRUN -> [SKIP][104] ([fdo#109271] / [i915#2994])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-kbl2/igt@sysfs_clients@sema-10.html
- shard-iclb: NOTRUN -> [SKIP][105] ([i915#2994])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-iclb2/igt@sysfs_clients@sema-10.html
* igt@sysfs_clients@sema-50:
- shard-apl: NOTRUN -> [SKIP][106] ([fdo#109271] / [i915#2994])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-apl6/igt@sysfs_clients@sema-50.html
#### Possible fixes ####
* igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-skl: [INCOMPLETE][107] ([i915#146] / [i915#198]) -> [PASS][108]
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10706/shard-skl1/igt@gem_ctx_isolation@preservation-s3@vcs0.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-skl8/igt@gem_ctx_isolation@preservation-s3@vcs0.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [TIMEOUT][109] ([i915#2369] / [i915#3063] / [i915#3648]) -> [PASS][110]
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10706/shard-tglb2/igt@gem_eio@unwedge-stress.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-tglb1/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [FAIL][111] ([i915#2842]) -> [PASS][112] +3 similar issues
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10706/shard-tglb3/igt@gem_exec_fair@basic-flow@rcs0.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-tglb5/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [FAIL][113] ([i915#2842]) -> [PASS][114]
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10706/shard-iclb7/igt@gem_exec_fair@basic-none-share@rcs0.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-iclb8/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl: [SKIP][115] ([fdo#109271]) -> [PASS][116] +1 similar issue
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10706/shard-kbl1/igt@gem_exec_fair@basic-pace@vcs1.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-kbl3/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [FAIL][117] ([i915#2842]) -> [PASS][118]
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10706/shard-glk3/igt@gem_exec_fair@basic-throttle@rcs0.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-glk4/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_sync@basic-many-each:
- shard-iclb: [INCOMPLETE][119] ([i915#4274]) -> [PASS][120]
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10706/shard-iclb8/igt@gem_sync@basic-many-each.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-iclb8/igt@gem_sync@basic-many-each.html
* igt@i915_pm_dc@dc9-dpms:
- shard-iclb: [SKIP][121] -> [PASS][122]
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10706/shard-iclb3/igt@i915_pm_dc@dc9-dpms.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-iclb7/igt@i915_pm_dc@dc9-dpms.html
* igt@kms_big_fb@y-tiled-32bpp-rotate-0:
- shard-glk: [DMESG-WARN][123] ([i915#118]) -> [PASS][124]
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10706/shard-glk2/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-glk1/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html
* igt@kms_color@pipe-a-ctm-0-5:
- shard-skl: [DMESG-WARN][125] ([i915#1982]) -> [PASS][126] +2 similar issues
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10706/shard-skl2/igt@kms_color@pipe-a-ctm-0-5.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-skl5/igt@kms_color@pipe-a-ctm-0-5.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [DMESG-WARN][127] ([i915#180]) -> [PASS][128] +7 similar issues
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10706/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-kbl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_cursor_edge_walk@pipe-a-256x256-top-edge:
- shard-iclb: [DMESG-FAIL][129] ([i915#1226]) -> [PASS][130]
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10706/shard-iclb3/igt@kms_cursor_edge_walk@pipe-a-256x256-top-edge.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-iclb1/igt@kms_cursor_edge_walk@pipe-a-256x256-top-edge.html
* igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1:
- shard-glk: [FAIL][131] ([i915#79]) -> [PASS][132]
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10706/shard-glk7/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-glk2/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
- shard-skl: [FAIL][133] ([i915#2122]) -> [PASS][134]
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10706/shard-skl7/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-skl3/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-glk: [FAIL][135] ([i915#2546]) -> [PASS][136] +1 similar issue
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10706/shard-glk2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/shard-glk1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-wc:
- shard-tglb: [INCOM
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21302/index.html
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^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [PATCH v3 3/5] drm/i915/panelreplay: Initializaton and compute config for panel replay
2021-10-10 12:10 ` [Intel-gfx] " Animesh Manna
@ 2021-10-10 18:21 ` kernel test robot
-1 siblings, 0 replies; 31+ messages in thread
From: kernel test robot @ 2021-10-10 18:21 UTC (permalink / raw)
To: Animesh Manna, intel-gfx, dri-devel
Cc: llvm, kbuild-all, gwan-gyeong.mun, mika.kahola, jani.nikula,
manasi.d.navare, jose.souza, Animesh Manna
[-- Attachment #1: Type: text/plain, Size: 3995 bytes --]
Hi Animesh,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-tip/drm-tip]
[also build test WARNING on next-20211008]
[cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next tegra-drm/drm/tegra/for-next linus/master airlied/drm-next v5.15-rc4]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Animesh-Manna/Panel-replay-phase1-implementation/20211010-203447
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: i386-randconfig-a014-20211010 (attached as .config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 903b30fea21f99d8f48fde4defcc838970e30ee1)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/474a8190321f2836a1fe989326736d19dc9a732b
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Animesh-Manna/Panel-replay-phase1-implementation/20211010-203447
git checkout 474a8190321f2836a1fe989326736d19dc9a732b
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 ARCH=i386
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/i915/display/intel_dp.c:2780:27: warning: overlapping comparisons always evaluate to true [-Wtautological-overlap-compare]
if (vsc->revision != 0x5 || vsc->revision != 0x7)
~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~
1 warning generated.
vim +2780 drivers/gpu/drm/i915/display/intel_dp.c
2756
2757 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
2758 struct dp_sdp *sdp, size_t size)
2759 {
2760 size_t length = sizeof(struct dp_sdp);
2761
2762 if (size < length)
2763 return -ENOSPC;
2764
2765 memset(sdp, 0, size);
2766
2767 /*
2768 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
2769 * VSC SDP Header Bytes
2770 */
2771 sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
2772 sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
2773 sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
2774 sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
2775
2776 /*
2777 * Revision 0x5 and 0x7 supports Pixel Encoding/Colorimetry Format as
2778 * per DP 1.4a spec and DP 2.0 spec respectively.
2779 */
> 2780 if (vsc->revision != 0x5 || vsc->revision != 0x7)
2781 goto out;
2782
2783 /* VSC SDP Payload for DB16 through DB18 */
2784 /* Pixel Encoding and Colorimetry Formats */
2785 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
2786 sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
2787
2788 switch (vsc->bpc) {
2789 case 6:
2790 /* 6bpc: 0x0 */
2791 break;
2792 case 8:
2793 sdp->db[17] = 0x1; /* DB17[3:0] */
2794 break;
2795 case 10:
2796 sdp->db[17] = 0x2;
2797 break;
2798 case 12:
2799 sdp->db[17] = 0x3;
2800 break;
2801 case 16:
2802 sdp->db[17] = 0x4;
2803 break;
2804 default:
2805 MISSING_CASE(vsc->bpc);
2806 break;
2807 }
2808 /* Dynamic Range and Component Bit Depth */
2809 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
2810 sdp->db[17] |= 0x80; /* DB17[7] */
2811
2812 /* Content Type */
2813 sdp->db[18] = vsc->content_type & 0x7;
2814
2815 out:
2816 return length;
2817 }
2818
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 40157 bytes --]
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [PATCH v3 3/5] drm/i915/panelreplay: Initializaton and compute config for panel replay
@ 2021-10-10 18:21 ` kernel test robot
0 siblings, 0 replies; 31+ messages in thread
From: kernel test robot @ 2021-10-10 18:21 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 4102 bytes --]
Hi Animesh,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-tip/drm-tip]
[also build test WARNING on next-20211008]
[cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next tegra-drm/drm/tegra/for-next linus/master airlied/drm-next v5.15-rc4]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Animesh-Manna/Panel-replay-phase1-implementation/20211010-203447
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: i386-randconfig-a014-20211010 (attached as .config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 903b30fea21f99d8f48fde4defcc838970e30ee1)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/474a8190321f2836a1fe989326736d19dc9a732b
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Animesh-Manna/Panel-replay-phase1-implementation/20211010-203447
git checkout 474a8190321f2836a1fe989326736d19dc9a732b
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 ARCH=i386
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/i915/display/intel_dp.c:2780:27: warning: overlapping comparisons always evaluate to true [-Wtautological-overlap-compare]
if (vsc->revision != 0x5 || vsc->revision != 0x7)
~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~
1 warning generated.
vim +2780 drivers/gpu/drm/i915/display/intel_dp.c
2756
2757 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
2758 struct dp_sdp *sdp, size_t size)
2759 {
2760 size_t length = sizeof(struct dp_sdp);
2761
2762 if (size < length)
2763 return -ENOSPC;
2764
2765 memset(sdp, 0, size);
2766
2767 /*
2768 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
2769 * VSC SDP Header Bytes
2770 */
2771 sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
2772 sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
2773 sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
2774 sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
2775
2776 /*
2777 * Revision 0x5 and 0x7 supports Pixel Encoding/Colorimetry Format as
2778 * per DP 1.4a spec and DP 2.0 spec respectively.
2779 */
> 2780 if (vsc->revision != 0x5 || vsc->revision != 0x7)
2781 goto out;
2782
2783 /* VSC SDP Payload for DB16 through DB18 */
2784 /* Pixel Encoding and Colorimetry Formats */
2785 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
2786 sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
2787
2788 switch (vsc->bpc) {
2789 case 6:
2790 /* 6bpc: 0x0 */
2791 break;
2792 case 8:
2793 sdp->db[17] = 0x1; /* DB17[3:0] */
2794 break;
2795 case 10:
2796 sdp->db[17] = 0x2;
2797 break;
2798 case 12:
2799 sdp->db[17] = 0x3;
2800 break;
2801 case 16:
2802 sdp->db[17] = 0x4;
2803 break;
2804 default:
2805 MISSING_CASE(vsc->bpc);
2806 break;
2807 }
2808 /* Dynamic Range and Component Bit Depth */
2809 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
2810 sdp->db[17] |= 0x80; /* DB17[7] */
2811
2812 /* Content Type */
2813 sdp->db[18] = vsc->content_type & 0x7;
2814
2815 out:
2816 return length;
2817 }
2818
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 40157 bytes --]
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [PATCH v3 3/5] drm/i915/panelreplay: Initializaton and compute config for panel replay
2021-10-10 12:10 ` [Intel-gfx] " Animesh Manna
@ 2021-10-10 20:28 ` kernel test robot
-1 siblings, 0 replies; 31+ messages in thread
From: kernel test robot @ 2021-10-10 20:28 UTC (permalink / raw)
To: Animesh Manna, intel-gfx, dri-devel
Cc: llvm, kbuild-all, gwan-gyeong.mun, mika.kahola, jani.nikula,
manasi.d.navare, jose.souza, Animesh Manna
[-- Attachment #1: Type: text/plain, Size: 3989 bytes --]
Hi Animesh,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-tip/drm-tip]
[also build test ERROR on next-20211008]
[cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next tegra-drm/drm/tegra/for-next linus/master airlied/drm-next v5.15-rc4]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Animesh-Manna/Panel-replay-phase1-implementation/20211010-203447
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: i386-randconfig-r014-20211010 (attached as .config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 903b30fea21f99d8f48fde4defcc838970e30ee1)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/474a8190321f2836a1fe989326736d19dc9a732b
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Animesh-Manna/Panel-replay-phase1-implementation/20211010-203447
git checkout 474a8190321f2836a1fe989326736d19dc9a732b
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 ARCH=i386
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> drivers/gpu/drm/i915/display/intel_dp.c:2780:27: error: overlapping comparisons always evaluate to true [-Werror,-Wtautological-overlap-compare]
if (vsc->revision != 0x5 || vsc->revision != 0x7)
~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~
1 error generated.
vim +2780 drivers/gpu/drm/i915/display/intel_dp.c
2756
2757 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
2758 struct dp_sdp *sdp, size_t size)
2759 {
2760 size_t length = sizeof(struct dp_sdp);
2761
2762 if (size < length)
2763 return -ENOSPC;
2764
2765 memset(sdp, 0, size);
2766
2767 /*
2768 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
2769 * VSC SDP Header Bytes
2770 */
2771 sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
2772 sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
2773 sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
2774 sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
2775
2776 /*
2777 * Revision 0x5 and 0x7 supports Pixel Encoding/Colorimetry Format as
2778 * per DP 1.4a spec and DP 2.0 spec respectively.
2779 */
> 2780 if (vsc->revision != 0x5 || vsc->revision != 0x7)
2781 goto out;
2782
2783 /* VSC SDP Payload for DB16 through DB18 */
2784 /* Pixel Encoding and Colorimetry Formats */
2785 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
2786 sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
2787
2788 switch (vsc->bpc) {
2789 case 6:
2790 /* 6bpc: 0x0 */
2791 break;
2792 case 8:
2793 sdp->db[17] = 0x1; /* DB17[3:0] */
2794 break;
2795 case 10:
2796 sdp->db[17] = 0x2;
2797 break;
2798 case 12:
2799 sdp->db[17] = 0x3;
2800 break;
2801 case 16:
2802 sdp->db[17] = 0x4;
2803 break;
2804 default:
2805 MISSING_CASE(vsc->bpc);
2806 break;
2807 }
2808 /* Dynamic Range and Component Bit Depth */
2809 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
2810 sdp->db[17] |= 0x80; /* DB17[7] */
2811
2812 /* Content Type */
2813 sdp->db[18] = vsc->content_type & 0x7;
2814
2815 out:
2816 return length;
2817 }
2818
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 40089 bytes --]
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [PATCH v3 3/5] drm/i915/panelreplay: Initializaton and compute config for panel replay
@ 2021-10-10 20:28 ` kernel test robot
0 siblings, 0 replies; 31+ messages in thread
From: kernel test robot @ 2021-10-10 20:28 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 4096 bytes --]
Hi Animesh,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-tip/drm-tip]
[also build test ERROR on next-20211008]
[cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next tegra-drm/drm/tegra/for-next linus/master airlied/drm-next v5.15-rc4]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Animesh-Manna/Panel-replay-phase1-implementation/20211010-203447
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: i386-randconfig-r014-20211010 (attached as .config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project 903b30fea21f99d8f48fde4defcc838970e30ee1)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/474a8190321f2836a1fe989326736d19dc9a732b
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Animesh-Manna/Panel-replay-phase1-implementation/20211010-203447
git checkout 474a8190321f2836a1fe989326736d19dc9a732b
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 ARCH=i386
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> drivers/gpu/drm/i915/display/intel_dp.c:2780:27: error: overlapping comparisons always evaluate to true [-Werror,-Wtautological-overlap-compare]
if (vsc->revision != 0x5 || vsc->revision != 0x7)
~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~
1 error generated.
vim +2780 drivers/gpu/drm/i915/display/intel_dp.c
2756
2757 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
2758 struct dp_sdp *sdp, size_t size)
2759 {
2760 size_t length = sizeof(struct dp_sdp);
2761
2762 if (size < length)
2763 return -ENOSPC;
2764
2765 memset(sdp, 0, size);
2766
2767 /*
2768 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
2769 * VSC SDP Header Bytes
2770 */
2771 sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
2772 sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
2773 sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
2774 sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
2775
2776 /*
2777 * Revision 0x5 and 0x7 supports Pixel Encoding/Colorimetry Format as
2778 * per DP 1.4a spec and DP 2.0 spec respectively.
2779 */
> 2780 if (vsc->revision != 0x5 || vsc->revision != 0x7)
2781 goto out;
2782
2783 /* VSC SDP Payload for DB16 through DB18 */
2784 /* Pixel Encoding and Colorimetry Formats */
2785 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
2786 sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
2787
2788 switch (vsc->bpc) {
2789 case 6:
2790 /* 6bpc: 0x0 */
2791 break;
2792 case 8:
2793 sdp->db[17] = 0x1; /* DB17[3:0] */
2794 break;
2795 case 10:
2796 sdp->db[17] = 0x2;
2797 break;
2798 case 12:
2799 sdp->db[17] = 0x3;
2800 break;
2801 case 16:
2802 sdp->db[17] = 0x4;
2803 break;
2804 default:
2805 MISSING_CASE(vsc->bpc);
2806 break;
2807 }
2808 /* Dynamic Range and Component Bit Depth */
2809 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
2810 sdp->db[17] |= 0x80; /* DB17[7] */
2811
2812 /* Content Type */
2813 sdp->db[18] = vsc->content_type & 0x7;
2814
2815 out:
2816 return length;
2817 }
2818
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org
[-- Attachment #2: config.gz --]
[-- Type: application/gzip, Size: 40089 bytes --]
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v3 1/5] drm/i915/panelreplay: dpcd register definition for panelreplay
2021-10-10 12:10 ` [Intel-gfx] " Animesh Manna
@ 2021-11-23 19:37 ` Souza, Jose
-1 siblings, 0 replies; 31+ messages in thread
From: Souza, Jose @ 2021-11-23 19:37 UTC (permalink / raw)
To: dri-devel, Manna, Animesh, intel-gfx
Cc: Nikula, Jani, Navare, Manasi D, Kahola, Mika, Mun, Gwan-gyeong
On Sun, 2021-10-10 at 17:40 +0530, Animesh Manna wrote:
> DPCD register definition added to check and enable panel replay
> capability of the sink.
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
> include/drm/drm_dp_helper.h | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index b52df4db3e8f..8a2b929c3f88 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -541,6 +541,9 @@ struct drm_panel;
> /* DFP Capability Extension */
> #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
>
> +#define DP_PANEL_REPLAY_CAP 0x0b0
> +# define PANEL_REPLAY_SUPPORT (1 << 0)
Missing bit 1, that is very important when panel do not support selective update panel replay needs to act like PSR1 when it is sets it needs to act
like PSR2.
> +
> /* Link Configuration */
> #define DP_LINK_BW_SET 0x100
> # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
> @@ -709,6 +712,9 @@ struct drm_panel;
> #define DP_BRANCH_DEVICE_CTRL 0x1a1
> # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0)
>
> +#define PANEL_REPLAY_CONFIG 0x1b0
> +# define PANEL_REPLAY_ENABLE (1 << 0)
All other bits are also important, for the errors ones we have PSR counter parts and your are missing the error status register.
> +
> #define DP_PAYLOAD_ALLOCATE_SET 0x1c0
> #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
> #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [PATCH v3 1/5] drm/i915/panelreplay: dpcd register definition for panelreplay
@ 2021-11-23 19:37 ` Souza, Jose
0 siblings, 0 replies; 31+ messages in thread
From: Souza, Jose @ 2021-11-23 19:37 UTC (permalink / raw)
To: dri-devel, Manna, Animesh, intel-gfx; +Cc: Nikula, Jani
On Sun, 2021-10-10 at 17:40 +0530, Animesh Manna wrote:
> DPCD register definition added to check and enable panel replay
> capability of the sink.
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
> include/drm/drm_dp_helper.h | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index b52df4db3e8f..8a2b929c3f88 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -541,6 +541,9 @@ struct drm_panel;
> /* DFP Capability Extension */
> #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
>
> +#define DP_PANEL_REPLAY_CAP 0x0b0
> +# define PANEL_REPLAY_SUPPORT (1 << 0)
Missing bit 1, that is very important when panel do not support selective update panel replay needs to act like PSR1 when it is sets it needs to act
like PSR2.
> +
> /* Link Configuration */
> #define DP_LINK_BW_SET 0x100
> # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
> @@ -709,6 +712,9 @@ struct drm_panel;
> #define DP_BRANCH_DEVICE_CTRL 0x1a1
> # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0)
>
> +#define PANEL_REPLAY_CONFIG 0x1b0
> +# define PANEL_REPLAY_ENABLE (1 << 0)
All other bits are also important, for the errors ones we have PSR counter parts and your are missing the error status register.
> +
> #define DP_PAYLOAD_ALLOCATE_SET 0x1c0
> #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1
> #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v3 3/5] drm/i915/panelreplay: Initializaton and compute config for panel replay
2021-10-10 12:10 ` [Intel-gfx] " Animesh Manna
@ 2021-11-23 19:48 ` Souza, Jose
-1 siblings, 0 replies; 31+ messages in thread
From: Souza, Jose @ 2021-11-23 19:48 UTC (permalink / raw)
To: dri-devel, Manna, Animesh, intel-gfx
Cc: Nikula, Jani, Navare, Manasi D, Kahola, Mika, Mun, Gwan-gyeong
On Sun, 2021-10-10 at 17:40 +0530, Animesh Manna wrote:
> As panel replay feature similar to PSR feature of EDP panel, so currently
> utilized existing psr framework for panel replay.
>
> v1: RFC version.
> v2: optimized code, pr_enabled and pr_dpcd variable removed. [Jose]
> v3:
> - code comments improved. [Jani]
> - dpcd_readb used instead of dpcd_read. [Jani]
> - panel-repaplay init/compute functions moved inside respective psr
> function. [Jani]
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
> .../drm/i915/display/intel_display_types.h | 2 +
> drivers/gpu/drm/i915/display/intel_dp.c | 43 +++++++++++++----
> drivers/gpu/drm/i915/display/intel_psr.c | 48 +++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_psr.h | 3 ++
> 4 files changed, 87 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 39e11eaec1a3..48f7d676ed2c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1070,6 +1070,7 @@ struct intel_crtc_state {
> bool req_psr2_sdp_prior_scanline;
> u32 dc3co_exitline;
> u16 su_y_granularity;
> + bool has_panel_replay;
We can drop this and reuse current ones ones, see bellow.
> struct drm_dp_vsc_sdp psr_vsc;
>
> /*
> @@ -1531,6 +1532,7 @@ struct intel_psr {
> bool irq_aux_error;
> u16 su_w_granularity;
> u16 su_y_granularity;
> + bool sink_panel_replay_support;
move this closer to has_psr and set both when it is panel replay.
otherwise psr functions will not be executed for panel replay, see CAN_PSR().
> u32 dc3co_exitline;
> u32 dc3co_exit_delay;
> struct delayed_work dc3co_work;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 10fda20a5bd8..f58a7b72be14 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1587,12 +1587,22 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> - /*
> - * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> - * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> - * Colorimetry Format indication.
> - */
> - vsc->revision = 0x5;
> + if (crtc_state->has_panel_replay) {
> + /*
> + * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
> + * VSC SDP supporting 3D stereo, Panel Replay, and Pixel
> + * Encoding/Colorimetry Format indication.
> + */
> + vsc->revision = 0x7;
> + } else {
> + /*
> + * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> + * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> + * Colorimetry Format indication.
> + */
> + vsc->revision = 0x5;
> + }
> +
> vsc->length = 0x13;
>
> /* DP 1.4a spec, Table 2-120 */
> @@ -1701,6 +1711,21 @@ void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
> vsc->revision = 0x4;
> vsc->length = 0xe;
> }
> + } else if (intel_dp->psr.enabled && !intel_dp_is_edp(intel_dp)) {
> + if (intel_dp->psr.colorimetry_support &&
> + intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> + /* [Panel Replay with colorimetry info] */
> + intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
> + vsc);
> + } else {
> + /*
> + * [Panel Replay without colorimetry info]
> + * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
> + * VSC SDP supporting 3D stereo + Panel Replay.
> + */
> + vsc->revision = 0x6;
> + vsc->length = 0x10;
> + }
> } else {
> /*
> * [PSR1]
> @@ -2749,10 +2774,10 @@ static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
> sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
>
> /*
> - * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
> - * per DP 1.4a spec.
> + * Revision 0x5 and 0x7 supports Pixel Encoding/Colorimetry Format as
> + * per DP 1.4a spec and DP 2.0 spec respectively.
> */
> - if (vsc->revision != 0x5)
> + if (vsc->revision != 0x5 || vsc->revision != 0x7)
> goto out;
>
> /* VSC SDP Payload for DB16 through DB18 */
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 7a205fd5023b..91c2efe2f3ad 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -933,6 +933,21 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
> return true;
> }
>
> +void intel_panel_replay_compute_config(struct intel_dp *intel_dp,
> + struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> +
> + if (!intel_dp->psr.sink_panel_replay_support)
> + return;
> +
> + crtc_state->has_panel_replay = true;
> + crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
> +
> + if (HAS_PSR2_SEL_FETCH(i915))
> + intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state);
> +}
> +
> void intel_psr_compute_config(struct intel_dp *intel_dp,
> struct intel_crtc_state *crtc_state,
> struct drm_connector_state *conn_state)
> @@ -942,6 +957,8 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
> &crtc_state->hw.adjusted_mode;
> int psr_setup_time;
>
> + intel_panel_replay_compute_config(intel_dp, crtc_state);
have you checked if the other PSR are needed for panel replay? what about the psr2 checks? when using panel replay selective update some additional
tests will be needed regarding granularity...
> +
> /*
> * Current PSR panels dont work reliably with VRR enabled
> * So if VRR is enabled, do not enable PSR.
> @@ -2170,6 +2187,35 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
> }
> }
>
> +/**
> + * intel_panel_replay_init - Check for sink and source capability.
> + * @intel_dp: Intel DP
> + *
> + * This function is called after the initializing connector.
> + * (the initializing of connector treats the handling of connector capabilities)
> + * And it initializes basic panel replay stuff for each DP Encoder.
> + */
> +void intel_panel_replay_init(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + u8 pr_dpcd = 0;
> +
> + if (!(HAS_DP20(dev_priv) && HAS_PANEL_REPLAY(dev_priv)))
> + return;
> +
> + drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP, &pr_dpcd);
> +
> + if (!(pr_dpcd & PANEL_REPLAY_SUPPORT)) {
> + drm_dbg_kms(&dev_priv->drm,
> + "Panel replay is not supported by panel\n");
> + return;
> + }
> +
> + drm_dbg_kms(&dev_priv->drm,
> + "Panel replay is supported by panel\n");
> + intel_dp->psr.sink_panel_replay_support = true;
> +}
> +
> /**
> * intel_psr_init - Init basic PSR work and mutex.
> * @intel_dp: Intel DP
> @@ -2183,6 +2229,8 @@ void intel_psr_init(struct intel_dp *intel_dp)
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>
> + intel_panel_replay_init(intel_dp);
> +
> if (!HAS_PSR(dev_priv))
> return;
mutex initialization is not executed, workers not initialized...
please go more carefully trough every PSR function and check what are the panel replay implications
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
> index facffbacd357..c9d1c1f0b470 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -32,6 +32,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
> unsigned frontbuffer_bits,
> enum fb_op_origin origin);
> void intel_psr_init(struct intel_dp *intel_dp);
> +void intel_panel_replay_init(struct intel_dp *intel_dp);
> void intel_psr_compute_config(struct intel_dp *intel_dp,
> struct intel_crtc_state *crtc_state,
> struct drm_connector_state *conn_state);
> @@ -52,5 +53,7 @@ void intel_psr2_disable_plane_sel_fetch(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state);
> void intel_psr_pause(struct intel_dp *intel_dp);
> void intel_psr_resume(struct intel_dp *intel_dp);
> +void intel_panel_replay_compute_config(struct intel_dp *intel_dp,
> + struct intel_crtc_state *crtc_state);
>
> #endif /* __INTEL_PSR_H__ */
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [PATCH v3 3/5] drm/i915/panelreplay: Initializaton and compute config for panel replay
@ 2021-11-23 19:48 ` Souza, Jose
0 siblings, 0 replies; 31+ messages in thread
From: Souza, Jose @ 2021-11-23 19:48 UTC (permalink / raw)
To: dri-devel, Manna, Animesh, intel-gfx; +Cc: Nikula, Jani
On Sun, 2021-10-10 at 17:40 +0530, Animesh Manna wrote:
> As panel replay feature similar to PSR feature of EDP panel, so currently
> utilized existing psr framework for panel replay.
>
> v1: RFC version.
> v2: optimized code, pr_enabled and pr_dpcd variable removed. [Jose]
> v3:
> - code comments improved. [Jani]
> - dpcd_readb used instead of dpcd_read. [Jani]
> - panel-repaplay init/compute functions moved inside respective psr
> function. [Jani]
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> ---
> .../drm/i915/display/intel_display_types.h | 2 +
> drivers/gpu/drm/i915/display/intel_dp.c | 43 +++++++++++++----
> drivers/gpu/drm/i915/display/intel_psr.c | 48 +++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_psr.h | 3 ++
> 4 files changed, 87 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 39e11eaec1a3..48f7d676ed2c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1070,6 +1070,7 @@ struct intel_crtc_state {
> bool req_psr2_sdp_prior_scanline;
> u32 dc3co_exitline;
> u16 su_y_granularity;
> + bool has_panel_replay;
We can drop this and reuse current ones ones, see bellow.
> struct drm_dp_vsc_sdp psr_vsc;
>
> /*
> @@ -1531,6 +1532,7 @@ struct intel_psr {
> bool irq_aux_error;
> u16 su_w_granularity;
> u16 su_y_granularity;
> + bool sink_panel_replay_support;
move this closer to has_psr and set both when it is panel replay.
otherwise psr functions will not be executed for panel replay, see CAN_PSR().
> u32 dc3co_exitline;
> u32 dc3co_exit_delay;
> struct delayed_work dc3co_work;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 10fda20a5bd8..f58a7b72be14 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -1587,12 +1587,22 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> - /*
> - * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> - * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> - * Colorimetry Format indication.
> - */
> - vsc->revision = 0x5;
> + if (crtc_state->has_panel_replay) {
> + /*
> + * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
> + * VSC SDP supporting 3D stereo, Panel Replay, and Pixel
> + * Encoding/Colorimetry Format indication.
> + */
> + vsc->revision = 0x7;
> + } else {
> + /*
> + * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> + * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> + * Colorimetry Format indication.
> + */
> + vsc->revision = 0x5;
> + }
> +
> vsc->length = 0x13;
>
> /* DP 1.4a spec, Table 2-120 */
> @@ -1701,6 +1711,21 @@ void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
> vsc->revision = 0x4;
> vsc->length = 0xe;
> }
> + } else if (intel_dp->psr.enabled && !intel_dp_is_edp(intel_dp)) {
> + if (intel_dp->psr.colorimetry_support &&
> + intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> + /* [Panel Replay with colorimetry info] */
> + intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
> + vsc);
> + } else {
> + /*
> + * [Panel Replay without colorimetry info]
> + * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
> + * VSC SDP supporting 3D stereo + Panel Replay.
> + */
> + vsc->revision = 0x6;
> + vsc->length = 0x10;
> + }
> } else {
> /*
> * [PSR1]
> @@ -2749,10 +2774,10 @@ static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
> sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
>
> /*
> - * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
> - * per DP 1.4a spec.
> + * Revision 0x5 and 0x7 supports Pixel Encoding/Colorimetry Format as
> + * per DP 1.4a spec and DP 2.0 spec respectively.
> */
> - if (vsc->revision != 0x5)
> + if (vsc->revision != 0x5 || vsc->revision != 0x7)
> goto out;
>
> /* VSC SDP Payload for DB16 through DB18 */
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 7a205fd5023b..91c2efe2f3ad 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -933,6 +933,21 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
> return true;
> }
>
> +void intel_panel_replay_compute_config(struct intel_dp *intel_dp,
> + struct intel_crtc_state *crtc_state)
> +{
> + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> +
> + if (!intel_dp->psr.sink_panel_replay_support)
> + return;
> +
> + crtc_state->has_panel_replay = true;
> + crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
> +
> + if (HAS_PSR2_SEL_FETCH(i915))
> + intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state);
> +}
> +
> void intel_psr_compute_config(struct intel_dp *intel_dp,
> struct intel_crtc_state *crtc_state,
> struct drm_connector_state *conn_state)
> @@ -942,6 +957,8 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
> &crtc_state->hw.adjusted_mode;
> int psr_setup_time;
>
> + intel_panel_replay_compute_config(intel_dp, crtc_state);
have you checked if the other PSR are needed for panel replay? what about the psr2 checks? when using panel replay selective update some additional
tests will be needed regarding granularity...
> +
> /*
> * Current PSR panels dont work reliably with VRR enabled
> * So if VRR is enabled, do not enable PSR.
> @@ -2170,6 +2187,35 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
> }
> }
>
> +/**
> + * intel_panel_replay_init - Check for sink and source capability.
> + * @intel_dp: Intel DP
> + *
> + * This function is called after the initializing connector.
> + * (the initializing of connector treats the handling of connector capabilities)
> + * And it initializes basic panel replay stuff for each DP Encoder.
> + */
> +void intel_panel_replay_init(struct intel_dp *intel_dp)
> +{
> + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> + u8 pr_dpcd = 0;
> +
> + if (!(HAS_DP20(dev_priv) && HAS_PANEL_REPLAY(dev_priv)))
> + return;
> +
> + drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP, &pr_dpcd);
> +
> + if (!(pr_dpcd & PANEL_REPLAY_SUPPORT)) {
> + drm_dbg_kms(&dev_priv->drm,
> + "Panel replay is not supported by panel\n");
> + return;
> + }
> +
> + drm_dbg_kms(&dev_priv->drm,
> + "Panel replay is supported by panel\n");
> + intel_dp->psr.sink_panel_replay_support = true;
> +}
> +
> /**
> * intel_psr_init - Init basic PSR work and mutex.
> * @intel_dp: Intel DP
> @@ -2183,6 +2229,8 @@ void intel_psr_init(struct intel_dp *intel_dp)
> struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>
> + intel_panel_replay_init(intel_dp);
> +
> if (!HAS_PSR(dev_priv))
> return;
mutex initialization is not executed, workers not initialized...
please go more carefully trough every PSR function and check what are the panel replay implications
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
> index facffbacd357..c9d1c1f0b470 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -32,6 +32,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
> unsigned frontbuffer_bits,
> enum fb_op_origin origin);
> void intel_psr_init(struct intel_dp *intel_dp);
> +void intel_panel_replay_init(struct intel_dp *intel_dp);
> void intel_psr_compute_config(struct intel_dp *intel_dp,
> struct intel_crtc_state *crtc_state,
> struct drm_connector_state *conn_state);
> @@ -52,5 +53,7 @@ void intel_psr2_disable_plane_sel_fetch(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state);
> void intel_psr_pause(struct intel_dp *intel_dp);
> void intel_psr_resume(struct intel_dp *intel_dp);
> +void intel_panel_replay_compute_config(struct intel_dp *intel_dp,
> + struct intel_crtc_state *crtc_state);
>
> #endif /* __INTEL_PSR_H__ */
^ permalink raw reply [flat|nested] 31+ messages in thread
* RE: [PATCH v3 1/5] drm/i915/panelreplay: dpcd register definition for panelreplay
2021-11-23 19:37 ` [Intel-gfx] " Souza, Jose
@ 2022-01-04 15:51 ` Manna, Animesh
-1 siblings, 0 replies; 31+ messages in thread
From: Manna, Animesh @ 2022-01-04 15:51 UTC (permalink / raw)
To: Souza, Jose, dri-devel, intel-gfx
Cc: Nikula, Jani, Navare, Manasi D, Kahola, Mika, Mun, Gwan-gyeong
> -----Original Message-----
> From: Souza, Jose <jose.souza@intel.com>
> Sent: Wednesday, November 24, 2021 1:07 AM
> To: dri-devel@lists.freedesktop.org; Manna, Animesh
> <animesh.manna@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Mun, Gwan-gyeong <gwan-gyeong.mun@intel.com>; Nikula, Jani
> <jani.nikula@intel.com>; Kahola, Mika <mika.kahola@intel.com>; Navare,
> Manasi D <manasi.d.navare@intel.com>
> Subject: Re: [PATCH v3 1/5] drm/i915/panelreplay: dpcd register definition for
> panelreplay
>
> On Sun, 2021-10-10 at 17:40 +0530, Animesh Manna wrote:
> > DPCD register definition added to check and enable panel replay
> > capability of the sink.
> >
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> > include/drm/drm_dp_helper.h | 6 ++++++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> > index b52df4db3e8f..8a2b929c3f88 100644
> > --- a/include/drm/drm_dp_helper.h
> > +++ b/include/drm/drm_dp_helper.h
> > @@ -541,6 +541,9 @@ struct drm_panel;
> > /* DFP Capability Extension */
> > #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> >
> > +#define DP_PANEL_REPLAY_CAP 0x0b0
> > +# define PANEL_REPLAY_SUPPORT (1 << 0)
>
> Missing bit 1, that is very important when panel do not support selective update
> panel replay needs to act like PSR1 when it is sets it needs to act like PSR2.
>
> > +
> > /* Link Configuration */
> > #define DP_LINK_BW_SET 0x100
> > # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
> > @@ -709,6 +712,9 @@ struct drm_panel;
> > #define DP_BRANCH_DEVICE_CTRL 0x1a1
> > # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0)
> >
> > +#define PANEL_REPLAY_CONFIG 0x1b0
> > +# define PANEL_REPLAY_ENABLE (1 << 0)
>
> All other bits are also important, for the errors ones we have PSR counter parts
> and your are missing the error status register.
Thanks for review.
Added the suggested changes in current version.
Regards,
Animesh
>
> > +
> > #define DP_PAYLOAD_ALLOCATE_SET 0x1c0
> > #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1 #define
> > DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [PATCH v3 1/5] drm/i915/panelreplay: dpcd register definition for panelreplay
@ 2022-01-04 15:51 ` Manna, Animesh
0 siblings, 0 replies; 31+ messages in thread
From: Manna, Animesh @ 2022-01-04 15:51 UTC (permalink / raw)
To: Souza, Jose, dri-devel, intel-gfx; +Cc: Nikula, Jani
> -----Original Message-----
> From: Souza, Jose <jose.souza@intel.com>
> Sent: Wednesday, November 24, 2021 1:07 AM
> To: dri-devel@lists.freedesktop.org; Manna, Animesh
> <animesh.manna@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Mun, Gwan-gyeong <gwan-gyeong.mun@intel.com>; Nikula, Jani
> <jani.nikula@intel.com>; Kahola, Mika <mika.kahola@intel.com>; Navare,
> Manasi D <manasi.d.navare@intel.com>
> Subject: Re: [PATCH v3 1/5] drm/i915/panelreplay: dpcd register definition for
> panelreplay
>
> On Sun, 2021-10-10 at 17:40 +0530, Animesh Manna wrote:
> > DPCD register definition added to check and enable panel replay
> > capability of the sink.
> >
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> > include/drm/drm_dp_helper.h | 6 ++++++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> > index b52df4db3e8f..8a2b929c3f88 100644
> > --- a/include/drm/drm_dp_helper.h
> > +++ b/include/drm/drm_dp_helper.h
> > @@ -541,6 +541,9 @@ struct drm_panel;
> > /* DFP Capability Extension */
> > #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */
> >
> > +#define DP_PANEL_REPLAY_CAP 0x0b0
> > +# define PANEL_REPLAY_SUPPORT (1 << 0)
>
> Missing bit 1, that is very important when panel do not support selective update
> panel replay needs to act like PSR1 when it is sets it needs to act like PSR2.
>
> > +
> > /* Link Configuration */
> > #define DP_LINK_BW_SET 0x100
> > # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */
> > @@ -709,6 +712,9 @@ struct drm_panel;
> > #define DP_BRANCH_DEVICE_CTRL 0x1a1
> > # define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0)
> >
> > +#define PANEL_REPLAY_CONFIG 0x1b0
> > +# define PANEL_REPLAY_ENABLE (1 << 0)
>
> All other bits are also important, for the errors ones we have PSR counter parts
> and your are missing the error status register.
Thanks for review.
Added the suggested changes in current version.
Regards,
Animesh
>
> > +
> > #define DP_PAYLOAD_ALLOCATE_SET 0x1c0
> > #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1 #define
> > DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2
^ permalink raw reply [flat|nested] 31+ messages in thread
* RE: [PATCH v3 3/5] drm/i915/panelreplay: Initializaton and compute config for panel replay
2021-11-23 19:48 ` [Intel-gfx] " Souza, Jose
@ 2022-01-04 15:51 ` Manna, Animesh
-1 siblings, 0 replies; 31+ messages in thread
From: Manna, Animesh @ 2022-01-04 15:51 UTC (permalink / raw)
To: Souza, Jose, dri-devel, intel-gfx
Cc: Nikula, Jani, Navare, Manasi D, Kahola, Mika, Mun, Gwan-gyeong
Hi,
> -----Original Message-----
> From: Souza, Jose <jose.souza@intel.com>
> Sent: Wednesday, November 24, 2021 1:19 AM
> To: dri-devel@lists.freedesktop.org; Manna, Animesh
> <animesh.manna@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Mun, Gwan-gyeong <gwan-gyeong.mun@intel.com>; Nikula, Jani
> <jani.nikula@intel.com>; Kahola, Mika <mika.kahola@intel.com>; Navare,
> Manasi D <manasi.d.navare@intel.com>
> Subject: Re: [PATCH v3 3/5] drm/i915/panelreplay: Initializaton and compute
> config for panel replay
>
> On Sun, 2021-10-10 at 17:40 +0530, Animesh Manna wrote:
> > As panel replay feature similar to PSR feature of EDP panel, so
> > currently utilized existing psr framework for panel replay.
> >
> > v1: RFC version.
> > v2: optimized code, pr_enabled and pr_dpcd variable removed. [Jose]
> > v3:
> > - code comments improved. [Jani]
> > - dpcd_readb used instead of dpcd_read. [Jani]
> > - panel-repaplay init/compute functions moved inside respective psr
> > function. [Jani]
> >
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> > .../drm/i915/display/intel_display_types.h | 2 +
> > drivers/gpu/drm/i915/display/intel_dp.c | 43 +++++++++++++----
> > drivers/gpu/drm/i915/display/intel_psr.c | 48 +++++++++++++++++++
> > drivers/gpu/drm/i915/display/intel_psr.h | 3 ++
> > 4 files changed, 87 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 39e11eaec1a3..48f7d676ed2c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1070,6 +1070,7 @@ struct intel_crtc_state {
> > bool req_psr2_sdp_prior_scanline;
> > u32 dc3co_exitline;
> > u16 su_y_granularity;
> > + bool has_panel_replay;
>
> We can drop this and reuse current ones ones, see bellow.
>
> > struct drm_dp_vsc_sdp psr_vsc;
> >
> > /*
> > @@ -1531,6 +1532,7 @@ struct intel_psr {
> > bool irq_aux_error;
> > u16 su_w_granularity;
> > u16 su_y_granularity;
> > + bool sink_panel_replay_support;
>
> move this closer to has_psr and set both when it is panel replay.
> otherwise psr functions will not be executed for panel replay, see CAN_PSR().
AFIU Panel replay do not have any dependency with PSR.
So that’s why I have created separate function for panel replay which is doing similar thing whatever needed for panel replay.
For example intel_panel_replay_compute_config() can be independent of intel_psr_compute_config().
Do you see any dependency with PSR for panel replay?
>
> > u32 dc3co_exitline;
> > u32 dc3co_exit_delay;
> > struct delayed_work dc3co_work;
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 10fda20a5bd8..f58a7b72be14 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -1587,12 +1587,22 @@ static void
> intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >
> > - /*
> > - * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> > - * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> > - * Colorimetry Format indication.
> > - */
> > - vsc->revision = 0x5;
> > + if (crtc_state->has_panel_replay) {
> > + /*
> > + * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
> > + * VSC SDP supporting 3D stereo, Panel Replay, and Pixel
> > + * Encoding/Colorimetry Format indication.
> > + */
> > + vsc->revision = 0x7;
> > + } else {
> > + /*
> > + * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> > + * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> > + * Colorimetry Format indication.
> > + */
> > + vsc->revision = 0x5;
> > + }
> > +
> > vsc->length = 0x13;
> >
> > /* DP 1.4a spec, Table 2-120 */
> > @@ -1701,6 +1711,21 @@ void intel_dp_compute_psr_vsc_sdp(struct
> intel_dp *intel_dp,
> > vsc->revision = 0x4;
> > vsc->length = 0xe;
> > }
> > + } else if (intel_dp->psr.enabled && !intel_dp_is_edp(intel_dp)) {
> > + if (intel_dp->psr.colorimetry_support &&
> > + intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> > + /* [Panel Replay with colorimetry info] */
> > + intel_dp_compute_vsc_colorimetry(crtc_state,
> conn_state,
> > + vsc);
> > + } else {
> > + /*
> > + * [Panel Replay without colorimetry info]
> > + * Prepare VSC Header for SU as per DP 2.0 spec, Table
> 2-223
> > + * VSC SDP supporting 3D stereo + Panel Replay.
> > + */
> > + vsc->revision = 0x6;
> > + vsc->length = 0x10;
> > + }
> > } else {
> > /*
> > * [PSR1]
> > @@ -2749,10 +2774,10 @@ static ssize_t intel_dp_vsc_sdp_pack(const struct
> drm_dp_vsc_sdp *vsc,
> > sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
> >
> > /*
> > - * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
> > - * per DP 1.4a spec.
> > + * Revision 0x5 and 0x7 supports Pixel Encoding/Colorimetry Format as
> > + * per DP 1.4a spec and DP 2.0 spec respectively.
> > */
> > - if (vsc->revision != 0x5)
> > + if (vsc->revision != 0x5 || vsc->revision != 0x7)
> > goto out;
> >
> > /* VSC SDP Payload for DB16 through DB18 */ diff --git
> > a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 7a205fd5023b..91c2efe2f3ad 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -933,6 +933,21 @@ static bool intel_psr2_config_valid(struct intel_dp
> *intel_dp,
> > return true;
> > }
> >
> > +void intel_panel_replay_compute_config(struct intel_dp *intel_dp,
> > + struct intel_crtc_state *crtc_state) {
> > + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> > +
> > + if (!intel_dp->psr.sink_panel_replay_support)
> > + return;
> > +
> > + crtc_state->has_panel_replay = true;
> > + crtc_state->infoframes.enable |=
> > +intel_hdmi_infoframe_enable(DP_SDP_VSC);
> > +
> > + if (HAS_PSR2_SEL_FETCH(i915))
> > + intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state); }
> > +
> > void intel_psr_compute_config(struct intel_dp *intel_dp,
> > struct intel_crtc_state *crtc_state,
> > struct drm_connector_state *conn_state) @@ -
> 942,6 +957,8 @@
> > void intel_psr_compute_config(struct intel_dp *intel_dp,
> > &crtc_state->hw.adjusted_mode;
> > int psr_setup_time;
> >
> > + intel_panel_replay_compute_config(intel_dp, crtc_state);
>
> have you checked if the other PSR are needed for panel replay? what about the
> psr2 checks? when using panel replay selective update some additional tests will
> be needed regarding granularity...
As mentioned above I understood panel replay do not have any dependency with PSR.
Will not target panel replay selective update for dg2.
>
> > +
> > /*
> > * Current PSR panels dont work reliably with VRR enabled
> > * So if VRR is enabled, do not enable PSR.
> > @@ -2170,6 +2187,35 @@ void intel_psr_flush(struct drm_i915_private
> *dev_priv,
> > }
> > }
> >
> > +/**
> > + * intel_panel_replay_init - Check for sink and source capability.
> > + * @intel_dp: Intel DP
> > + *
> > + * This function is called after the initializing connector.
> > + * (the initializing of connector treats the handling of connector
> > +capabilities)
> > + * And it initializes basic panel replay stuff for each DP Encoder.
> > + */
> > +void intel_panel_replay_init(struct intel_dp *intel_dp) {
> > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > + u8 pr_dpcd = 0;
> > +
> > + if (!(HAS_DP20(dev_priv) && HAS_PANEL_REPLAY(dev_priv)))
> > + return;
> > +
> > + drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP,
> &pr_dpcd);
> > +
> > + if (!(pr_dpcd & PANEL_REPLAY_SUPPORT)) {
> > + drm_dbg_kms(&dev_priv->drm,
> > + "Panel replay is not supported by panel\n");
> > + return;
> > + }
> > +
> > + drm_dbg_kms(&dev_priv->drm,
> > + "Panel replay is supported by panel\n");
> > + intel_dp->psr.sink_panel_replay_support = true; }
> > +
> > /**
> > * intel_psr_init - Init basic PSR work and mutex.
> > * @intel_dp: Intel DP
> > @@ -2183,6 +2229,8 @@ void intel_psr_init(struct intel_dp *intel_dp)
> > struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> >
> > + intel_panel_replay_init(intel_dp);
> > +
> > if (!HAS_PSR(dev_priv))
> > return;
>
> mutex initialization is not executed, workers not initialized...
> please go more carefully trough every PSR function and check what are the
> panel replay implications
Tried to double check once more.
Currently as per bspec and dp 2.0 spec did not see any dependency with PSR.
Not sure if we really need worker thread to enter in panel replay mode unlike psr where we need to wait for few idle frames.
Any suggestion/input will be helpful here.
Regards,
Animesh
>
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> > b/drivers/gpu/drm/i915/display/intel_psr.h
> > index facffbacd357..c9d1c1f0b470 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.h
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> > @@ -32,6 +32,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
> > unsigned frontbuffer_bits,
> > enum fb_op_origin origin);
> > void intel_psr_init(struct intel_dp *intel_dp);
> > +void intel_panel_replay_init(struct intel_dp *intel_dp);
> > void intel_psr_compute_config(struct intel_dp *intel_dp,
> > struct intel_crtc_state *crtc_state,
> > struct drm_connector_state *conn_state); @@ -
> 52,5 +53,7 @@
> > void intel_psr2_disable_plane_sel_fetch(struct intel_plane *plane,
> > const struct intel_crtc_state
> *crtc_state); void
> > intel_psr_pause(struct intel_dp *intel_dp); void
> > intel_psr_resume(struct intel_dp *intel_dp);
> > +void intel_panel_replay_compute_config(struct intel_dp *intel_dp,
> > + struct intel_crtc_state *crtc_state);
> >
> > #endif /* __INTEL_PSR_H__ */
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [PATCH v3 3/5] drm/i915/panelreplay: Initializaton and compute config for panel replay
@ 2022-01-04 15:51 ` Manna, Animesh
0 siblings, 0 replies; 31+ messages in thread
From: Manna, Animesh @ 2022-01-04 15:51 UTC (permalink / raw)
To: Souza, Jose, dri-devel, intel-gfx; +Cc: Nikula, Jani
Hi,
> -----Original Message-----
> From: Souza, Jose <jose.souza@intel.com>
> Sent: Wednesday, November 24, 2021 1:19 AM
> To: dri-devel@lists.freedesktop.org; Manna, Animesh
> <animesh.manna@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Mun, Gwan-gyeong <gwan-gyeong.mun@intel.com>; Nikula, Jani
> <jani.nikula@intel.com>; Kahola, Mika <mika.kahola@intel.com>; Navare,
> Manasi D <manasi.d.navare@intel.com>
> Subject: Re: [PATCH v3 3/5] drm/i915/panelreplay: Initializaton and compute
> config for panel replay
>
> On Sun, 2021-10-10 at 17:40 +0530, Animesh Manna wrote:
> > As panel replay feature similar to PSR feature of EDP panel, so
> > currently utilized existing psr framework for panel replay.
> >
> > v1: RFC version.
> > v2: optimized code, pr_enabled and pr_dpcd variable removed. [Jose]
> > v3:
> > - code comments improved. [Jani]
> > - dpcd_readb used instead of dpcd_read. [Jani]
> > - panel-repaplay init/compute functions moved inside respective psr
> > function. [Jani]
> >
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > ---
> > .../drm/i915/display/intel_display_types.h | 2 +
> > drivers/gpu/drm/i915/display/intel_dp.c | 43 +++++++++++++----
> > drivers/gpu/drm/i915/display/intel_psr.c | 48 +++++++++++++++++++
> > drivers/gpu/drm/i915/display/intel_psr.h | 3 ++
> > 4 files changed, 87 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 39e11eaec1a3..48f7d676ed2c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1070,6 +1070,7 @@ struct intel_crtc_state {
> > bool req_psr2_sdp_prior_scanline;
> > u32 dc3co_exitline;
> > u16 su_y_granularity;
> > + bool has_panel_replay;
>
> We can drop this and reuse current ones ones, see bellow.
>
> > struct drm_dp_vsc_sdp psr_vsc;
> >
> > /*
> > @@ -1531,6 +1532,7 @@ struct intel_psr {
> > bool irq_aux_error;
> > u16 su_w_granularity;
> > u16 su_y_granularity;
> > + bool sink_panel_replay_support;
>
> move this closer to has_psr and set both when it is panel replay.
> otherwise psr functions will not be executed for panel replay, see CAN_PSR().
AFIU Panel replay do not have any dependency with PSR.
So that’s why I have created separate function for panel replay which is doing similar thing whatever needed for panel replay.
For example intel_panel_replay_compute_config() can be independent of intel_psr_compute_config().
Do you see any dependency with PSR for panel replay?
>
> > u32 dc3co_exitline;
> > u32 dc3co_exit_delay;
> > struct delayed_work dc3co_work;
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 10fda20a5bd8..f58a7b72be14 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -1587,12 +1587,22 @@ static void
> intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >
> > - /*
> > - * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> > - * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> > - * Colorimetry Format indication.
> > - */
> > - vsc->revision = 0x5;
> > + if (crtc_state->has_panel_replay) {
> > + /*
> > + * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
> > + * VSC SDP supporting 3D stereo, Panel Replay, and Pixel
> > + * Encoding/Colorimetry Format indication.
> > + */
> > + vsc->revision = 0x7;
> > + } else {
> > + /*
> > + * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> > + * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> > + * Colorimetry Format indication.
> > + */
> > + vsc->revision = 0x5;
> > + }
> > +
> > vsc->length = 0x13;
> >
> > /* DP 1.4a spec, Table 2-120 */
> > @@ -1701,6 +1711,21 @@ void intel_dp_compute_psr_vsc_sdp(struct
> intel_dp *intel_dp,
> > vsc->revision = 0x4;
> > vsc->length = 0xe;
> > }
> > + } else if (intel_dp->psr.enabled && !intel_dp_is_edp(intel_dp)) {
> > + if (intel_dp->psr.colorimetry_support &&
> > + intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> > + /* [Panel Replay with colorimetry info] */
> > + intel_dp_compute_vsc_colorimetry(crtc_state,
> conn_state,
> > + vsc);
> > + } else {
> > + /*
> > + * [Panel Replay without colorimetry info]
> > + * Prepare VSC Header for SU as per DP 2.0 spec, Table
> 2-223
> > + * VSC SDP supporting 3D stereo + Panel Replay.
> > + */
> > + vsc->revision = 0x6;
> > + vsc->length = 0x10;
> > + }
> > } else {
> > /*
> > * [PSR1]
> > @@ -2749,10 +2774,10 @@ static ssize_t intel_dp_vsc_sdp_pack(const struct
> drm_dp_vsc_sdp *vsc,
> > sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
> >
> > /*
> > - * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
> > - * per DP 1.4a spec.
> > + * Revision 0x5 and 0x7 supports Pixel Encoding/Colorimetry Format as
> > + * per DP 1.4a spec and DP 2.0 spec respectively.
> > */
> > - if (vsc->revision != 0x5)
> > + if (vsc->revision != 0x5 || vsc->revision != 0x7)
> > goto out;
> >
> > /* VSC SDP Payload for DB16 through DB18 */ diff --git
> > a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 7a205fd5023b..91c2efe2f3ad 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -933,6 +933,21 @@ static bool intel_psr2_config_valid(struct intel_dp
> *intel_dp,
> > return true;
> > }
> >
> > +void intel_panel_replay_compute_config(struct intel_dp *intel_dp,
> > + struct intel_crtc_state *crtc_state) {
> > + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> > +
> > + if (!intel_dp->psr.sink_panel_replay_support)
> > + return;
> > +
> > + crtc_state->has_panel_replay = true;
> > + crtc_state->infoframes.enable |=
> > +intel_hdmi_infoframe_enable(DP_SDP_VSC);
> > +
> > + if (HAS_PSR2_SEL_FETCH(i915))
> > + intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state); }
> > +
> > void intel_psr_compute_config(struct intel_dp *intel_dp,
> > struct intel_crtc_state *crtc_state,
> > struct drm_connector_state *conn_state) @@ -
> 942,6 +957,8 @@
> > void intel_psr_compute_config(struct intel_dp *intel_dp,
> > &crtc_state->hw.adjusted_mode;
> > int psr_setup_time;
> >
> > + intel_panel_replay_compute_config(intel_dp, crtc_state);
>
> have you checked if the other PSR are needed for panel replay? what about the
> psr2 checks? when using panel replay selective update some additional tests will
> be needed regarding granularity...
As mentioned above I understood panel replay do not have any dependency with PSR.
Will not target panel replay selective update for dg2.
>
> > +
> > /*
> > * Current PSR panels dont work reliably with VRR enabled
> > * So if VRR is enabled, do not enable PSR.
> > @@ -2170,6 +2187,35 @@ void intel_psr_flush(struct drm_i915_private
> *dev_priv,
> > }
> > }
> >
> > +/**
> > + * intel_panel_replay_init - Check for sink and source capability.
> > + * @intel_dp: Intel DP
> > + *
> > + * This function is called after the initializing connector.
> > + * (the initializing of connector treats the handling of connector
> > +capabilities)
> > + * And it initializes basic panel replay stuff for each DP Encoder.
> > + */
> > +void intel_panel_replay_init(struct intel_dp *intel_dp) {
> > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > + u8 pr_dpcd = 0;
> > +
> > + if (!(HAS_DP20(dev_priv) && HAS_PANEL_REPLAY(dev_priv)))
> > + return;
> > +
> > + drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP,
> &pr_dpcd);
> > +
> > + if (!(pr_dpcd & PANEL_REPLAY_SUPPORT)) {
> > + drm_dbg_kms(&dev_priv->drm,
> > + "Panel replay is not supported by panel\n");
> > + return;
> > + }
> > +
> > + drm_dbg_kms(&dev_priv->drm,
> > + "Panel replay is supported by panel\n");
> > + intel_dp->psr.sink_panel_replay_support = true; }
> > +
> > /**
> > * intel_psr_init - Init basic PSR work and mutex.
> > * @intel_dp: Intel DP
> > @@ -2183,6 +2229,8 @@ void intel_psr_init(struct intel_dp *intel_dp)
> > struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> >
> > + intel_panel_replay_init(intel_dp);
> > +
> > if (!HAS_PSR(dev_priv))
> > return;
>
> mutex initialization is not executed, workers not initialized...
> please go more carefully trough every PSR function and check what are the
> panel replay implications
Tried to double check once more.
Currently as per bspec and dp 2.0 spec did not see any dependency with PSR.
Not sure if we really need worker thread to enter in panel replay mode unlike psr where we need to wait for few idle frames.
Any suggestion/input will be helpful here.
Regards,
Animesh
>
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> > b/drivers/gpu/drm/i915/display/intel_psr.h
> > index facffbacd357..c9d1c1f0b470 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.h
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> > @@ -32,6 +32,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
> > unsigned frontbuffer_bits,
> > enum fb_op_origin origin);
> > void intel_psr_init(struct intel_dp *intel_dp);
> > +void intel_panel_replay_init(struct intel_dp *intel_dp);
> > void intel_psr_compute_config(struct intel_dp *intel_dp,
> > struct intel_crtc_state *crtc_state,
> > struct drm_connector_state *conn_state); @@ -
> 52,5 +53,7 @@
> > void intel_psr2_disable_plane_sel_fetch(struct intel_plane *plane,
> > const struct intel_crtc_state
> *crtc_state); void
> > intel_psr_pause(struct intel_dp *intel_dp); void
> > intel_psr_resume(struct intel_dp *intel_dp);
> > +void intel_panel_replay_compute_config(struct intel_dp *intel_dp,
> > + struct intel_crtc_state *crtc_state);
> >
> > #endif /* __INTEL_PSR_H__ */
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v3 3/5] drm/i915/panelreplay: Initializaton and compute config for panel replay
2022-01-04 15:51 ` [Intel-gfx] " Manna, Animesh
@ 2022-01-04 15:55 ` Souza, Jose
-1 siblings, 0 replies; 31+ messages in thread
From: Souza, Jose @ 2022-01-04 15:55 UTC (permalink / raw)
To: dri-devel, Manna, Animesh, intel-gfx
Cc: Nikula, Jani, Navare, Manasi D, Kahola, Mika, Mun, Gwan-gyeong
On Tue, 2022-01-04 at 21:21 +0530, Manna, Animesh wrote:
> Hi,
>
> > -----Original Message-----
> > From: Souza, Jose <jose.souza@intel.com>
> > Sent: Wednesday, November 24, 2021 1:19 AM
> > To: dri-devel@lists.freedesktop.org; Manna, Animesh
> > <animesh.manna@intel.com>; intel-gfx@lists.freedesktop.org
> > Cc: Mun, Gwan-gyeong <gwan-gyeong.mun@intel.com>; Nikula, Jani
> > <jani.nikula@intel.com>; Kahola, Mika <mika.kahola@intel.com>; Navare,
> > Manasi D <manasi.d.navare@intel.com>
> > Subject: Re: [PATCH v3 3/5] drm/i915/panelreplay: Initializaton and compute
> > config for panel replay
> >
> > On Sun, 2021-10-10 at 17:40 +0530, Animesh Manna wrote:
> > > As panel replay feature similar to PSR feature of EDP panel, so
> > > currently utilized existing psr framework for panel replay.
> > >
> > > v1: RFC version.
> > > v2: optimized code, pr_enabled and pr_dpcd variable removed. [Jose]
> > > v3:
> > > - code comments improved. [Jani]
> > > - dpcd_readb used instead of dpcd_read. [Jani]
> > > - panel-repaplay init/compute functions moved inside respective psr
> > > function. [Jani]
> > >
> > > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > > ---
> > > .../drm/i915/display/intel_display_types.h | 2 +
> > > drivers/gpu/drm/i915/display/intel_dp.c | 43 +++++++++++++----
> > > drivers/gpu/drm/i915/display/intel_psr.c | 48 +++++++++++++++++++
> > > drivers/gpu/drm/i915/display/intel_psr.h | 3 ++
> > > 4 files changed, 87 insertions(+), 9 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index 39e11eaec1a3..48f7d676ed2c 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -1070,6 +1070,7 @@ struct intel_crtc_state {
> > > bool req_psr2_sdp_prior_scanline;
> > > u32 dc3co_exitline;
> > > u16 su_y_granularity;
> > > + bool has_panel_replay;
> >
> > We can drop this and reuse current ones ones, see bellow.
> >
> > > struct drm_dp_vsc_sdp psr_vsc;
> > >
> > > /*
> > > @@ -1531,6 +1532,7 @@ struct intel_psr {
> > > bool irq_aux_error;
> > > u16 su_w_granularity;
> > > u16 su_y_granularity;
> > > + bool sink_panel_replay_support;
> >
> > move this closer to has_psr and set both when it is panel replay.
> > otherwise psr functions will not be executed for panel replay, see CAN_PSR().
>
> AFIU Panel replay do not have any dependency with PSR.
> So that’s why I have created separate function for panel replay which is doing similar thing whatever needed for panel replay.
> For example intel_panel_replay_compute_config() can be independent of intel_psr_compute_config().
> Do you see any dependency with PSR for panel replay?
There is no dependency but panel replay is PSR for DP so we should re-use PSR code as much as possible.
eDP + sink_support = PSR
DP + sink_support = panel replay
So we can reuse has_psr and all other stuff.
>
> >
> > > u32 dc3co_exitline;
> > > u32 dc3co_exit_delay;
> > > struct delayed_work dc3co_work;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index 10fda20a5bd8..f58a7b72be14 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -1587,12 +1587,22 @@ static void
> > intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
> > > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > >
> > > - /*
> > > - * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> > > - * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> > > - * Colorimetry Format indication.
> > > - */
> > > - vsc->revision = 0x5;
> > > + if (crtc_state->has_panel_replay) {
> > > + /*
> > > + * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
> > > + * VSC SDP supporting 3D stereo, Panel Replay, and Pixel
> > > + * Encoding/Colorimetry Format indication.
> > > + */
> > > + vsc->revision = 0x7;
> > > + } else {
> > > + /*
> > > + * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> > > + * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> > > + * Colorimetry Format indication.
> > > + */
> > > + vsc->revision = 0x5;
> > > + }
> > > +
> > > vsc->length = 0x13;
> > >
> > > /* DP 1.4a spec, Table 2-120 */
> > > @@ -1701,6 +1711,21 @@ void intel_dp_compute_psr_vsc_sdp(struct
> > intel_dp *intel_dp,
> > > vsc->revision = 0x4;
> > > vsc->length = 0xe;
> > > }
> > > + } else if (intel_dp->psr.enabled && !intel_dp_is_edp(intel_dp)) {
> > > + if (intel_dp->psr.colorimetry_support &&
> > > + intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> > > + /* [Panel Replay with colorimetry info] */
> > > + intel_dp_compute_vsc_colorimetry(crtc_state,
> > conn_state,
> > > + vsc);
> > > + } else {
> > > + /*
> > > + * [Panel Replay without colorimetry info]
> > > + * Prepare VSC Header for SU as per DP 2.0 spec, Table
> > 2-223
> > > + * VSC SDP supporting 3D stereo + Panel Replay.
> > > + */
> > > + vsc->revision = 0x6;
> > > + vsc->length = 0x10;
> > > + }
> > > } else {
> > > /*
> > > * [PSR1]
> > > @@ -2749,10 +2774,10 @@ static ssize_t intel_dp_vsc_sdp_pack(const struct
> > drm_dp_vsc_sdp *vsc,
> > > sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
> > >
> > > /*
> > > - * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
> > > - * per DP 1.4a spec.
> > > + * Revision 0x5 and 0x7 supports Pixel Encoding/Colorimetry Format as
> > > + * per DP 1.4a spec and DP 2.0 spec respectively.
> > > */
> > > - if (vsc->revision != 0x5)
> > > + if (vsc->revision != 0x5 || vsc->revision != 0x7)
> > > goto out;
> > >
> > > /* VSC SDP Payload for DB16 through DB18 */ diff --git
> > > a/drivers/gpu/drm/i915/display/intel_psr.c
> > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index 7a205fd5023b..91c2efe2f3ad 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -933,6 +933,21 @@ static bool intel_psr2_config_valid(struct intel_dp
> > *intel_dp,
> > > return true;
> > > }
> > >
> > > +void intel_panel_replay_compute_config(struct intel_dp *intel_dp,
> > > + struct intel_crtc_state *crtc_state) {
> > > + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> > > +
> > > + if (!intel_dp->psr.sink_panel_replay_support)
> > > + return;
> > > +
> > > + crtc_state->has_panel_replay = true;
> > > + crtc_state->infoframes.enable |=
> > > +intel_hdmi_infoframe_enable(DP_SDP_VSC);
> > > +
> > > + if (HAS_PSR2_SEL_FETCH(i915))
> > > + intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state); }
> > > +
> > > void intel_psr_compute_config(struct intel_dp *intel_dp,
> > > struct intel_crtc_state *crtc_state,
> > > struct drm_connector_state *conn_state) @@ -
> > 942,6 +957,8 @@
> > > void intel_psr_compute_config(struct intel_dp *intel_dp,
> > > &crtc_state->hw.adjusted_mode;
> > > int psr_setup_time;
> > >
> > > + intel_panel_replay_compute_config(intel_dp, crtc_state);
> >
> > have you checked if the other PSR are needed for panel replay? what about the
> > psr2 checks? when using panel replay selective update some additional tests will
> > be needed regarding granularity...
>
> As mentioned above I understood panel replay do not have any dependency with PSR.
> Will not target panel replay selective update for dg2.
>
> >
> > > +
> > > /*
> > > * Current PSR panels dont work reliably with VRR enabled
> > > * So if VRR is enabled, do not enable PSR.
> > > @@ -2170,6 +2187,35 @@ void intel_psr_flush(struct drm_i915_private
> > *dev_priv,
> > > }
> > > }
> > >
> > > +/**
> > > + * intel_panel_replay_init - Check for sink and source capability.
> > > + * @intel_dp: Intel DP
> > > + *
> > > + * This function is called after the initializing connector.
> > > + * (the initializing of connector treats the handling of connector
> > > +capabilities)
> > > + * And it initializes basic panel replay stuff for each DP Encoder.
> > > + */
> > > +void intel_panel_replay_init(struct intel_dp *intel_dp) {
> > > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > > + u8 pr_dpcd = 0;
> > > +
> > > + if (!(HAS_DP20(dev_priv) && HAS_PANEL_REPLAY(dev_priv)))
> > > + return;
> > > +
> > > + drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP,
> > &pr_dpcd);
> > > +
> > > + if (!(pr_dpcd & PANEL_REPLAY_SUPPORT)) {
> > > + drm_dbg_kms(&dev_priv->drm,
> > > + "Panel replay is not supported by panel\n");
> > > + return;
> > > + }
> > > +
> > > + drm_dbg_kms(&dev_priv->drm,
> > > + "Panel replay is supported by panel\n");
> > > + intel_dp->psr.sink_panel_replay_support = true; }
> > > +
> > > /**
> > > * intel_psr_init - Init basic PSR work and mutex.
> > > * @intel_dp: Intel DP
> > > @@ -2183,6 +2229,8 @@ void intel_psr_init(struct intel_dp *intel_dp)
> > > struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> > > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > >
> > > + intel_panel_replay_init(intel_dp);
> > > +
> > > if (!HAS_PSR(dev_priv))
> > > return;
> >
> > mutex initialization is not executed, workers not initialized...
> > please go more carefully trough every PSR function and check what are the
> > panel replay implications
>
> Tried to double check once more.
> Currently as per bspec and dp 2.0 spec did not see any dependency with PSR.
> Not sure if we really need worker thread to enter in panel replay mode unlike psr where we need to wait for few idle frames.
> Any suggestion/input will be helpful here.
>
> Regards,
> Animesh
>
> >
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> > > b/drivers/gpu/drm/i915/display/intel_psr.h
> > > index facffbacd357..c9d1c1f0b470 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> > > @@ -32,6 +32,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
> > > unsigned frontbuffer_bits,
> > > enum fb_op_origin origin);
> > > void intel_psr_init(struct intel_dp *intel_dp);
> > > +void intel_panel_replay_init(struct intel_dp *intel_dp);
> > > void intel_psr_compute_config(struct intel_dp *intel_dp,
> > > struct intel_crtc_state *crtc_state,
> > > struct drm_connector_state *conn_state); @@ -
> > 52,5 +53,7 @@
> > > void intel_psr2_disable_plane_sel_fetch(struct intel_plane *plane,
> > > const struct intel_crtc_state
> > *crtc_state); void
> > > intel_psr_pause(struct intel_dp *intel_dp); void
> > > intel_psr_resume(struct intel_dp *intel_dp);
> > > +void intel_panel_replay_compute_config(struct intel_dp *intel_dp,
> > > + struct intel_crtc_state *crtc_state);
> > >
> > > #endif /* __INTEL_PSR_H__ */
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [PATCH v3 3/5] drm/i915/panelreplay: Initializaton and compute config for panel replay
@ 2022-01-04 15:55 ` Souza, Jose
0 siblings, 0 replies; 31+ messages in thread
From: Souza, Jose @ 2022-01-04 15:55 UTC (permalink / raw)
To: dri-devel, Manna, Animesh, intel-gfx; +Cc: Nikula, Jani
On Tue, 2022-01-04 at 21:21 +0530, Manna, Animesh wrote:
> Hi,
>
> > -----Original Message-----
> > From: Souza, Jose <jose.souza@intel.com>
> > Sent: Wednesday, November 24, 2021 1:19 AM
> > To: dri-devel@lists.freedesktop.org; Manna, Animesh
> > <animesh.manna@intel.com>; intel-gfx@lists.freedesktop.org
> > Cc: Mun, Gwan-gyeong <gwan-gyeong.mun@intel.com>; Nikula, Jani
> > <jani.nikula@intel.com>; Kahola, Mika <mika.kahola@intel.com>; Navare,
> > Manasi D <manasi.d.navare@intel.com>
> > Subject: Re: [PATCH v3 3/5] drm/i915/panelreplay: Initializaton and compute
> > config for panel replay
> >
> > On Sun, 2021-10-10 at 17:40 +0530, Animesh Manna wrote:
> > > As panel replay feature similar to PSR feature of EDP panel, so
> > > currently utilized existing psr framework for panel replay.
> > >
> > > v1: RFC version.
> > > v2: optimized code, pr_enabled and pr_dpcd variable removed. [Jose]
> > > v3:
> > > - code comments improved. [Jani]
> > > - dpcd_readb used instead of dpcd_read. [Jani]
> > > - panel-repaplay init/compute functions moved inside respective psr
> > > function. [Jani]
> > >
> > > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > > ---
> > > .../drm/i915/display/intel_display_types.h | 2 +
> > > drivers/gpu/drm/i915/display/intel_dp.c | 43 +++++++++++++----
> > > drivers/gpu/drm/i915/display/intel_psr.c | 48 +++++++++++++++++++
> > > drivers/gpu/drm/i915/display/intel_psr.h | 3 ++
> > > 4 files changed, 87 insertions(+), 9 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index 39e11eaec1a3..48f7d676ed2c 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -1070,6 +1070,7 @@ struct intel_crtc_state {
> > > bool req_psr2_sdp_prior_scanline;
> > > u32 dc3co_exitline;
> > > u16 su_y_granularity;
> > > + bool has_panel_replay;
> >
> > We can drop this and reuse current ones ones, see bellow.
> >
> > > struct drm_dp_vsc_sdp psr_vsc;
> > >
> > > /*
> > > @@ -1531,6 +1532,7 @@ struct intel_psr {
> > > bool irq_aux_error;
> > > u16 su_w_granularity;
> > > u16 su_y_granularity;
> > > + bool sink_panel_replay_support;
> >
> > move this closer to has_psr and set both when it is panel replay.
> > otherwise psr functions will not be executed for panel replay, see CAN_PSR().
>
> AFIU Panel replay do not have any dependency with PSR.
> So that’s why I have created separate function for panel replay which is doing similar thing whatever needed for panel replay.
> For example intel_panel_replay_compute_config() can be independent of intel_psr_compute_config().
> Do you see any dependency with PSR for panel replay?
There is no dependency but panel replay is PSR for DP so we should re-use PSR code as much as possible.
eDP + sink_support = PSR
DP + sink_support = panel replay
So we can reuse has_psr and all other stuff.
>
> >
> > > u32 dc3co_exitline;
> > > u32 dc3co_exit_delay;
> > > struct delayed_work dc3co_work;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index 10fda20a5bd8..f58a7b72be14 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -1587,12 +1587,22 @@ static void
> > intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
> > > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > >
> > > - /*
> > > - * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> > > - * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> > > - * Colorimetry Format indication.
> > > - */
> > > - vsc->revision = 0x5;
> > > + if (crtc_state->has_panel_replay) {
> > > + /*
> > > + * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
> > > + * VSC SDP supporting 3D stereo, Panel Replay, and Pixel
> > > + * Encoding/Colorimetry Format indication.
> > > + */
> > > + vsc->revision = 0x7;
> > > + } else {
> > > + /*
> > > + * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> > > + * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> > > + * Colorimetry Format indication.
> > > + */
> > > + vsc->revision = 0x5;
> > > + }
> > > +
> > > vsc->length = 0x13;
> > >
> > > /* DP 1.4a spec, Table 2-120 */
> > > @@ -1701,6 +1711,21 @@ void intel_dp_compute_psr_vsc_sdp(struct
> > intel_dp *intel_dp,
> > > vsc->revision = 0x4;
> > > vsc->length = 0xe;
> > > }
> > > + } else if (intel_dp->psr.enabled && !intel_dp_is_edp(intel_dp)) {
> > > + if (intel_dp->psr.colorimetry_support &&
> > > + intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> > > + /* [Panel Replay with colorimetry info] */
> > > + intel_dp_compute_vsc_colorimetry(crtc_state,
> > conn_state,
> > > + vsc);
> > > + } else {
> > > + /*
> > > + * [Panel Replay without colorimetry info]
> > > + * Prepare VSC Header for SU as per DP 2.0 spec, Table
> > 2-223
> > > + * VSC SDP supporting 3D stereo + Panel Replay.
> > > + */
> > > + vsc->revision = 0x6;
> > > + vsc->length = 0x10;
> > > + }
> > > } else {
> > > /*
> > > * [PSR1]
> > > @@ -2749,10 +2774,10 @@ static ssize_t intel_dp_vsc_sdp_pack(const struct
> > drm_dp_vsc_sdp *vsc,
> > > sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
> > >
> > > /*
> > > - * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
> > > - * per DP 1.4a spec.
> > > + * Revision 0x5 and 0x7 supports Pixel Encoding/Colorimetry Format as
> > > + * per DP 1.4a spec and DP 2.0 spec respectively.
> > > */
> > > - if (vsc->revision != 0x5)
> > > + if (vsc->revision != 0x5 || vsc->revision != 0x7)
> > > goto out;
> > >
> > > /* VSC SDP Payload for DB16 through DB18 */ diff --git
> > > a/drivers/gpu/drm/i915/display/intel_psr.c
> > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index 7a205fd5023b..91c2efe2f3ad 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -933,6 +933,21 @@ static bool intel_psr2_config_valid(struct intel_dp
> > *intel_dp,
> > > return true;
> > > }
> > >
> > > +void intel_panel_replay_compute_config(struct intel_dp *intel_dp,
> > > + struct intel_crtc_state *crtc_state) {
> > > + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> > > +
> > > + if (!intel_dp->psr.sink_panel_replay_support)
> > > + return;
> > > +
> > > + crtc_state->has_panel_replay = true;
> > > + crtc_state->infoframes.enable |=
> > > +intel_hdmi_infoframe_enable(DP_SDP_VSC);
> > > +
> > > + if (HAS_PSR2_SEL_FETCH(i915))
> > > + intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state); }
> > > +
> > > void intel_psr_compute_config(struct intel_dp *intel_dp,
> > > struct intel_crtc_state *crtc_state,
> > > struct drm_connector_state *conn_state) @@ -
> > 942,6 +957,8 @@
> > > void intel_psr_compute_config(struct intel_dp *intel_dp,
> > > &crtc_state->hw.adjusted_mode;
> > > int psr_setup_time;
> > >
> > > + intel_panel_replay_compute_config(intel_dp, crtc_state);
> >
> > have you checked if the other PSR are needed for panel replay? what about the
> > psr2 checks? when using panel replay selective update some additional tests will
> > be needed regarding granularity...
>
> As mentioned above I understood panel replay do not have any dependency with PSR.
> Will not target panel replay selective update for dg2.
>
> >
> > > +
> > > /*
> > > * Current PSR panels dont work reliably with VRR enabled
> > > * So if VRR is enabled, do not enable PSR.
> > > @@ -2170,6 +2187,35 @@ void intel_psr_flush(struct drm_i915_private
> > *dev_priv,
> > > }
> > > }
> > >
> > > +/**
> > > + * intel_panel_replay_init - Check for sink and source capability.
> > > + * @intel_dp: Intel DP
> > > + *
> > > + * This function is called after the initializing connector.
> > > + * (the initializing of connector treats the handling of connector
> > > +capabilities)
> > > + * And it initializes basic panel replay stuff for each DP Encoder.
> > > + */
> > > +void intel_panel_replay_init(struct intel_dp *intel_dp) {
> > > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > > + u8 pr_dpcd = 0;
> > > +
> > > + if (!(HAS_DP20(dev_priv) && HAS_PANEL_REPLAY(dev_priv)))
> > > + return;
> > > +
> > > + drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP,
> > &pr_dpcd);
> > > +
> > > + if (!(pr_dpcd & PANEL_REPLAY_SUPPORT)) {
> > > + drm_dbg_kms(&dev_priv->drm,
> > > + "Panel replay is not supported by panel\n");
> > > + return;
> > > + }
> > > +
> > > + drm_dbg_kms(&dev_priv->drm,
> > > + "Panel replay is supported by panel\n");
> > > + intel_dp->psr.sink_panel_replay_support = true; }
> > > +
> > > /**
> > > * intel_psr_init - Init basic PSR work and mutex.
> > > * @intel_dp: Intel DP
> > > @@ -2183,6 +2229,8 @@ void intel_psr_init(struct intel_dp *intel_dp)
> > > struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> > > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > >
> > > + intel_panel_replay_init(intel_dp);
> > > +
> > > if (!HAS_PSR(dev_priv))
> > > return;
> >
> > mutex initialization is not executed, workers not initialized...
> > please go more carefully trough every PSR function and check what are the
> > panel replay implications
>
> Tried to double check once more.
> Currently as per bspec and dp 2.0 spec did not see any dependency with PSR.
> Not sure if we really need worker thread to enter in panel replay mode unlike psr where we need to wait for few idle frames.
> Any suggestion/input will be helpful here.
>
> Regards,
> Animesh
>
> >
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> > > b/drivers/gpu/drm/i915/display/intel_psr.h
> > > index facffbacd357..c9d1c1f0b470 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> > > @@ -32,6 +32,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
> > > unsigned frontbuffer_bits,
> > > enum fb_op_origin origin);
> > > void intel_psr_init(struct intel_dp *intel_dp);
> > > +void intel_panel_replay_init(struct intel_dp *intel_dp);
> > > void intel_psr_compute_config(struct intel_dp *intel_dp,
> > > struct intel_crtc_state *crtc_state,
> > > struct drm_connector_state *conn_state); @@ -
> > 52,5 +53,7 @@
> > > void intel_psr2_disable_plane_sel_fetch(struct intel_plane *plane,
> > > const struct intel_crtc_state
> > *crtc_state); void
> > > intel_psr_pause(struct intel_dp *intel_dp); void
> > > intel_psr_resume(struct intel_dp *intel_dp);
> > > +void intel_panel_replay_compute_config(struct intel_dp *intel_dp,
> > > + struct intel_crtc_state *crtc_state);
> > >
> > > #endif /* __INTEL_PSR_H__ */
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* RE: [PATCH v3 3/5] drm/i915/panelreplay: Initializaton and compute config for panel replay
2022-01-04 15:55 ` [Intel-gfx] " Souza, Jose
@ 2022-01-04 16:44 ` Manna, Animesh
-1 siblings, 0 replies; 31+ messages in thread
From: Manna, Animesh @ 2022-01-04 16:44 UTC (permalink / raw)
To: Souza, Jose, dri-devel, intel-gfx
Cc: Nikula, Jani, Navare, Manasi D, Kahola, Mika, Mun, Gwan-gyeong
> -----Original Message-----
> From: Souza, Jose <jose.souza@intel.com>
> Sent: Tuesday, January 4, 2022 9:25 PM
> To: dri-devel@lists.freedesktop.org; Manna, Animesh
> <animesh.manna@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Mun, Gwan-gyeong <gwan-gyeong.mun@intel.com>; Nikula, Jani
> <jani.nikula@intel.com>; Kahola, Mika <mika.kahola@intel.com>; Navare,
> Manasi D <manasi.d.navare@intel.com>
> Subject: Re: [PATCH v3 3/5] drm/i915/panelreplay: Initializaton and compute
> config for panel replay
>
> On Tue, 2022-01-04 at 21:21 +0530, Manna, Animesh wrote:
> > Hi,
> >
> > > -----Original Message-----
> > > From: Souza, Jose <jose.souza@intel.com>
> > > Sent: Wednesday, November 24, 2021 1:19 AM
> > > To: dri-devel@lists.freedesktop.org; Manna, Animesh
> > > <animesh.manna@intel.com>; intel-gfx@lists.freedesktop.org
> > > Cc: Mun, Gwan-gyeong <gwan-gyeong.mun@intel.com>; Nikula, Jani
> > > <jani.nikula@intel.com>; Kahola, Mika <mika.kahola@intel.com>;
> > > Navare, Manasi D <manasi.d.navare@intel.com>
> > > Subject: Re: [PATCH v3 3/5] drm/i915/panelreplay: Initializaton and
> > > compute config for panel replay
> > >
> > > On Sun, 2021-10-10 at 17:40 +0530, Animesh Manna wrote:
> > > > As panel replay feature similar to PSR feature of EDP panel, so
> > > > currently utilized existing psr framework for panel replay.
> > > >
> > > > v1: RFC version.
> > > > v2: optimized code, pr_enabled and pr_dpcd variable removed.
> > > > [Jose]
> > > > v3:
> > > > - code comments improved. [Jani]
> > > > - dpcd_readb used instead of dpcd_read. [Jani]
> > > > - panel-repaplay init/compute functions moved inside respective
> > > > psr function. [Jani]
> > > >
> > > > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > > > ---
> > > > .../drm/i915/display/intel_display_types.h | 2 +
> > > > drivers/gpu/drm/i915/display/intel_dp.c | 43 +++++++++++++----
> > > > drivers/gpu/drm/i915/display/intel_psr.c | 48 +++++++++++++++++++
> > > > drivers/gpu/drm/i915/display/intel_psr.h | 3 ++
> > > > 4 files changed, 87 insertions(+), 9 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > index 39e11eaec1a3..48f7d676ed2c 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > @@ -1070,6 +1070,7 @@ struct intel_crtc_state {
> > > > bool req_psr2_sdp_prior_scanline;
> > > > u32 dc3co_exitline;
> > > > u16 su_y_granularity;
> > > > + bool has_panel_replay;
> > >
> > > We can drop this and reuse current ones ones, see bellow.
> > >
> > > > struct drm_dp_vsc_sdp psr_vsc;
> > > >
> > > > /*
> > > > @@ -1531,6 +1532,7 @@ struct intel_psr {
> > > > bool irq_aux_error;
> > > > u16 su_w_granularity;
> > > > u16 su_y_granularity;
> > > > + bool sink_panel_replay_support;
> > >
> > > move this closer to has_psr and set both when it is panel replay.
> > > otherwise psr functions will not be executed for panel replay, see CAN_PSR().
> >
> > AFIU Panel replay do not have any dependency with PSR.
> > So that’s why I have created separate function for panel replay which is doing
> similar thing whatever needed for panel replay.
> > For example intel_panel_replay_compute_config() can be independent of
> intel_psr_compute_config().
> > Do you see any dependency with PSR for panel replay?
>
> There is no dependency but panel replay is PSR for DP so we should re-use PSR
> code as much as possible.
>
> eDP + sink_support = PSR
> DP + sink_support = panel replay
>
> So we can reuse has_psr and all other stuff.
Not sure what to reuse from psr other than selective update part which will not enable on dg2 for panel replay.
Will check further on this.
Regards,
Animesh
>
> >
> > >
> > > > u32 dc3co_exitline;
> > > > u32 dc3co_exit_delay;
> > > > struct delayed_work dc3co_work;
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > index 10fda20a5bd8..f58a7b72be14 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > @@ -1587,12 +1587,22 @@ static void
> > > intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
> > > > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > > > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > > >
> > > > - /*
> > > > - * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> > > > - * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> > > > - * Colorimetry Format indication.
> > > > - */
> > > > - vsc->revision = 0x5;
> > > > + if (crtc_state->has_panel_replay) {
> > > > + /*
> > > > + * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
> > > > + * VSC SDP supporting 3D stereo, Panel Replay, and Pixel
> > > > + * Encoding/Colorimetry Format indication.
> > > > + */
> > > > + vsc->revision = 0x7;
> > > > + } else {
> > > > + /*
> > > > + * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> > > > + * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> > > > + * Colorimetry Format indication.
> > > > + */
> > > > + vsc->revision = 0x5;
> > > > + }
> > > > +
> > > > vsc->length = 0x13;
> > > >
> > > > /* DP 1.4a spec, Table 2-120 */
> > > > @@ -1701,6 +1711,21 @@ void intel_dp_compute_psr_vsc_sdp(struct
> > > intel_dp *intel_dp,
> > > > vsc->revision = 0x4;
> > > > vsc->length = 0xe;
> > > > }
> > > > + } else if (intel_dp->psr.enabled && !intel_dp_is_edp(intel_dp)) {
> > > > + if (intel_dp->psr.colorimetry_support &&
> > > > + intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> > > > + /* [Panel Replay with colorimetry info] */
> > > > + intel_dp_compute_vsc_colorimetry(crtc_state,
> > > conn_state,
> > > > + vsc);
> > > > + } else {
> > > > + /*
> > > > + * [Panel Replay without colorimetry info]
> > > > + * Prepare VSC Header for SU as per DP 2.0 spec, Table
> > > 2-223
> > > > + * VSC SDP supporting 3D stereo + Panel Replay.
> > > > + */
> > > > + vsc->revision = 0x6;
> > > > + vsc->length = 0x10;
> > > > + }
> > > > } else {
> > > > /*
> > > > * [PSR1]
> > > > @@ -2749,10 +2774,10 @@ static ssize_t intel_dp_vsc_sdp_pack(const
> > > > struct
> > > drm_dp_vsc_sdp *vsc,
> > > > sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes
> > > > */
> > > >
> > > > /*
> > > > - * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
> > > > - * per DP 1.4a spec.
> > > > + * Revision 0x5 and 0x7 supports Pixel Encoding/Colorimetry Format as
> > > > + * per DP 1.4a spec and DP 2.0 spec respectively.
> > > > */
> > > > - if (vsc->revision != 0x5)
> > > > + if (vsc->revision != 0x5 || vsc->revision != 0x7)
> > > > goto out;
> > > >
> > > > /* VSC SDP Payload for DB16 through DB18 */ diff --git
> > > > a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > index 7a205fd5023b..91c2efe2f3ad 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > @@ -933,6 +933,21 @@ static bool intel_psr2_config_valid(struct
> > > > intel_dp
> > > *intel_dp,
> > > > return true;
> > > > }
> > > >
> > > > +void intel_panel_replay_compute_config(struct intel_dp *intel_dp,
> > > > + struct intel_crtc_state *crtc_state) {
> > > > + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> > > > +
> > > > + if (!intel_dp->psr.sink_panel_replay_support)
> > > > + return;
> > > > +
> > > > + crtc_state->has_panel_replay = true;
> > > > + crtc_state->infoframes.enable |=
> > > > +intel_hdmi_infoframe_enable(DP_SDP_VSC);
> > > > +
> > > > + if (HAS_PSR2_SEL_FETCH(i915))
> > > > + intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state); }
> > > > +
> > > > void intel_psr_compute_config(struct intel_dp *intel_dp,
> > > > struct intel_crtc_state *crtc_state,
> > > > struct drm_connector_state *conn_state) @@ -
> > > 942,6 +957,8 @@
> > > > void intel_psr_compute_config(struct intel_dp *intel_dp,
> > > > &crtc_state->hw.adjusted_mode;
> > > > int psr_setup_time;
> > > >
> > > > + intel_panel_replay_compute_config(intel_dp, crtc_state);
> > >
> > > have you checked if the other PSR are needed for panel replay? what
> > > about the
> > > psr2 checks? when using panel replay selective update some
> > > additional tests will be needed regarding granularity...
> >
> > As mentioned above I understood panel replay do not have any dependency
> with PSR.
> > Will not target panel replay selective update for dg2.
> >
> > >
> > > > +
> > > > /*
> > > > * Current PSR panels dont work reliably with VRR enabled
> > > > * So if VRR is enabled, do not enable PSR.
> > > > @@ -2170,6 +2187,35 @@ void intel_psr_flush(struct
> > > > drm_i915_private
> > > *dev_priv,
> > > > }
> > > > }
> > > >
> > > > +/**
> > > > + * intel_panel_replay_init - Check for sink and source capability.
> > > > + * @intel_dp: Intel DP
> > > > + *
> > > > + * This function is called after the initializing connector.
> > > > + * (the initializing of connector treats the handling of
> > > > +connector
> > > > +capabilities)
> > > > + * And it initializes basic panel replay stuff for each DP Encoder.
> > > > + */
> > > > +void intel_panel_replay_init(struct intel_dp *intel_dp) {
> > > > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > > > + u8 pr_dpcd = 0;
> > > > +
> > > > + if (!(HAS_DP20(dev_priv) && HAS_PANEL_REPLAY(dev_priv)))
> > > > + return;
> > > > +
> > > > + drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP,
> > > &pr_dpcd);
> > > > +
> > > > + if (!(pr_dpcd & PANEL_REPLAY_SUPPORT)) {
> > > > + drm_dbg_kms(&dev_priv->drm,
> > > > + "Panel replay is not supported by panel\n");
> > > > + return;
> > > > + }
> > > > +
> > > > + drm_dbg_kms(&dev_priv->drm,
> > > > + "Panel replay is supported by panel\n");
> > > > + intel_dp->psr.sink_panel_replay_support = true; }
> > > > +
> > > > /**
> > > > * intel_psr_init - Init basic PSR work and mutex.
> > > > * @intel_dp: Intel DP
> > > > @@ -2183,6 +2229,8 @@ void intel_psr_init(struct intel_dp *intel_dp)
> > > > struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> > > > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > > >
> > > > + intel_panel_replay_init(intel_dp);
> > > > +
> > > > if (!HAS_PSR(dev_priv))
> > > > return;
> > >
> > > mutex initialization is not executed, workers not initialized...
> > > please go more carefully trough every PSR function and check what
> > > are the panel replay implications
> >
> > Tried to double check once more.
> > Currently as per bspec and dp 2.0 spec did not see any dependency with PSR.
> > Not sure if we really need worker thread to enter in panel replay mode unlike
> psr where we need to wait for few idle frames.
> > Any suggestion/input will be helpful here.
> >
> > Regards,
> > Animesh
> >
> > >
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> > > > b/drivers/gpu/drm/i915/display/intel_psr.h
> > > > index facffbacd357..c9d1c1f0b470 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_psr.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> > > > @@ -32,6 +32,7 @@ void intel_psr_flush(struct drm_i915_private
> *dev_priv,
> > > > unsigned frontbuffer_bits,
> > > > enum fb_op_origin origin); void intel_psr_init(struct
> > > > intel_dp *intel_dp);
> > > > +void intel_panel_replay_init(struct intel_dp *intel_dp);
> > > > void intel_psr_compute_config(struct intel_dp *intel_dp,
> > > > struct intel_crtc_state *crtc_state,
> > > > struct drm_connector_state *conn_state); @@ -
> > > 52,5 +53,7 @@
> > > > void intel_psr2_disable_plane_sel_fetch(struct intel_plane *plane,
> > > > const struct intel_crtc_state
> > > *crtc_state); void
> > > > intel_psr_pause(struct intel_dp *intel_dp); void
> > > > intel_psr_resume(struct intel_dp *intel_dp);
> > > > +void intel_panel_replay_compute_config(struct intel_dp *intel_dp,
> > > > + struct intel_crtc_state *crtc_state);
> > > >
> > > > #endif /* __INTEL_PSR_H__ */
> >
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [Intel-gfx] [PATCH v3 3/5] drm/i915/panelreplay: Initializaton and compute config for panel replay
@ 2022-01-04 16:44 ` Manna, Animesh
0 siblings, 0 replies; 31+ messages in thread
From: Manna, Animesh @ 2022-01-04 16:44 UTC (permalink / raw)
To: Souza, Jose, dri-devel, intel-gfx; +Cc: Nikula, Jani
> -----Original Message-----
> From: Souza, Jose <jose.souza@intel.com>
> Sent: Tuesday, January 4, 2022 9:25 PM
> To: dri-devel@lists.freedesktop.org; Manna, Animesh
> <animesh.manna@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Mun, Gwan-gyeong <gwan-gyeong.mun@intel.com>; Nikula, Jani
> <jani.nikula@intel.com>; Kahola, Mika <mika.kahola@intel.com>; Navare,
> Manasi D <manasi.d.navare@intel.com>
> Subject: Re: [PATCH v3 3/5] drm/i915/panelreplay: Initializaton and compute
> config for panel replay
>
> On Tue, 2022-01-04 at 21:21 +0530, Manna, Animesh wrote:
> > Hi,
> >
> > > -----Original Message-----
> > > From: Souza, Jose <jose.souza@intel.com>
> > > Sent: Wednesday, November 24, 2021 1:19 AM
> > > To: dri-devel@lists.freedesktop.org; Manna, Animesh
> > > <animesh.manna@intel.com>; intel-gfx@lists.freedesktop.org
> > > Cc: Mun, Gwan-gyeong <gwan-gyeong.mun@intel.com>; Nikula, Jani
> > > <jani.nikula@intel.com>; Kahola, Mika <mika.kahola@intel.com>;
> > > Navare, Manasi D <manasi.d.navare@intel.com>
> > > Subject: Re: [PATCH v3 3/5] drm/i915/panelreplay: Initializaton and
> > > compute config for panel replay
> > >
> > > On Sun, 2021-10-10 at 17:40 +0530, Animesh Manna wrote:
> > > > As panel replay feature similar to PSR feature of EDP panel, so
> > > > currently utilized existing psr framework for panel replay.
> > > >
> > > > v1: RFC version.
> > > > v2: optimized code, pr_enabled and pr_dpcd variable removed.
> > > > [Jose]
> > > > v3:
> > > > - code comments improved. [Jani]
> > > > - dpcd_readb used instead of dpcd_read. [Jani]
> > > > - panel-repaplay init/compute functions moved inside respective
> > > > psr function. [Jani]
> > > >
> > > > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > > > ---
> > > > .../drm/i915/display/intel_display_types.h | 2 +
> > > > drivers/gpu/drm/i915/display/intel_dp.c | 43 +++++++++++++----
> > > > drivers/gpu/drm/i915/display/intel_psr.c | 48 +++++++++++++++++++
> > > > drivers/gpu/drm/i915/display/intel_psr.h | 3 ++
> > > > 4 files changed, 87 insertions(+), 9 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > index 39e11eaec1a3..48f7d676ed2c 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > @@ -1070,6 +1070,7 @@ struct intel_crtc_state {
> > > > bool req_psr2_sdp_prior_scanline;
> > > > u32 dc3co_exitline;
> > > > u16 su_y_granularity;
> > > > + bool has_panel_replay;
> > >
> > > We can drop this and reuse current ones ones, see bellow.
> > >
> > > > struct drm_dp_vsc_sdp psr_vsc;
> > > >
> > > > /*
> > > > @@ -1531,6 +1532,7 @@ struct intel_psr {
> > > > bool irq_aux_error;
> > > > u16 su_w_granularity;
> > > > u16 su_y_granularity;
> > > > + bool sink_panel_replay_support;
> > >
> > > move this closer to has_psr and set both when it is panel replay.
> > > otherwise psr functions will not be executed for panel replay, see CAN_PSR().
> >
> > AFIU Panel replay do not have any dependency with PSR.
> > So that’s why I have created separate function for panel replay which is doing
> similar thing whatever needed for panel replay.
> > For example intel_panel_replay_compute_config() can be independent of
> intel_psr_compute_config().
> > Do you see any dependency with PSR for panel replay?
>
> There is no dependency but panel replay is PSR for DP so we should re-use PSR
> code as much as possible.
>
> eDP + sink_support = PSR
> DP + sink_support = panel replay
>
> So we can reuse has_psr and all other stuff.
Not sure what to reuse from psr other than selective update part which will not enable on dg2 for panel replay.
Will check further on this.
Regards,
Animesh
>
> >
> > >
> > > > u32 dc3co_exitline;
> > > > u32 dc3co_exit_delay;
> > > > struct delayed_work dc3co_work;
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > index 10fda20a5bd8..f58a7b72be14 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > @@ -1587,12 +1587,22 @@ static void
> > > intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc
> > > > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > > > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > > >
> > > > - /*
> > > > - * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> > > > - * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> > > > - * Colorimetry Format indication.
> > > > - */
> > > > - vsc->revision = 0x5;
> > > > + if (crtc_state->has_panel_replay) {
> > > > + /*
> > > > + * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223
> > > > + * VSC SDP supporting 3D stereo, Panel Replay, and Pixel
> > > > + * Encoding/Colorimetry Format indication.
> > > > + */
> > > > + vsc->revision = 0x7;
> > > > + } else {
> > > > + /*
> > > > + * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
> > > > + * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> > > > + * Colorimetry Format indication.
> > > > + */
> > > > + vsc->revision = 0x5;
> > > > + }
> > > > +
> > > > vsc->length = 0x13;
> > > >
> > > > /* DP 1.4a spec, Table 2-120 */
> > > > @@ -1701,6 +1711,21 @@ void intel_dp_compute_psr_vsc_sdp(struct
> > > intel_dp *intel_dp,
> > > > vsc->revision = 0x4;
> > > > vsc->length = 0xe;
> > > > }
> > > > + } else if (intel_dp->psr.enabled && !intel_dp_is_edp(intel_dp)) {
> > > > + if (intel_dp->psr.colorimetry_support &&
> > > > + intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
> > > > + /* [Panel Replay with colorimetry info] */
> > > > + intel_dp_compute_vsc_colorimetry(crtc_state,
> > > conn_state,
> > > > + vsc);
> > > > + } else {
> > > > + /*
> > > > + * [Panel Replay without colorimetry info]
> > > > + * Prepare VSC Header for SU as per DP 2.0 spec, Table
> > > 2-223
> > > > + * VSC SDP supporting 3D stereo + Panel Replay.
> > > > + */
> > > > + vsc->revision = 0x6;
> > > > + vsc->length = 0x10;
> > > > + }
> > > > } else {
> > > > /*
> > > > * [PSR1]
> > > > @@ -2749,10 +2774,10 @@ static ssize_t intel_dp_vsc_sdp_pack(const
> > > > struct
> > > drm_dp_vsc_sdp *vsc,
> > > > sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes
> > > > */
> > > >
> > > > /*
> > > > - * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
> > > > - * per DP 1.4a spec.
> > > > + * Revision 0x5 and 0x7 supports Pixel Encoding/Colorimetry Format as
> > > > + * per DP 1.4a spec and DP 2.0 spec respectively.
> > > > */
> > > > - if (vsc->revision != 0x5)
> > > > + if (vsc->revision != 0x5 || vsc->revision != 0x7)
> > > > goto out;
> > > >
> > > > /* VSC SDP Payload for DB16 through DB18 */ diff --git
> > > > a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > index 7a205fd5023b..91c2efe2f3ad 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > @@ -933,6 +933,21 @@ static bool intel_psr2_config_valid(struct
> > > > intel_dp
> > > *intel_dp,
> > > > return true;
> > > > }
> > > >
> > > > +void intel_panel_replay_compute_config(struct intel_dp *intel_dp,
> > > > + struct intel_crtc_state *crtc_state) {
> > > > + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> > > > +
> > > > + if (!intel_dp->psr.sink_panel_replay_support)
> > > > + return;
> > > > +
> > > > + crtc_state->has_panel_replay = true;
> > > > + crtc_state->infoframes.enable |=
> > > > +intel_hdmi_infoframe_enable(DP_SDP_VSC);
> > > > +
> > > > + if (HAS_PSR2_SEL_FETCH(i915))
> > > > + intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state); }
> > > > +
> > > > void intel_psr_compute_config(struct intel_dp *intel_dp,
> > > > struct intel_crtc_state *crtc_state,
> > > > struct drm_connector_state *conn_state) @@ -
> > > 942,6 +957,8 @@
> > > > void intel_psr_compute_config(struct intel_dp *intel_dp,
> > > > &crtc_state->hw.adjusted_mode;
> > > > int psr_setup_time;
> > > >
> > > > + intel_panel_replay_compute_config(intel_dp, crtc_state);
> > >
> > > have you checked if the other PSR are needed for panel replay? what
> > > about the
> > > psr2 checks? when using panel replay selective update some
> > > additional tests will be needed regarding granularity...
> >
> > As mentioned above I understood panel replay do not have any dependency
> with PSR.
> > Will not target panel replay selective update for dg2.
> >
> > >
> > > > +
> > > > /*
> > > > * Current PSR panels dont work reliably with VRR enabled
> > > > * So if VRR is enabled, do not enable PSR.
> > > > @@ -2170,6 +2187,35 @@ void intel_psr_flush(struct
> > > > drm_i915_private
> > > *dev_priv,
> > > > }
> > > > }
> > > >
> > > > +/**
> > > > + * intel_panel_replay_init - Check for sink and source capability.
> > > > + * @intel_dp: Intel DP
> > > > + *
> > > > + * This function is called after the initializing connector.
> > > > + * (the initializing of connector treats the handling of
> > > > +connector
> > > > +capabilities)
> > > > + * And it initializes basic panel replay stuff for each DP Encoder.
> > > > + */
> > > > +void intel_panel_replay_init(struct intel_dp *intel_dp) {
> > > > + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > > > + u8 pr_dpcd = 0;
> > > > +
> > > > + if (!(HAS_DP20(dev_priv) && HAS_PANEL_REPLAY(dev_priv)))
> > > > + return;
> > > > +
> > > > + drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP,
> > > &pr_dpcd);
> > > > +
> > > > + if (!(pr_dpcd & PANEL_REPLAY_SUPPORT)) {
> > > > + drm_dbg_kms(&dev_priv->drm,
> > > > + "Panel replay is not supported by panel\n");
> > > > + return;
> > > > + }
> > > > +
> > > > + drm_dbg_kms(&dev_priv->drm,
> > > > + "Panel replay is supported by panel\n");
> > > > + intel_dp->psr.sink_panel_replay_support = true; }
> > > > +
> > > > /**
> > > > * intel_psr_init - Init basic PSR work and mutex.
> > > > * @intel_dp: Intel DP
> > > > @@ -2183,6 +2229,8 @@ void intel_psr_init(struct intel_dp *intel_dp)
> > > > struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> > > > struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > > >
> > > > + intel_panel_replay_init(intel_dp);
> > > > +
> > > > if (!HAS_PSR(dev_priv))
> > > > return;
> > >
> > > mutex initialization is not executed, workers not initialized...
> > > please go more carefully trough every PSR function and check what
> > > are the panel replay implications
> >
> > Tried to double check once more.
> > Currently as per bspec and dp 2.0 spec did not see any dependency with PSR.
> > Not sure if we really need worker thread to enter in panel replay mode unlike
> psr where we need to wait for few idle frames.
> > Any suggestion/input will be helpful here.
> >
> > Regards,
> > Animesh
> >
> > >
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> > > > b/drivers/gpu/drm/i915/display/intel_psr.h
> > > > index facffbacd357..c9d1c1f0b470 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_psr.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> > > > @@ -32,6 +32,7 @@ void intel_psr_flush(struct drm_i915_private
> *dev_priv,
> > > > unsigned frontbuffer_bits,
> > > > enum fb_op_origin origin); void intel_psr_init(struct
> > > > intel_dp *intel_dp);
> > > > +void intel_panel_replay_init(struct intel_dp *intel_dp);
> > > > void intel_psr_compute_config(struct intel_dp *intel_dp,
> > > > struct intel_crtc_state *crtc_state,
> > > > struct drm_connector_state *conn_state); @@ -
> > > 52,5 +53,7 @@
> > > > void intel_psr2_disable_plane_sel_fetch(struct intel_plane *plane,
> > > > const struct intel_crtc_state
> > > *crtc_state); void
> > > > intel_psr_pause(struct intel_dp *intel_dp); void
> > > > intel_psr_resume(struct intel_dp *intel_dp);
> > > > +void intel_panel_replay_compute_config(struct intel_dp *intel_dp,
> > > > + struct intel_crtc_state *crtc_state);
> > > >
> > > > #endif /* __INTEL_PSR_H__ */
> >
^ permalink raw reply [flat|nested] 31+ messages in thread
end of thread, other threads:[~2022-01-04 16:44 UTC | newest]
Thread overview: 31+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-10-10 12:10 [PATCH v3 0/5] Panel replay phase1 implementation Animesh Manna
2021-10-10 12:10 ` [Intel-gfx] " Animesh Manna
2021-10-10 12:10 ` [PATCH v3 1/5] drm/i915/panelreplay: dpcd register definition for panelreplay Animesh Manna
2021-10-10 12:10 ` [Intel-gfx] " Animesh Manna
2021-11-23 19:37 ` Souza, Jose
2021-11-23 19:37 ` [Intel-gfx] " Souza, Jose
2022-01-04 15:51 ` Manna, Animesh
2022-01-04 15:51 ` [Intel-gfx] " Manna, Animesh
2021-10-10 12:10 ` [PATCH v3 2/5] drm/i915/panelreplay: HAS_PR() macro added for panel replay Animesh Manna
2021-10-10 12:10 ` [Intel-gfx] " Animesh Manna
2021-10-10 12:10 ` [PATCH v3 3/5] drm/i915/panelreplay: Initializaton and compute config " Animesh Manna
2021-10-10 12:10 ` [Intel-gfx] " Animesh Manna
2021-10-10 18:21 ` kernel test robot
2021-10-10 18:21 ` kernel test robot
2021-10-10 20:28 ` kernel test robot
2021-10-10 20:28 ` kernel test robot
2021-11-23 19:48 ` Souza, Jose
2021-11-23 19:48 ` [Intel-gfx] " Souza, Jose
2022-01-04 15:51 ` Manna, Animesh
2022-01-04 15:51 ` [Intel-gfx] " Manna, Animesh
2022-01-04 15:55 ` Souza, Jose
2022-01-04 15:55 ` [Intel-gfx] " Souza, Jose
2022-01-04 16:44 ` Manna, Animesh
2022-01-04 16:44 ` [Intel-gfx] " Manna, Animesh
2021-10-10 12:10 ` [PATCH v3 4/5] drm/i915/panelreplay: enable/disable " Animesh Manna
2021-10-10 12:10 ` [Intel-gfx] " Animesh Manna
2021-10-10 12:10 ` [PATCH v3 5/5] drm/i915/panelreplay: Added state checker for panel replay state Animesh Manna
2021-10-10 12:10 ` [Intel-gfx] " Animesh Manna
2021-10-10 12:50 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Panel replay phase1 implementation (rev3) Patchwork
2021-10-10 13:19 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-10-10 14:28 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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