* [PATCH 1/6] numa: Enable numa for SGX EPC sections
2021-10-11 11:15 [PATCH 0/6] SGX NUMA support Yang Zhong
@ 2021-10-11 11:15 ` Yang Zhong
2021-10-11 16:32 ` Eric Blake
2021-10-11 11:15 ` [PATCH 2/6] monitor: Support 'info numa' command Yang Zhong
` (4 subsequent siblings)
5 siblings, 1 reply; 17+ messages in thread
From: Yang Zhong @ 2021-10-11 11:15 UTC (permalink / raw)
To: qemu-devel; +Cc: yang.zhong, pbonzini, eblake, philmd
The basic SGX did not enable numa for SGX EPC sections, which
result in all EPC sections located in numa node 0. This patch
enable SGX numa function in the guest and the EPC section can
work with RAM as one numa node.
The Guest kernel related log:
[ 0.009981] ACPI: SRAT: Node 0 PXM 0 [mem 0x180000000-0x183ffffff]
[ 0.009982] ACPI: SRAT: Node 1 PXM 1 [mem 0x184000000-0x185bfffff]
The SRAT table can normally show SGX EPC sections menory info in different
numa nodes.
The SGX EPC numa related command:
......
-m 4G,maxmem=20G \
-smp sockets=2,cores=2 \
-cpu host,+sgx-provisionkey \
-object memory-backend-ram,size=2G,host-nodes=0,policy=bind,id=node0 \
-object memory-backend-epc,id=mem0,size=64M,prealloc=on,host-nodes=0,policy=bind \
-numa node,nodeid=0,cpus=0-1,memdev=node0 \
-object memory-backend-ram,size=2G,host-nodes=1,policy=bind,id=node1 \
-object memory-backend-epc,id=mem1,size=28M,prealloc=on,host-nodes=1,policy=bind \
-numa node,nodeid=1,cpus=2-3,memdev=node1 \
-M sgx-epc.0.memdev=mem0,sgx-epc.0.node=0,sgx-epc.1.memdev=mem1,sgx-epc.1.node=1 \
......
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
---
qapi/machine.json | 6 +++++-
include/hw/i386/sgx-epc.h | 3 +++
hw/i386/acpi-build.c | 4 ++++
hw/i386/sgx-epc.c | 3 +++
hw/i386/sgx.c | 44 +++++++++++++++++++++++++++++++++++++++
monitor/hmp-cmds.c | 1 +
qemu-options.hx | 4 ++--
7 files changed, 62 insertions(+), 3 deletions(-)
diff --git a/qapi/machine.json b/qapi/machine.json
index 5db54df298..09b6188e6f 100644
--- a/qapi/machine.json
+++ b/qapi/machine.json
@@ -1213,6 +1213,7 @@
'data': { '*id': 'str',
'memaddr': 'size',
'size': 'size',
+ 'node': 'int',
'memdev': 'str'
}
}
@@ -1288,7 +1289,10 @@
# Since: 6.2
##
{ 'struct': 'SgxEPC',
- 'data': { 'memdev': 'str' } }
+ 'data': { 'memdev': 'str',
+ 'node': 'int'
+ }
+}
##
# @SgxEPCProperties:
diff --git a/include/hw/i386/sgx-epc.h b/include/hw/i386/sgx-epc.h
index 65a68ca753..7a61c52869 100644
--- a/include/hw/i386/sgx-epc.h
+++ b/include/hw/i386/sgx-epc.h
@@ -25,6 +25,7 @@
#define SGX_EPC_ADDR_PROP "addr"
#define SGX_EPC_SIZE_PROP "size"
#define SGX_EPC_MEMDEV_PROP "memdev"
+#define SGX_EPC_NUMA_NODE_PROP "node"
/**
* SGXEPCDevice:
@@ -38,6 +39,7 @@ typedef struct SGXEPCDevice {
/* public */
uint64_t addr;
+ uint32_t node;
HostMemoryBackendEpc *hostmem;
} SGXEPCDevice;
@@ -56,6 +58,7 @@ typedef struct SGXEPCState {
} SGXEPCState;
int sgx_epc_get_section(int section_nr, uint64_t *addr, uint64_t *size);
+void sgx_epc_build_srat(GArray *table_data);
static inline uint64_t sgx_epc_above_4g_end(SGXEPCState *sgx_epc)
{
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 81418b7911..563a38992f 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -2062,6 +2062,10 @@ build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
nvdimm_build_srat(table_data);
}
+ if (pcms->sgx_epc.size != 0) {
+ sgx_epc_build_srat(table_data);
+ }
+
/*
* TODO: this part is not in ACPI spec and current linux kernel boots fine
* without these entries. But I recall there were issues the last time I
diff --git a/hw/i386/sgx-epc.c b/hw/i386/sgx-epc.c
index 55e2217eae..e5cd2789be 100644
--- a/hw/i386/sgx-epc.c
+++ b/hw/i386/sgx-epc.c
@@ -21,6 +21,7 @@
static Property sgx_epc_properties[] = {
DEFINE_PROP_UINT64(SGX_EPC_ADDR_PROP, SGXEPCDevice, addr, 0),
+ DEFINE_PROP_UINT32(SGX_EPC_NUMA_NODE_PROP, SGXEPCDevice, node, 0),
DEFINE_PROP_LINK(SGX_EPC_MEMDEV_PROP, SGXEPCDevice, hostmem,
TYPE_MEMORY_BACKEND_EPC, HostMemoryBackendEpc *),
DEFINE_PROP_END_OF_LIST(),
@@ -139,6 +140,8 @@ static void sgx_epc_md_fill_device_info(const MemoryDeviceState *md,
se->memaddr = epc->addr;
se->size = object_property_get_uint(OBJECT(epc), SGX_EPC_SIZE_PROP,
NULL);
+ se->node = object_property_get_uint(OBJECT(epc), SGX_EPC_NUMA_NODE_PROP,
+ NULL);
se->memdev = object_get_canonical_path(OBJECT(epc->hostmem));
info->u.sgx_epc.data = se;
diff --git a/hw/i386/sgx.c b/hw/i386/sgx.c
index e481e9358f..906facb645 100644
--- a/hw/i386/sgx.c
+++ b/hw/i386/sgx.c
@@ -19,6 +19,7 @@
#include "exec/address-spaces.h"
#include "hw/i386/sgx.h"
#include "sysemu/hw_accel.h"
+#include "hw/acpi/aml-build.h"
#define SGX_MAX_EPC_SECTIONS 8
#define SGX_CPUID_EPC_INVALID 0x0
@@ -27,6 +28,46 @@
#define SGX_CPUID_EPC_SECTION 0x1
#define SGX_CPUID_EPC_MASK 0xF
+static int sgx_epc_device_list(Object *obj, void *opaque)
+{
+ GSList **list = opaque;
+
+ if (object_dynamic_cast(obj, TYPE_SGX_EPC)) {
+ *list = g_slist_append(*list, DEVICE(obj));
+ }
+
+ object_child_foreach(obj, sgx_epc_device_list, opaque);
+ return 0;
+}
+
+static GSList *sgx_epc_get_device_list(void)
+{
+ GSList *list = NULL;
+
+ object_child_foreach(qdev_get_machine(), sgx_epc_device_list, &list);
+ return list;
+}
+
+void sgx_epc_build_srat(GArray *table_data)
+{
+ GSList *device_list = sgx_epc_get_device_list();
+
+ for (; device_list; device_list = device_list->next) {
+ DeviceState *dev = device_list->data;
+ Object *obj = OBJECT(dev);
+ uint64_t addr, size;
+ int node;
+
+ node = object_property_get_uint(obj, SGX_EPC_NUMA_NODE_PROP,
+ &error_abort);
+ addr = object_property_get_uint(obj, SGX_EPC_ADDR_PROP, &error_abort);
+ size = object_property_get_uint(obj, SGX_EPC_SIZE_PROP, &error_abort);
+
+ build_srat_memory(table_data, addr, size, node, MEM_AFFINITY_ENABLED);
+ }
+ g_slist_free(device_list);
+}
+
static uint64_t sgx_calc_section_metric(uint64_t low, uint64_t high)
{
return (low & MAKE_64BIT_MASK(12, 20)) +
@@ -156,6 +197,9 @@ void pc_machine_init_sgx_epc(PCMachineState *pcms)
/* set the memdev link with memory backend */
object_property_parse(obj, SGX_EPC_MEMDEV_PROP, list->value->memdev,
&error_fatal);
+ /* set the numa node property for sgx epc object */
+ object_property_set_uint(obj, SGX_EPC_NUMA_NODE_PROP, list->value->node,
+ &error_fatal);
object_property_set_bool(obj, "realized", true, &error_fatal);
object_unref(obj);
}
diff --git a/monitor/hmp-cmds.c b/monitor/hmp-cmds.c
index bcaa41350e..8af26e3e20 100644
--- a/monitor/hmp-cmds.c
+++ b/monitor/hmp-cmds.c
@@ -1878,6 +1878,7 @@ void hmp_info_memory_devices(Monitor *mon, const QDict *qdict)
se->id ? se->id : "");
monitor_printf(mon, " memaddr: 0x%" PRIx64 "\n", se->memaddr);
monitor_printf(mon, " size: %" PRIu64 "\n", se->size);
+ monitor_printf(mon, " node: %" PRId64 "\n", se->node);
monitor_printf(mon, " memdev: %s\n", se->memdev);
break;
default:
diff --git a/qemu-options.hx b/qemu-options.hx
index 5f375bbfa6..aaa5a1926d 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -127,11 +127,11 @@ SRST
ERST
DEF("M", HAS_ARG, QEMU_OPTION_M,
- " sgx-epc.0.memdev=memid\n",
+ " sgx-epc.0.memdev=memid,sgx-epc.0.node=numaid\n",
QEMU_ARCH_ALL)
SRST
-``sgx-epc.0.memdev=@var{memid}``
+``sgx-epc.0.memdev=@var{memid},sgx-epc.0.node=@var{numaid}``
Define an SGX EPC section.
ERST
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 1/6] numa: Enable numa for SGX EPC sections
2021-10-11 11:15 ` [PATCH 1/6] numa: Enable numa for SGX EPC sections Yang Zhong
@ 2021-10-11 16:32 ` Eric Blake
2021-10-20 7:02 ` Yang Zhong
0 siblings, 1 reply; 17+ messages in thread
From: Eric Blake @ 2021-10-11 16:32 UTC (permalink / raw)
To: Yang Zhong; +Cc: pbonzini, philmd, qemu-devel
On Mon, Oct 11, 2021 at 07:15:49PM +0800, Yang Zhong wrote:
> The basic SGX did not enable numa for SGX EPC sections, which
> result in all EPC sections located in numa node 0. This patch
> enable SGX numa function in the guest and the EPC section can
> work with RAM as one numa node.
>
> The Guest kernel related log:
> [ 0.009981] ACPI: SRAT: Node 0 PXM 0 [mem 0x180000000-0x183ffffff]
> [ 0.009982] ACPI: SRAT: Node 1 PXM 1 [mem 0x184000000-0x185bfffff]
> The SRAT table can normally show SGX EPC sections menory info in different
> numa nodes.
>
> The SGX EPC numa related command:
> ......
> -m 4G,maxmem=20G \
> -smp sockets=2,cores=2 \
> -cpu host,+sgx-provisionkey \
> -object memory-backend-ram,size=2G,host-nodes=0,policy=bind,id=node0 \
> -object memory-backend-epc,id=mem0,size=64M,prealloc=on,host-nodes=0,policy=bind \
> -numa node,nodeid=0,cpus=0-1,memdev=node0 \
> -object memory-backend-ram,size=2G,host-nodes=1,policy=bind,id=node1 \
> -object memory-backend-epc,id=mem1,size=28M,prealloc=on,host-nodes=1,policy=bind \
> -numa node,nodeid=1,cpus=2-3,memdev=node1 \
> -M sgx-epc.0.memdev=mem0,sgx-epc.0.node=0,sgx-epc.1.memdev=mem1,sgx-epc.1.node=1 \
> ......
>
> Signed-off-by: Yang Zhong <yang.zhong@intel.com>
> ---
> qapi/machine.json | 6 +++++-
> include/hw/i386/sgx-epc.h | 3 +++
> hw/i386/acpi-build.c | 4 ++++
> hw/i386/sgx-epc.c | 3 +++
> hw/i386/sgx.c | 44 +++++++++++++++++++++++++++++++++++++++
> monitor/hmp-cmds.c | 1 +
> qemu-options.hx | 4 ++--
> 7 files changed, 62 insertions(+), 3 deletions(-)
>
> diff --git a/qapi/machine.json b/qapi/machine.json
> index 5db54df298..09b6188e6f 100644
> --- a/qapi/machine.json
> +++ b/qapi/machine.json
> @@ -1213,6 +1213,7 @@
> 'data': { '*id': 'str',
> 'memaddr': 'size',
> 'size': 'size',
> + 'node': 'int',
> 'memdev': 'str'
> }
> }
> @@ -1288,7 +1289,10 @@
> # Since: 6.2
> ##
> { 'struct': 'SgxEPC',
> - 'data': { 'memdev': 'str' } }
> + 'data': { 'memdev': 'str',
> + 'node': 'int'
> + }
> +}
Missing documentation of the new member.
--
Eric Blake, Principal Software Engineer
Red Hat, Inc. +1-919-301-3266
Virtualization: qemu.org | libvirt.org
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH 1/6] numa: Enable numa for SGX EPC sections
2021-10-11 16:32 ` Eric Blake
@ 2021-10-20 7:02 ` Yang Zhong
0 siblings, 0 replies; 17+ messages in thread
From: Yang Zhong @ 2021-10-20 7:02 UTC (permalink / raw)
To: Eric Blake; +Cc: yang.zhong, pbonzini, philmd, qemu-devel
On Mon, Oct 11, 2021 at 11:32:39AM -0500, Eric Blake wrote:
> On Mon, Oct 11, 2021 at 07:15:49PM +0800, Yang Zhong wrote:
> > The basic SGX did not enable numa for SGX EPC sections, which
> > result in all EPC sections located in numa node 0. This patch
> > enable SGX numa function in the guest and the EPC section can
> > work with RAM as one numa node.
> >
> > The Guest kernel related log:
> > [ 0.009981] ACPI: SRAT: Node 0 PXM 0 [mem 0x180000000-0x183ffffff]
> > [ 0.009982] ACPI: SRAT: Node 1 PXM 1 [mem 0x184000000-0x185bfffff]
> > The SRAT table can normally show SGX EPC sections menory info in different
> > numa nodes.
> >
> > The SGX EPC numa related command:
> > ......
> > -m 4G,maxmem=20G \
> > -smp sockets=2,cores=2 \
> > -cpu host,+sgx-provisionkey \
> > -object memory-backend-ram,size=2G,host-nodes=0,policy=bind,id=node0 \
> > -object memory-backend-epc,id=mem0,size=64M,prealloc=on,host-nodes=0,policy=bind \
> > -numa node,nodeid=0,cpus=0-1,memdev=node0 \
> > -object memory-backend-ram,size=2G,host-nodes=1,policy=bind,id=node1 \
> > -object memory-backend-epc,id=mem1,size=28M,prealloc=on,host-nodes=1,policy=bind \
> > -numa node,nodeid=1,cpus=2-3,memdev=node1 \
> > -M sgx-epc.0.memdev=mem0,sgx-epc.0.node=0,sgx-epc.1.memdev=mem1,sgx-epc.1.node=1 \
> > ......
> >
> > Signed-off-by: Yang Zhong <yang.zhong@intel.com>
> > ---
> > qapi/machine.json | 6 +++++-
> > include/hw/i386/sgx-epc.h | 3 +++
> > hw/i386/acpi-build.c | 4 ++++
> > hw/i386/sgx-epc.c | 3 +++
> > hw/i386/sgx.c | 44 +++++++++++++++++++++++++++++++++++++++
> > monitor/hmp-cmds.c | 1 +
> > qemu-options.hx | 4 ++--
> > 7 files changed, 62 insertions(+), 3 deletions(-)
> >
> > diff --git a/qapi/machine.json b/qapi/machine.json
> > index 5db54df298..09b6188e6f 100644
> > --- a/qapi/machine.json
> > +++ b/qapi/machine.json
> > @@ -1213,6 +1213,7 @@
> > 'data': { '*id': 'str',
> > 'memaddr': 'size',
> > 'size': 'size',
> > + 'node': 'int',
> > 'memdev': 'str'
> > }
> > }
> > @@ -1288,7 +1289,10 @@
> > # Since: 6.2
> > ##
> > { 'struct': 'SgxEPC',
> > - 'data': { 'memdev': 'str' } }
> > + 'data': { 'memdev': 'str',
> > + 'node': 'int'
> > + }
> > +}
>
> Missing documentation of the new member.
>
Sorry for delay response, i will add this in next version, thanks!
Yang
> --
> Eric Blake, Principal Software Engineer
> Red Hat, Inc. +1-919-301-3266
> Virtualization: qemu.org | libvirt.org
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 2/6] monitor: Support 'info numa' command
2021-10-11 11:15 [PATCH 0/6] SGX NUMA support Yang Zhong
2021-10-11 11:15 ` [PATCH 1/6] numa: Enable numa for SGX EPC sections Yang Zhong
@ 2021-10-11 11:15 ` Yang Zhong
2021-10-11 11:15 ` [PATCH 3/6] numa: Add SGXEPCSection list for multiple sections Yang Zhong
` (3 subsequent siblings)
5 siblings, 0 replies; 17+ messages in thread
From: Yang Zhong @ 2021-10-11 11:15 UTC (permalink / raw)
To: qemu-devel; +Cc: yang.zhong, pbonzini, eblake, philmd
Add the MEMORY_DEVICE_INFO_KIND_SGX_EPC case for SGX numa info
with 'info numa' command in the monitor.
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
---
hw/core/numa.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/hw/core/numa.c b/hw/core/numa.c
index 510d096a88..1aa05dcf42 100644
--- a/hw/core/numa.c
+++ b/hw/core/numa.c
@@ -756,6 +756,7 @@ static void numa_stat_memory_devices(NumaNodeMem node_mem[])
PCDIMMDeviceInfo *pcdimm_info;
VirtioPMEMDeviceInfo *vpi;
VirtioMEMDeviceInfo *vmi;
+ SgxEPCDeviceInfo *se;
for (info = info_list; info; info = info->next) {
MemoryDeviceInfo *value = info->value;
@@ -781,6 +782,11 @@ static void numa_stat_memory_devices(NumaNodeMem node_mem[])
node_mem[vmi->node].node_mem += vmi->size;
node_mem[vmi->node].node_plugged_mem += vmi->size;
break;
+ case MEMORY_DEVICE_INFO_KIND_SGX_EPC:
+ se = value->u.sgx_epc.data;
+ node_mem[se->node].node_mem += se->size;
+ node_mem[se->node].node_plugged_mem = 0;
+ break;
default:
g_assert_not_reached();
}
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH 3/6] numa: Add SGXEPCSection list for multiple sections
2021-10-11 11:15 [PATCH 0/6] SGX NUMA support Yang Zhong
2021-10-11 11:15 ` [PATCH 1/6] numa: Enable numa for SGX EPC sections Yang Zhong
2021-10-11 11:15 ` [PATCH 2/6] monitor: Support 'info numa' command Yang Zhong
@ 2021-10-11 11:15 ` Yang Zhong
2021-10-11 17:03 ` Eric Blake
2021-10-12 11:01 ` Paolo Bonzini
2021-10-11 11:15 ` [PATCH 4/6] monitor: numa support for 'info sgx' command Yang Zhong
` (2 subsequent siblings)
5 siblings, 2 replies; 17+ messages in thread
From: Yang Zhong @ 2021-10-11 11:15 UTC (permalink / raw)
To: qemu-devel; +Cc: yang.zhong, pbonzini, eblake, philmd
The SGXEPCSection list added into SGXInfo to show the multiple
SGX EPC sections detailed info, not the total size like before.
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
---
qapi/misc-target.json | 19 +++++++++++++++++--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/qapi/misc-target.json b/qapi/misc-target.json
index 594fbd1577..89a5a4250a 100644
--- a/qapi/misc-target.json
+++ b/qapi/misc-target.json
@@ -334,6 +334,21 @@
'returns': 'SevAttestationReport',
'if': 'TARGET_I386' }
+##
+# @SGXEPCSection:
+#
+# Information about intel SGX EPC section info
+#
+# @index: the SGX epc section index
+#
+# @size: the size of epc section
+#
+# Since: 6.2
+##
+{ 'struct': 'SGXEPCSection',
+ 'data': { 'index': 'uint64',
+ 'size': 'uint64'}}
+
##
# @SGXInfo:
#
@@ -347,7 +362,7 @@
#
# @flc: true if FLC is supported
#
-# @section-size: The EPC section size for guest
+# @sections: The EPC sections info for guest
#
# Since: 6.2
##
@@ -356,7 +371,7 @@
'sgx1': 'bool',
'sgx2': 'bool',
'flc': 'bool',
- 'section-size': 'uint64'},
+ 'sections': ['SGXEPCSection']},
'if': 'TARGET_I386' }
##
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 3/6] numa: Add SGXEPCSection list for multiple sections
2021-10-11 11:15 ` [PATCH 3/6] numa: Add SGXEPCSection list for multiple sections Yang Zhong
@ 2021-10-11 17:03 ` Eric Blake
2021-10-12 11:01 ` Paolo Bonzini
2021-10-20 8:06 ` Yang Zhong
2021-10-12 11:01 ` Paolo Bonzini
1 sibling, 2 replies; 17+ messages in thread
From: Eric Blake @ 2021-10-11 17:03 UTC (permalink / raw)
To: Yang Zhong; +Cc: pbonzini, philmd, qemu-devel
On Mon, Oct 11, 2021 at 07:15:51PM +0800, Yang Zhong wrote:
> The SGXEPCSection list added into SGXInfo to show the multiple
> SGX EPC sections detailed info, not the total size like before.
>
> Signed-off-by: Yang Zhong <yang.zhong@intel.com>
> ---
> qapi/misc-target.json | 19 +++++++++++++++++--
> 1 file changed, 17 insertions(+), 2 deletions(-)
>
> diff --git a/qapi/misc-target.json b/qapi/misc-target.json
> index 594fbd1577..89a5a4250a 100644
> --- a/qapi/misc-target.json
> +++ b/qapi/misc-target.json
> @@ -334,6 +334,21 @@
> 'returns': 'SevAttestationReport',
> 'if': 'TARGET_I386' }
>
> +##
> +# @SGXEPCSection:
> +#
> +# Information about intel SGX EPC section info
> +#
> +# @index: the SGX epc section index
> +#
> +# @size: the size of epc section
> +#
> +# Since: 6.2
> +##
> +{ 'struct': 'SGXEPCSection',
> + 'data': { 'index': 'uint64',
> + 'size': 'uint64'}}
> +
> ##
> # @SGXInfo:
> #
> @@ -347,7 +362,7 @@
> #
> # @flc: true if FLC is supported
> #
> -# @section-size: The EPC section size for guest
> +# @sections: The EPC sections info for guest
> #
> # Since: 6.2
Given this has not yet been in a stable release, we can make this change...
> ##
> @@ -356,7 +371,7 @@
> 'sgx1': 'bool',
> 'sgx2': 'bool',
> 'flc': 'bool',
> - 'section-size': 'uint64'},
> + 'sections': ['SGXEPCSection']},
> 'if': 'TARGET_I386' }
...but are we sure we have the best interface possible if we are still
expressing uncertainty about the QAPI used to represent it?
--
Eric Blake, Principal Software Engineer
Red Hat, Inc. +1-919-301-3266
Virtualization: qemu.org | libvirt.org
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH 3/6] numa: Add SGXEPCSection list for multiple sections
2021-10-11 17:03 ` Eric Blake
@ 2021-10-12 11:01 ` Paolo Bonzini
2021-10-20 8:06 ` Yang Zhong
1 sibling, 0 replies; 17+ messages in thread
From: Paolo Bonzini @ 2021-10-12 11:01 UTC (permalink / raw)
To: Eric Blake, Yang Zhong; +Cc: philmd, qemu-devel
On 11/10/21 19:03, Eric Blake wrote:
>> +# @sections: The EPC sections info for guest
>> #
>> # Since: 6.2
> Given this has not yet been in a stable release, we can make this change...
>
>> ##
>> @@ -356,7 +371,7 @@
>> 'sgx1': 'bool',
>> 'sgx2': 'bool',
>> 'flc': 'bool',
>> - 'section-size': 'uint64'},
>> + 'sections': ['SGXEPCSection']},
>> 'if': 'TARGET_I386' }
> ...but are we sure we have the best interface possible if we are still
> expressing uncertainty about the QAPI used to represent it?
Yes, I think it's better to have a more flexible representation.
Paolo
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 3/6] numa: Add SGXEPCSection list for multiple sections
2021-10-11 17:03 ` Eric Blake
2021-10-12 11:01 ` Paolo Bonzini
@ 2021-10-20 8:06 ` Yang Zhong
1 sibling, 0 replies; 17+ messages in thread
From: Yang Zhong @ 2021-10-20 8:06 UTC (permalink / raw)
To: Eric Blake; +Cc: yang.zhong, pbonzini, philmd, qemu-devel
On Mon, Oct 11, 2021 at 12:03:24PM -0500, Eric Blake wrote:
> On Mon, Oct 11, 2021 at 07:15:51PM +0800, Yang Zhong wrote:
> > The SGXEPCSection list added into SGXInfo to show the multiple
> > SGX EPC sections detailed info, not the total size like before.
> >
> > Signed-off-by: Yang Zhong <yang.zhong@intel.com>
> > ---
> > qapi/misc-target.json | 19 +++++++++++++++++--
> > 1 file changed, 17 insertions(+), 2 deletions(-)
> >
> > diff --git a/qapi/misc-target.json b/qapi/misc-target.json
> > index 594fbd1577..89a5a4250a 100644
> > --- a/qapi/misc-target.json
> > +++ b/qapi/misc-target.json
> > @@ -334,6 +334,21 @@
> > 'returns': 'SevAttestationReport',
> > 'if': 'TARGET_I386' }
> >
> > +##
> > +# @SGXEPCSection:
> > +#
> > +# Information about intel SGX EPC section info
> > +#
> > +# @index: the SGX epc section index
> > +#
> > +# @size: the size of epc section
> > +#
> > +# Since: 6.2
> > +##
> > +{ 'struct': 'SGXEPCSection',
> > + 'data': { 'index': 'uint64',
> > + 'size': 'uint64'}}
> > +
> > ##
> > # @SGXInfo:
> > #
> > @@ -347,7 +362,7 @@
> > #
> > # @flc: true if FLC is supported
> > #
> > -# @section-size: The EPC section size for guest
> > +# @sections: The EPC sections info for guest
> > #
> > # Since: 6.2
>
> Given this has not yet been in a stable release, we can make this change...
>
The basic SGX is only suitable for one vepc section to guest. This new patchset
need support NUMA function with multiple vepc to guest. So we need detailed epc
or vepc section info. Thanks!
Yang
> > ##
> > @@ -356,7 +371,7 @@
> > 'sgx1': 'bool',
> > 'sgx2': 'bool',
> > 'flc': 'bool',
> > - 'section-size': 'uint64'},
> > + 'sections': ['SGXEPCSection']},
> > 'if': 'TARGET_I386' }
>
> ...but are we sure we have the best interface possible if we are still
> expressing uncertainty about the QAPI used to represent it?
>
Yes, we need more accurate definition to handle this. Paolo suggested
to use the numa node to replace this index, which is much better. Let
me change this in next version, thanks!
Yang
> --
> Eric Blake, Principal Software Engineer
> Red Hat, Inc. +1-919-301-3266
> Virtualization: qemu.org | libvirt.org
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [PATCH 3/6] numa: Add SGXEPCSection list for multiple sections
2021-10-11 11:15 ` [PATCH 3/6] numa: Add SGXEPCSection list for multiple sections Yang Zhong
2021-10-11 17:03 ` Eric Blake
@ 2021-10-12 11:01 ` Paolo Bonzini
2021-10-20 8:08 ` Yang Zhong
1 sibling, 1 reply; 17+ messages in thread
From: Paolo Bonzini @ 2021-10-12 11:01 UTC (permalink / raw)
To: Yang Zhong, qemu-devel; +Cc: philmd, eblake
On 11/10/21 13:15, Yang Zhong wrote:
> The SGXEPCSection list added into SGXInfo to show the multiple
> SGX EPC sections detailed info, not the total size like before.
>
> Signed-off-by: Yang Zhong <yang.zhong@intel.com>
> ---
> qapi/misc-target.json | 19 +++++++++++++++++--
> 1 file changed, 17 insertions(+), 2 deletions(-)
>
> diff --git a/qapi/misc-target.json b/qapi/misc-target.json
> index 594fbd1577..89a5a4250a 100644
> --- a/qapi/misc-target.json
> +++ b/qapi/misc-target.json
> @@ -334,6 +334,21 @@
> 'returns': 'SevAttestationReport',
> 'if': 'TARGET_I386' }
>
> +##
> +# @SGXEPCSection:
> +#
> +# Information about intel SGX EPC section info
> +#
> +# @index: the SGX epc section index
> +#
> +# @size: the size of epc section
> +#
> +# Since: 6.2
> +##
> +{ 'struct': 'SGXEPCSection',
> + 'data': { 'index': 'uint64',
> + 'size': 'uint64'}}
> +
> ##
> # @SGXInfo:
> #
> @@ -347,7 +362,7 @@
> #
> # @flc: true if FLC is supported
> #
> -# @section-size: The EPC section size for guest
> +# @sections: The EPC sections info for guest
> #
> # Since: 6.2
> ##
> @@ -356,7 +371,7 @@
> 'sgx1': 'bool',
> 'sgx2': 'bool',
> 'flc': 'bool',
> - 'section-size': 'uint64'},
> + 'sections': ['SGXEPCSection']},
> 'if': 'TARGET_I386' }
>
> ##
>
I am not sure the index is particularly useful, but perhaps you should
add the node there?
Paolo
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH 3/6] numa: Add SGXEPCSection list for multiple sections
2021-10-12 11:01 ` Paolo Bonzini
@ 2021-10-20 8:08 ` Yang Zhong
0 siblings, 0 replies; 17+ messages in thread
From: Yang Zhong @ 2021-10-20 8:08 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: yang.zhong, pbonzini, philmd, qemu-devel, eblake
On Tue, Oct 12, 2021 at 01:01:34PM +0200, Paolo Bonzini wrote:
> On 11/10/21 13:15, Yang Zhong wrote:
> >The SGXEPCSection list added into SGXInfo to show the multiple
> >SGX EPC sections detailed info, not the total size like before.
> >
> >Signed-off-by: Yang Zhong <yang.zhong@intel.com>
> >---
> > qapi/misc-target.json | 19 +++++++++++++++++--
> > 1 file changed, 17 insertions(+), 2 deletions(-)
> >
> >diff --git a/qapi/misc-target.json b/qapi/misc-target.json
> >index 594fbd1577..89a5a4250a 100644
> >--- a/qapi/misc-target.json
> >+++ b/qapi/misc-target.json
> >@@ -334,6 +334,21 @@
> > 'returns': 'SevAttestationReport',
> > 'if': 'TARGET_I386' }
> >+##
> >+# @SGXEPCSection:
> >+#
> >+# Information about intel SGX EPC section info
> >+#
> >+# @index: the SGX epc section index
> >+#
> >+# @size: the size of epc section
> >+#
> >+# Since: 6.2
> >+##
> >+{ 'struct': 'SGXEPCSection',
> >+ 'data': { 'index': 'uint64',
> >+ 'size': 'uint64'}}
> >+
> > ##
> > # @SGXInfo:
> > #
> >@@ -347,7 +362,7 @@
> > #
> > # @flc: true if FLC is supported
> > #
> >-# @section-size: The EPC section size for guest
> >+# @sections: The EPC sections info for guest
> > #
> > # Since: 6.2
> > ##
> >@@ -356,7 +371,7 @@
> > 'sgx1': 'bool',
> > 'sgx2': 'bool',
> > 'flc': 'bool',
> >- 'section-size': 'uint64'},
> >+ 'sections': ['SGXEPCSection']},
> > 'if': 'TARGET_I386' }
> > ##
> >
>
> I am not sure the index is particularly useful, but perhaps you
> should add the node there?
>
Good point! The node is much better than index here. thanks!
Yang
> Paolo
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 4/6] monitor: numa support for 'info sgx' command
2021-10-11 11:15 [PATCH 0/6] SGX NUMA support Yang Zhong
` (2 preceding siblings ...)
2021-10-11 11:15 ` [PATCH 3/6] numa: Add SGXEPCSection list for multiple sections Yang Zhong
@ 2021-10-11 11:15 ` Yang Zhong
2021-10-12 10:59 ` Paolo Bonzini
2021-10-11 11:15 ` [PATCH 5/6] numa: Enable numa for libvirt interface Yang Zhong
2021-10-11 11:15 ` [PATCH 6/6] doc: Add the SGX numa description Yang Zhong
5 siblings, 1 reply; 17+ messages in thread
From: Yang Zhong @ 2021-10-11 11:15 UTC (permalink / raw)
To: qemu-devel; +Cc: yang.zhong, pbonzini, eblake, philmd
This patch can enable numa support for 'info sgx' command
in the monitor, which can show detailed SGX EPC sections
info.
(qemu) info sgx
SGX support: enabled
SGX1 support: enabled
SGX2 support: enabled
FLC support: enabled
SECTION #0: size=67108864
SECTION #1: size=29360128
The QMP interface show:
(QEMU) query-sgx
{"return": {"sgx": true, "sgx2": true, "sgx1": true, "sections": \
[{"index": 0, "size": 67108864}, {"index": 1, "size": 29360128}], "flc": true}}
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
---
hw/i386/sgx.c | 25 +++++++++++++++++++++++--
target/i386/monitor.c | 11 +++++++++--
2 files changed, 32 insertions(+), 4 deletions(-)
diff --git a/hw/i386/sgx.c b/hw/i386/sgx.c
index 906facb645..8af45925c6 100644
--- a/hw/i386/sgx.c
+++ b/hw/i386/sgx.c
@@ -126,6 +126,28 @@ SGXInfo *sgx_get_capabilities(Error **errp)
return info;
}
+static SGXEPCSectionList *sgx_get_epc_sections_list(void)
+{
+ GSList *device_list = sgx_epc_get_device_list();
+ SGXEPCSectionList *head = NULL, **tail = &head;
+ SGXEPCSection *section;
+ uint64_t i = 0;
+
+ for (; device_list; device_list = device_list->next) {
+ DeviceState *dev = device_list->data;
+ Object *obj = OBJECT(dev);
+
+ section = g_new0(SGXEPCSection, 1);
+ section->index = i++;
+ section->size = object_property_get_uint(obj, SGX_EPC_SIZE_PROP,
+ &error_abort);
+ QAPI_LIST_APPEND(tail, section);
+ }
+ g_slist_free(device_list);
+
+ return head;
+}
+
SGXInfo *sgx_get_info(Error **errp)
{
SGXInfo *info = NULL;
@@ -144,14 +166,13 @@ SGXInfo *sgx_get_info(Error **errp)
return NULL;
}
- SGXEPCState *sgx_epc = &pcms->sgx_epc;
info = g_new0(SGXInfo, 1);
info->sgx = true;
info->sgx1 = true;
info->sgx2 = true;
info->flc = true;
- info->section_size = sgx_epc->size;
+ info->sections = sgx_get_epc_sections_list();
return info;
}
diff --git a/target/i386/monitor.c b/target/i386/monitor.c
index 196c1c9e77..08e7d4a425 100644
--- a/target/i386/monitor.c
+++ b/target/i386/monitor.c
@@ -773,6 +773,7 @@ SGXInfo *qmp_query_sgx(Error **errp)
void hmp_info_sgx(Monitor *mon, const QDict *qdict)
{
Error *err = NULL;
+ SGXEPCSectionList *section_list, *section;
g_autoptr(SGXInfo) info = qmp_query_sgx(&err);
if (err) {
@@ -787,8 +788,14 @@ void hmp_info_sgx(Monitor *mon, const QDict *qdict)
info->sgx2 ? "enabled" : "disabled");
monitor_printf(mon, "FLC support: %s\n",
info->flc ? "enabled" : "disabled");
- monitor_printf(mon, "size: %" PRIu64 "\n",
- info->section_size);
+
+ section_list = info->sections;
+ for (section = section_list; section; section = section->next) {
+ monitor_printf(mon, "SECTION #%" PRId64 ": ",
+ section->value->index);
+ monitor_printf(mon, "size=%" PRIu64 "\n",
+ section->value->size);
+ }
}
SGXInfo *qmp_query_sgx_capabilities(Error **errp)
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 4/6] monitor: numa support for 'info sgx' command
2021-10-11 11:15 ` [PATCH 4/6] monitor: numa support for 'info sgx' command Yang Zhong
@ 2021-10-12 10:59 ` Paolo Bonzini
2021-10-20 7:08 ` Yang Zhong
0 siblings, 1 reply; 17+ messages in thread
From: Paolo Bonzini @ 2021-10-12 10:59 UTC (permalink / raw)
To: Yang Zhong, qemu-devel; +Cc: philmd, eblake
On 11/10/21 13:15, Yang Zhong wrote:
> This patch can enable numa support for 'info sgx' command
> in the monitor, which can show detailed SGX EPC sections
> info.
>
> (qemu) info sgx
> SGX support: enabled
> SGX1 support: enabled
> SGX2 support: enabled
> FLC support: enabled
> SECTION #0: size=67108864
> SECTION #1: size=29360128
>
> The QMP interface show:
> (QEMU) query-sgx
> {"return": {"sgx": true, "sgx2": true, "sgx1": true, "sections": \
> [{"index": 0, "size": 67108864}, {"index": 1, "size": 29360128}], "flc": true}}
>
> Signed-off-by: Yang Zhong <yang.zhong@intel.com>
> ---
> hw/i386/sgx.c | 25 +++++++++++++++++++++++--
> target/i386/monitor.c | 11 +++++++++--
> 2 files changed, 32 insertions(+), 4 deletions(-)
>
> diff --git a/hw/i386/sgx.c b/hw/i386/sgx.c
> index 906facb645..8af45925c6 100644
> --- a/hw/i386/sgx.c
> +++ b/hw/i386/sgx.c
> @@ -126,6 +126,28 @@ SGXInfo *sgx_get_capabilities(Error **errp)
> return info;
> }
>
> +static SGXEPCSectionList *sgx_get_epc_sections_list(void)
> +{
> + GSList *device_list = sgx_epc_get_device_list();
> + SGXEPCSectionList *head = NULL, **tail = &head;
> + SGXEPCSection *section;
> + uint64_t i = 0;
> +
> + for (; device_list; device_list = device_list->next) {
> + DeviceState *dev = device_list->data;
> + Object *obj = OBJECT(dev);
> +
> + section = g_new0(SGXEPCSection, 1);
> + section->index = i++;
> + section->size = object_property_get_uint(obj, SGX_EPC_SIZE_PROP,
> + &error_abort);
> + QAPI_LIST_APPEND(tail, section);
> + }
> + g_slist_free(device_list);
> +
> + return head;
> +}
> +
> SGXInfo *sgx_get_info(Error **errp)
> {
> SGXInfo *info = NULL;
> @@ -144,14 +166,13 @@ SGXInfo *sgx_get_info(Error **errp)
> return NULL;
> }
>
> - SGXEPCState *sgx_epc = &pcms->sgx_epc;
> info = g_new0(SGXInfo, 1);
>
> info->sgx = true;
> info->sgx1 = true;
> info->sgx2 = true;
> info->flc = true;
> - info->section_size = sgx_epc->size;
> + info->sections = sgx_get_epc_sections_list();
>
> return info;
> }
> diff --git a/target/i386/monitor.c b/target/i386/monitor.c
> index 196c1c9e77..08e7d4a425 100644
> --- a/target/i386/monitor.c
> +++ b/target/i386/monitor.c
> @@ -773,6 +773,7 @@ SGXInfo *qmp_query_sgx(Error **errp)
> void hmp_info_sgx(Monitor *mon, const QDict *qdict)
> {
> Error *err = NULL;
> + SGXEPCSectionList *section_list, *section;
> g_autoptr(SGXInfo) info = qmp_query_sgx(&err);
>
> if (err) {
> @@ -787,8 +788,14 @@ void hmp_info_sgx(Monitor *mon, const QDict *qdict)
> info->sgx2 ? "enabled" : "disabled");
> monitor_printf(mon, "FLC support: %s\n",
> info->flc ? "enabled" : "disabled");
> - monitor_printf(mon, "size: %" PRIu64 "\n",
> - info->section_size);
> +
> + section_list = info->sections;
> + for (section = section_list; section; section = section->next) {
> + monitor_printf(mon, "SECTION #%" PRId64 ": ",
> + section->value->index);
> + monitor_printf(mon, "size=%" PRIu64 "\n",
> + section->value->size);
> + }
> }
>
> SGXInfo *qmp_query_sgx_capabilities(Error **errp)
>
This needs to be squashed in the previous patch.
Paolo
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH 4/6] monitor: numa support for 'info sgx' command
2021-10-12 10:59 ` Paolo Bonzini
@ 2021-10-20 7:08 ` Yang Zhong
0 siblings, 0 replies; 17+ messages in thread
From: Yang Zhong @ 2021-10-20 7:08 UTC (permalink / raw)
To: Paolo Bonzini; +Cc: yang.zhong, pbonzini, philmd, qemu-devel, eblake
On Tue, Oct 12, 2021 at 12:59:17PM +0200, Paolo Bonzini wrote:
> On 11/10/21 13:15, Yang Zhong wrote:
> >This patch can enable numa support for 'info sgx' command
> >in the monitor, which can show detailed SGX EPC sections
> >info.
> >
> >(qemu) info sgx
> > SGX support: enabled
> > SGX1 support: enabled
> > SGX2 support: enabled
> > FLC support: enabled
> > SECTION #0: size=67108864
> > SECTION #1: size=29360128
> >
> > The QMP interface show:
> > (QEMU) query-sgx
> > {"return": {"sgx": true, "sgx2": true, "sgx1": true, "sections": \
> > [{"index": 0, "size": 67108864}, {"index": 1, "size": 29360128}], "flc": true}}
> >
> >Signed-off-by: Yang Zhong <yang.zhong@intel.com>
> >---
> > hw/i386/sgx.c | 25 +++++++++++++++++++++++--
> > target/i386/monitor.c | 11 +++++++++--
> > 2 files changed, 32 insertions(+), 4 deletions(-)
> >
> >diff --git a/hw/i386/sgx.c b/hw/i386/sgx.c
> >index 906facb645..8af45925c6 100644
> >--- a/hw/i386/sgx.c
> >+++ b/hw/i386/sgx.c
> >@@ -126,6 +126,28 @@ SGXInfo *sgx_get_capabilities(Error **errp)
> > return info;
> > }
> >+static SGXEPCSectionList *sgx_get_epc_sections_list(void)
> >+{
> >+ GSList *device_list = sgx_epc_get_device_list();
> >+ SGXEPCSectionList *head = NULL, **tail = &head;
> >+ SGXEPCSection *section;
> >+ uint64_t i = 0;
> >+
> >+ for (; device_list; device_list = device_list->next) {
> >+ DeviceState *dev = device_list->data;
> >+ Object *obj = OBJECT(dev);
> >+
> >+ section = g_new0(SGXEPCSection, 1);
> >+ section->index = i++;
> >+ section->size = object_property_get_uint(obj, SGX_EPC_SIZE_PROP,
> >+ &error_abort);
> >+ QAPI_LIST_APPEND(tail, section);
> >+ }
> >+ g_slist_free(device_list);
> >+
> >+ return head;
> >+}
> >+
> > SGXInfo *sgx_get_info(Error **errp)
> > {
> > SGXInfo *info = NULL;
> >@@ -144,14 +166,13 @@ SGXInfo *sgx_get_info(Error **errp)
> > return NULL;
> > }
> >- SGXEPCState *sgx_epc = &pcms->sgx_epc;
> > info = g_new0(SGXInfo, 1);
> > info->sgx = true;
> > info->sgx1 = true;
> > info->sgx2 = true;
> > info->flc = true;
> >- info->section_size = sgx_epc->size;
> >+ info->sections = sgx_get_epc_sections_list();
> > return info;
> > }
> >diff --git a/target/i386/monitor.c b/target/i386/monitor.c
> >index 196c1c9e77..08e7d4a425 100644
> >--- a/target/i386/monitor.c
> >+++ b/target/i386/monitor.c
> >@@ -773,6 +773,7 @@ SGXInfo *qmp_query_sgx(Error **errp)
> > void hmp_info_sgx(Monitor *mon, const QDict *qdict)
> > {
> > Error *err = NULL;
> >+ SGXEPCSectionList *section_list, *section;
> > g_autoptr(SGXInfo) info = qmp_query_sgx(&err);
> > if (err) {
> >@@ -787,8 +788,14 @@ void hmp_info_sgx(Monitor *mon, const QDict *qdict)
> > info->sgx2 ? "enabled" : "disabled");
> > monitor_printf(mon, "FLC support: %s\n",
> > info->flc ? "enabled" : "disabled");
> >- monitor_printf(mon, "size: %" PRIu64 "\n",
> >- info->section_size);
> >+
> >+ section_list = info->sections;
> >+ for (section = section_list; section; section = section->next) {
> >+ monitor_printf(mon, "SECTION #%" PRId64 ": ",
> >+ section->value->index);
> >+ monitor_printf(mon, "size=%" PRIu64 "\n",
> >+ section->value->size);
> >+ }
> > }
> > SGXInfo *qmp_query_sgx_capabilities(Error **errp)
> >
>
> This needs to be squashed in the previous patch.
>
Okay, let me do it in next version, thanks!
Yang
> Paolo
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 5/6] numa: Enable numa for libvirt interface
2021-10-11 11:15 [PATCH 0/6] SGX NUMA support Yang Zhong
` (3 preceding siblings ...)
2021-10-11 11:15 ` [PATCH 4/6] monitor: numa support for 'info sgx' command Yang Zhong
@ 2021-10-11 11:15 ` Yang Zhong
2021-10-12 10:59 ` Paolo Bonzini
2021-10-11 11:15 ` [PATCH 6/6] doc: Add the SGX numa description Yang Zhong
5 siblings, 1 reply; 17+ messages in thread
From: Yang Zhong @ 2021-10-11 11:15 UTC (permalink / raw)
To: qemu-devel; +Cc: yang.zhong, pbonzini, eblake, philmd
Libvirt need get the detailed host SGX EPC capabilities to support
numa function. Libvirt can decide how to allocate host EPC sections
to guest numa from host numa info.
(QEMU) query-sgx-capabilities
{"return": {"sgx": true, "sgx2": true, "sgx1": true, "sections": \
[{"index": 0, "size": 17070817280}, {"index": 1, "size": 17079205888}], "flc": true}}
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
---
hw/i386/sgx.c | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/hw/i386/sgx.c b/hw/i386/sgx.c
index 8af45925c6..fe3034060d 100644
--- a/hw/i386/sgx.c
+++ b/hw/i386/sgx.c
@@ -74,11 +74,13 @@ static uint64_t sgx_calc_section_metric(uint64_t low, uint64_t high)
((high & MAKE_64BIT_MASK(0, 20)) << 32);
}
-static uint64_t sgx_calc_host_epc_section_size(void)
+static SGXEPCSectionList *sgx_calc_host_epc_sections(void)
{
+ SGXEPCSectionList *head = NULL, **tail = &head;
+ SGXEPCSection *section;
uint32_t i, type;
uint32_t eax, ebx, ecx, edx;
- uint64_t size = 0;
+ uint32_t j = 0;
for (i = 0; i < SGX_MAX_EPC_SECTIONS; i++) {
host_cpuid(0x12, i + 2, &eax, &ebx, &ecx, &edx);
@@ -92,10 +94,13 @@ static uint64_t sgx_calc_host_epc_section_size(void)
break;
}
- size += sgx_calc_section_metric(ecx, edx);
+ section = g_new0(SGXEPCSection, 1);
+ section->index = j++;
+ section->size = sgx_calc_section_metric(ecx, edx);
+ QAPI_LIST_APPEND(tail, section);
}
- return size;
+ return head;
}
SGXInfo *sgx_get_capabilities(Error **errp)
@@ -119,7 +124,7 @@ SGXInfo *sgx_get_capabilities(Error **errp)
info->sgx1 = eax & (1U << 0) ? true : false;
info->sgx2 = eax & (1U << 1) ? true : false;
- info->section_size = sgx_calc_host_epc_section_size();
+ info->sections = sgx_calc_host_epc_sections();
close(fd);
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH 5/6] numa: Enable numa for libvirt interface
2021-10-11 11:15 ` [PATCH 5/6] numa: Enable numa for libvirt interface Yang Zhong
@ 2021-10-12 10:59 ` Paolo Bonzini
0 siblings, 0 replies; 17+ messages in thread
From: Paolo Bonzini @ 2021-10-12 10:59 UTC (permalink / raw)
To: Yang Zhong, qemu-devel; +Cc: philmd, eblake
On 11/10/21 13:15, Yang Zhong wrote:
> Libvirt need get the detailed host SGX EPC capabilities to support
> numa function. Libvirt can decide how to allocate host EPC sections
> to guest numa from host numa info.
>
> (QEMU) query-sgx-capabilities
> {"return": {"sgx": true, "sgx2": true, "sgx1": true, "sections": \
> [{"index": 0, "size": 17070817280}, {"index": 1, "size": 17079205888}], "flc": true}}
>
> Signed-off-by: Yang Zhong <yang.zhong@intel.com>
> ---
> hw/i386/sgx.c | 15 ++++++++++-----
> 1 file changed, 10 insertions(+), 5 deletions(-)
>
> diff --git a/hw/i386/sgx.c b/hw/i386/sgx.c
> index 8af45925c6..fe3034060d 100644
> --- a/hw/i386/sgx.c
> +++ b/hw/i386/sgx.c
> @@ -74,11 +74,13 @@ static uint64_t sgx_calc_section_metric(uint64_t low, uint64_t high)
> ((high & MAKE_64BIT_MASK(0, 20)) << 32);
> }
>
> -static uint64_t sgx_calc_host_epc_section_size(void)
> +static SGXEPCSectionList *sgx_calc_host_epc_sections(void)
> {
> + SGXEPCSectionList *head = NULL, **tail = &head;
> + SGXEPCSection *section;
> uint32_t i, type;
> uint32_t eax, ebx, ecx, edx;
> - uint64_t size = 0;
> + uint32_t j = 0;
>
> for (i = 0; i < SGX_MAX_EPC_SECTIONS; i++) {
> host_cpuid(0x12, i + 2, &eax, &ebx, &ecx, &edx);
> @@ -92,10 +94,13 @@ static uint64_t sgx_calc_host_epc_section_size(void)
> break;
> }
>
> - size += sgx_calc_section_metric(ecx, edx);
> + section = g_new0(SGXEPCSection, 1);
> + section->index = j++;
> + section->size = sgx_calc_section_metric(ecx, edx);
> + QAPI_LIST_APPEND(tail, section);
> }
>
> - return size;
> + return head;
> }
>
> SGXInfo *sgx_get_capabilities(Error **errp)
> @@ -119,7 +124,7 @@ SGXInfo *sgx_get_capabilities(Error **errp)
> info->sgx1 = eax & (1U << 0) ? true : false;
> info->sgx2 = eax & (1U << 1) ? true : false;
>
> - info->section_size = sgx_calc_host_epc_section_size();
> + info->sections = sgx_calc_host_epc_sections();
>
> close(fd);
>
>
This too.
Paolo
^ permalink raw reply [flat|nested] 17+ messages in thread
* [PATCH 6/6] doc: Add the SGX numa description
2021-10-11 11:15 [PATCH 0/6] SGX NUMA support Yang Zhong
` (4 preceding siblings ...)
2021-10-11 11:15 ` [PATCH 5/6] numa: Enable numa for libvirt interface Yang Zhong
@ 2021-10-11 11:15 ` Yang Zhong
5 siblings, 0 replies; 17+ messages in thread
From: Yang Zhong @ 2021-10-11 11:15 UTC (permalink / raw)
To: qemu-devel; +Cc: yang.zhong, pbonzini, eblake, philmd
Add the SGX numa reference command and how to check if
SGX numa is support or not with multiple EPC sections.
Signed-off-by: Yang Zhong <yang.zhong@intel.com>
---
docs/system/i386/sgx.rst | 31 +++++++++++++++++++++++++++----
1 file changed, 27 insertions(+), 4 deletions(-)
diff --git a/docs/system/i386/sgx.rst b/docs/system/i386/sgx.rst
index f103ae2a2f..9e4ada761f 100644
--- a/docs/system/i386/sgx.rst
+++ b/docs/system/i386/sgx.rst
@@ -141,8 +141,7 @@ To launch a SGX guest:
|qemu_system_x86| \\
-cpu host,+sgx-provisionkey \\
-object memory-backend-epc,id=mem1,size=64M,prealloc=on \\
- -object memory-backend-epc,id=mem2,size=28M \\
- -M sgx-epc.0.memdev=mem1,sgx-epc.1.memdev=mem2
+ -M sgx-epc.0.memdev=mem1,sgx-epc.0.node=0
Utilizing SGX in the guest requires a kernel/OS with SGX support.
The support can be determined in guest by::
@@ -152,8 +151,32 @@ The support can be determined in guest by::
and SGX epc info by::
$ dmesg | grep sgx
- [ 1.242142] sgx: EPC section 0x180000000-0x181bfffff
- [ 1.242319] sgx: EPC section 0x181c00000-0x1837fffff
+ [ 0.182807] sgx: EPC section 0x140000000-0x143ffffff
+ [ 0.183695] sgx: [Firmware Bug]: Unable to map EPC section to online node. Fallback to the NUMA node 0.
+
+To launch a SGX numa guest:
+
+.. parsed-literal::
+
+ |qemu_system_x86| \\
+ -cpu host,+sgx-provisionkey \\
+ -object memory-backend-ram,size=2G,host-nodes=0,policy=bind,id=node0 \\
+ -object memory-backend-epc,id=mem0,size=64M,prealloc=on,host-nodes=0,policy=bind \\
+ -numa node,nodeid=0,cpus=0-1,memdev=node0 \\
+ -object memory-backend-ram,size=2G,host-nodes=1,policy=bind,id=node1 \\
+ -object memory-backend-epc,id=mem1,size=28M,prealloc=on,host-nodes=1,policy=bind \\
+ -numa node,nodeid=1,cpus=2-3,memdev=node1 \\
+ -M sgx-epc.0.memdev=mem0,sgx-epc.0.node=0,sgx-epc.1.memdev=mem1,sgx-epc.1.node=1
+
+and SGX epc numa info by::
+
+ $ dmesg | grep sgx
+ [ 0.369937] sgx: EPC section 0x180000000-0x183ffffff
+ [ 0.370259] sgx: EPC section 0x184000000-0x185bfffff
+
+ $ dmesg | grep SRAT
+ [ 0.009981] ACPI: SRAT: Node 0 PXM 0 [mem 0x180000000-0x183ffffff]
+ [ 0.009982] ACPI: SRAT: Node 1 PXM 1 [mem 0x184000000-0x185bfffff]
References
----------
^ permalink raw reply related [flat|nested] 17+ messages in thread