From: Ramalingam C <ramalingam.c@intel.com> To: dri-devel <dri-devel@lists.freedesktop.org>, intel-gfx <intel-gfx@lists.freedesktop.org> Cc: Daniel Vetter <daniel@ffwll.ch>, Matthew Auld <matthew.auld@intel.com>, CQ Tang <cq.tang@intel.com>, Hellstrom Thomas <thomas.hellstrom@intel.com>, Joonas Lahtinen <joonas.lahtinen@linux.intel.com>, Ramalingam C <ramalingam.c@intel.com> Subject: [PATCH 10/14] drm/i915/xehpsdv: Add has_flat_ccs to device info Date: Mon, 11 Oct 2021 21:41:51 +0530 [thread overview] Message-ID: <20211011161155.6397-11-ramalingam.c@intel.com> (raw) In-Reply-To: <20211011161155.6397-1-ramalingam.c@intel.com> From: CQ Tang <cq.tang@intel.com> Gen12+ devices support 3D surface (buffer) compression and various compression formats. This is accomplished by an additional compression control state (CCS) stored for each surface. Gen 12 devices(TGL family and DG1) stores compression states in a separate region of memory. It is managed by user-space and has an associated set of user-space managed page tables used by hardware for address translation. In Gen12.5 devices(XEHPSDV, DG2, etc), there is a new feature introduced i.e Flat CCS. It replaced AUX page tables with a flat indexed region of device memory for storing compression states. Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Matthew Auld <matthew.auld@intel.com> Signed-off-by: CQ Tang <cq.tang@intel.com> Signed-off-by: Ramalingam C <ramalingam.c@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_pci.c | 1 + drivers/gpu/drm/i915/intel_device_info.h | 1 + 3 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index a16fde38a252..57948e0ee48b 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1721,6 +1721,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i)) #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM) +#define HAS_FLAT_CCS(dev_priv) (INTEL_INFO(dev_priv)->has_flat_ccs) + #define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc) #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 8ef484a23652..68367b505dc4 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -991,6 +991,7 @@ static const struct intel_device_info adl_p_info = { XE_HP_PAGE_SIZES, \ .dma_mask_size = 46, \ .has_64bit_reloc = 1, \ + .has_flat_ccs = 1, \ .has_global_mocs = 1, \ .has_gt_uc = 1, \ .has_llc = 1, \ diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index dd453b96af19..87ee1d86d2ac 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -126,6 +126,7 @@ enum intel_ppgtt_type { func(has_64k_pages); \ func(gpu_reset_clobbers_display); \ func(has_reset_engine); \ + func(has_flat_ccs); \ func(has_global_mocs); \ func(has_gt_uc); \ func(has_l3_dpf); \ -- 2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: Ramalingam C <ramalingam.c@intel.com> To: dri-devel <dri-devel@lists.freedesktop.org>, intel-gfx <intel-gfx@lists.freedesktop.org> Cc: Daniel Vetter <daniel@ffwll.ch>, Matthew Auld <matthew.auld@intel.com>, CQ Tang <cq.tang@intel.com>, Hellstrom Thomas <thomas.hellstrom@intel.com>, Joonas Lahtinen <joonas.lahtinen@linux.intel.com>, Ramalingam C <ramalingam.c@intel.com> Subject: [Intel-gfx] [PATCH 10/14] drm/i915/xehpsdv: Add has_flat_ccs to device info Date: Mon, 11 Oct 2021 21:41:51 +0530 [thread overview] Message-ID: <20211011161155.6397-11-ramalingam.c@intel.com> (raw) In-Reply-To: <20211011161155.6397-1-ramalingam.c@intel.com> From: CQ Tang <cq.tang@intel.com> Gen12+ devices support 3D surface (buffer) compression and various compression formats. This is accomplished by an additional compression control state (CCS) stored for each surface. Gen 12 devices(TGL family and DG1) stores compression states in a separate region of memory. It is managed by user-space and has an associated set of user-space managed page tables used by hardware for address translation. In Gen12.5 devices(XEHPSDV, DG2, etc), there is a new feature introduced i.e Flat CCS. It replaced AUX page tables with a flat indexed region of device memory for storing compression states. Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Matthew Auld <matthew.auld@intel.com> Signed-off-by: CQ Tang <cq.tang@intel.com> Signed-off-by: Ramalingam C <ramalingam.c@intel.com> --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_pci.c | 1 + drivers/gpu/drm/i915/intel_device_info.h | 1 + 3 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index a16fde38a252..57948e0ee48b 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1721,6 +1721,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i)) #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM) +#define HAS_FLAT_CCS(dev_priv) (INTEL_INFO(dev_priv)->has_flat_ccs) + #define HAS_GT_UC(dev_priv) (INTEL_INFO(dev_priv)->has_gt_uc) #define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 8ef484a23652..68367b505dc4 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -991,6 +991,7 @@ static const struct intel_device_info adl_p_info = { XE_HP_PAGE_SIZES, \ .dma_mask_size = 46, \ .has_64bit_reloc = 1, \ + .has_flat_ccs = 1, \ .has_global_mocs = 1, \ .has_gt_uc = 1, \ .has_llc = 1, \ diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index dd453b96af19..87ee1d86d2ac 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -126,6 +126,7 @@ enum intel_ppgtt_type { func(has_64k_pages); \ func(gpu_reset_clobbers_display); \ func(has_reset_engine); \ + func(has_flat_ccs); \ func(has_global_mocs); \ func(has_gt_uc); \ func(has_l3_dpf); \ -- 2.20.1
next prev parent reply other threads:[~2021-10-11 16:09 UTC|newest] Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-10-11 16:11 [PATCH 00/14] drm/i915/dg2: Enabling 64k page size and flat ccs Ramalingam C 2021-10-11 16:11 ` [Intel-gfx] " Ramalingam C 2021-10-11 16:11 ` [PATCH 01/14] drm/i915: Add has_64k_pages flag Ramalingam C 2021-10-11 16:11 ` [Intel-gfx] " Ramalingam C 2021-10-11 16:11 ` [PATCH 02/14] drm/i915/xehpsdv: set min page-size to 64K Ramalingam C 2021-10-11 16:11 ` [Intel-gfx] " Ramalingam C 2021-10-11 16:11 ` [PATCH 03/14] drm/i915/xehpsdv: enforce min GTT alignment Ramalingam C 2021-10-11 16:11 ` [Intel-gfx] " Ramalingam C 2021-10-13 13:38 ` Daniel Vetter 2021-10-13 13:38 ` [Intel-gfx] " Daniel Vetter 2021-10-13 14:13 ` Matthew Auld 2021-10-13 14:13 ` [Intel-gfx] " Matthew Auld 2021-10-14 13:33 ` Daniel Vetter 2021-10-14 13:33 ` [Intel-gfx] " Daniel Vetter 2021-10-14 14:21 ` Matthew Auld 2021-10-14 14:21 ` [Intel-gfx] " Matthew Auld 2021-10-11 16:11 ` [PATCH 04/14] drm/i915: enforce min page size for scratch Ramalingam C 2021-10-11 16:11 ` [Intel-gfx] " Ramalingam C 2021-10-11 16:11 ` [PATCH 05/14] drm/i915/gtt/xehpsdv: move scratch page to system memory Ramalingam C 2021-10-11 16:11 ` [Intel-gfx] " Ramalingam C 2021-10-11 16:11 ` [PATCH 06/14] drm/i915/xehpsdv: support 64K GTT pages Ramalingam C 2021-10-11 16:11 ` [Intel-gfx] " Ramalingam C 2021-10-11 16:11 ` [PATCH 07/14] drm/i915: Add vm min alignment support Ramalingam C 2021-10-11 16:11 ` [Intel-gfx] " Ramalingam C 2021-10-11 16:11 ` [PATCH 08/14] drm/i915/selftests: account for min_alignment in GTT selftests Ramalingam C 2021-10-11 16:11 ` [Intel-gfx] " Ramalingam C 2021-10-11 16:11 ` [PATCH 09/14] drm/i915/xehpsdv: implement memory coloring Ramalingam C 2021-10-11 16:11 ` [Intel-gfx] " Ramalingam C 2021-10-11 16:11 ` Ramalingam C [this message] 2021-10-11 16:11 ` [Intel-gfx] [PATCH 10/14] drm/i915/xehpsdv: Add has_flat_ccs to device info Ramalingam C 2021-10-11 16:11 ` [PATCH 11/14] drm/i915/lmem: Enable lmem for platforms with Flat CCS Ramalingam C 2021-10-11 16:11 ` [Intel-gfx] " Ramalingam C 2021-10-11 16:11 ` [PATCH 12/14] drm/i915/gt: Clear compress metadata for Gen12.5 >= platforms Ramalingam C 2021-10-11 16:11 ` [Intel-gfx] " Ramalingam C 2021-10-11 16:11 ` [PATCH 13/14] drm/i915/uapi: document behaviour for DG2 64K support Ramalingam C 2021-10-11 16:11 ` [Intel-gfx] " Ramalingam C 2021-10-13 13:46 ` Daniel Vetter 2021-10-13 13:46 ` [Intel-gfx] " Daniel Vetter 2021-10-11 16:11 ` [PATCH 14/14] Doc/gpu/rfc/i915: i915 DG2 uAPI Ramalingam C 2021-10-11 16:11 ` [Intel-gfx] " Ramalingam C 2021-10-11 17:08 ` Tang, CQ 2021-10-11 17:08 ` [Intel-gfx] " Tang, CQ 2021-10-12 5:23 ` Lucas De Marchi 2021-10-12 5:23 ` [Intel-gfx] " Lucas De Marchi 2021-10-13 13:50 ` Daniel Vetter 2021-10-13 13:50 ` [Intel-gfx] " Daniel Vetter 2021-10-11 18:05 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dg2: Enabling 64k page size and flat ccs Patchwork 2021-10-11 18:06 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2021-10-11 18:34 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork 2021-10-13 13:51 ` [PATCH 00/14] " Daniel Vetter 2021-10-13 13:51 ` [Intel-gfx] " Daniel Vetter
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