[igt-dev] [PATCH i-g-t 0/7] Prepare IGTs to allow only zero alignment

[igt-dev] [PATCH i-g-t 0/7] Prepare IGTs to allow only zero alignment

[Zbigniew Kempczyński]

In the future we're planning to allow passing only zero alignment so
this is preparation step to introduce check and disable or fix 
igts which uses this constraint.

Cc: Petri Latvala <petri.latvala@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>

Zbigniew Kempczyński (7):
  lib/gem_submission: Add kernel exec object alignment capability
  lib/intel_batchbuffer: Detect and use kernel alignment capability
  tests/gem_exec_alignment: Add prerequisite alignment condition
  tests/gem_evict_alignment: Skip if kernel doesn't support passing
    alignment
  tests/i915_pm_rpm: Fix invalid alignment
  benchmarks/gem_exec_fault: Add timeout argument
  benchmarks/gem_exec_fault: Add softpin mode to support gens with ppgtt

 benchmarks/gem_exec_fault.c      | 71 +++++++++++++++++++++++++++-----
 lib/i915/gem_submission.c        | 32 ++++++++++++++
 lib/i915/gem_submission.h        |  1 +
 lib/intel_batchbuffer.c          |  9 +++-
 lib/intel_batchbuffer.h          |  1 +
 tests/i915/gem_evict_alignment.c |  1 +
 tests/i915/gem_exec_alignment.c  |  1 +
 tests/i915/i915_pm_rpm.c         |  2 +-
 8 files changed, 105 insertions(+), 13 deletions(-)

-- 
2.26.0

[igt-dev] [PATCH i-g-t 1/7] lib/gem_submission: Add kernel exec object alignment capability

[Zbigniew Kempczyński]

With newer gens passing non-zero alignment will be forbidden.
Add check which detects kernel supports it or not.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 lib/i915/gem_submission.c | 32 ++++++++++++++++++++++++++++++++
 lib/i915/gem_submission.h |  1 +
 2 files changed, 33 insertions(+)

diff --git a/lib/i915/gem_submission.c b/lib/i915/gem_submission.c
index f1af4f97c..459ee21f9 100644
--- a/lib/i915/gem_submission.c
+++ b/lib/i915/gem_submission.c
@@ -472,3 +472,35 @@ bool gem_has_relocations(int i915)
 
 	return has_relocs;
 }
+
+/**
+ * gem_allows_passing_alignment
+ * @fd: opened i915 drm file descriptor
+ *
+ * Check does i915 driver allows passing alignment in exec object to
+ * handle in kernel and adjust object offset accordingly.
+ *
+ * Returns: true if kernel supports setting offset to be aligned, otherwise
+ * false.
+ */
+bool gem_allows_passing_alignment(int fd)
+{
+	struct drm_i915_gem_exec_object2 obj = {
+		.handle = gem_create(fd, 4096),
+	};
+	struct drm_i915_gem_execbuffer2 execbuf = {
+		.buffers_ptr = to_user_pointer(&obj),
+		.buffer_count = 1,
+	};
+	bool ret;
+	const uint32_t bbe = MI_BATCH_BUFFER_END;
+
+	gem_write(fd, obj.handle, 0, &bbe, sizeof(bbe));
+	gem_execbuf(fd, &execbuf);
+
+	obj.alignment = 0x2000;
+	ret = __gem_execbuf(fd, &execbuf) == 0;
+	gem_close(fd, obj.handle);
+
+	return ret;
+}
diff --git a/lib/i915/gem_submission.h b/lib/i915/gem_submission.h
index 9b3e2a4e5..9f1ee8125 100644
--- a/lib/i915/gem_submission.h
+++ b/lib/i915/gem_submission.h
@@ -55,5 +55,6 @@ unsigned int gem_submission_measure(int i915, const intel_ctx_cfg_t *cfg,
 
 void gem_test_all_engines(int fd);
 bool gem_has_relocations(int fd);
+bool gem_allows_passing_alignment(int fd);
 
 #endif /* GEM_SUBMISSION_H */
-- 
2.26.0

Re: [igt-dev] [PATCH i-g-t 1/7] lib/gem_submission: Add kernel exec object alignment capability

[Dixit, Ashutosh]

On Thu, 07 Oct 2021 23:54:26 -0700, Zbigniew Kempczyński wrote:
>
> +bool gem_allows_passing_alignment(int fd)
> +{
> +	struct drm_i915_gem_exec_object2 obj = {
> +		.handle = gem_create(fd, 4096),
> +	};
> +	struct drm_i915_gem_execbuffer2 execbuf = {
> +		.buffers_ptr = to_user_pointer(&obj),
> +		.buffer_count = 1,
> +	};
> +	bool ret;
> +	const uint32_t bbe = MI_BATCH_BUFFER_END;
> +
> +	gem_write(fd, obj.handle, 0, &bbe, sizeof(bbe));
> +	gem_execbuf(fd, &execbuf);
> +
> +	obj.alignment = 0x2000;

8K? Shouldn't this be less than 4K?

> +	ret = __gem_execbuf(fd, &execbuf) == 0;
> +	gem_close(fd, obj.handle);
> +
> +	return ret;
> +}

Re: [igt-dev] [PATCH i-g-t 1/7] lib/gem_submission: Add kernel exec object alignment capability

[Zbigniew Kempczyński]

On Tue, Oct 12, 2021 at 09:47:18PM -0700, Dixit, Ashutosh wrote:
> On Thu, 07 Oct 2021 23:54:26 -0700, Zbigniew Kempczyński wrote:
> >
> > +bool gem_allows_passing_alignment(int fd)
> > +{
> > +	struct drm_i915_gem_exec_object2 obj = {
> > +		.handle = gem_create(fd, 4096),
> > +	};
> > +	struct drm_i915_gem_execbuffer2 execbuf = {
> > +		.buffers_ptr = to_user_pointer(&obj),
> > +		.buffer_count = 1,
> > +	};
> > +	bool ret;
> > +	const uint32_t bbe = MI_BATCH_BUFFER_END;
> > +
> > +	gem_write(fd, obj.handle, 0, &bbe, sizeof(bbe));
> > +	gem_execbuf(fd, &execbuf);
> > +
> > +	obj.alignment = 0x2000;
> 
> 8K? Shouldn't this be less than 4K?

I'm not sure how kernel check will look like so positive value larger
than 4K is sane for me. For example if in the kernel we will have:

if (entry->alignment != 0 && entry->alignment != 0x1000)
	return -EINVAL;

checking with 0x1000 would give me kernel supports alignment what
is not true. I'm saying I'm not sure because there's no patch 
kernel which land upstream yet. My trybot patch is in:

https://patchwork.freedesktop.org/series/95087/

but there's only generation check. 

--
Zbigniew

> 
> > +	ret = __gem_execbuf(fd, &execbuf) == 0;
> > +	gem_close(fd, obj.handle);
> > +
> > +	return ret;
> > +}

Re: [igt-dev] [PATCH i-g-t 1/7] lib/gem_submission: Add kernel exec object alignment capability

[Dixit, Ashutosh]

On Tue, 12 Oct 2021 22:27:45 -0700, Zbigniew Kempczyński wrote:
>
> On Tue, Oct 12, 2021 at 09:47:18PM -0700, Dixit, Ashutosh wrote:
> > On Thu, 07 Oct 2021 23:54:26 -0700, Zbigniew Kempczyński wrote:
> > >
> > > +bool gem_allows_passing_alignment(int fd)
> > > +{
> > > +	struct drm_i915_gem_exec_object2 obj = {
> > > +		.handle = gem_create(fd, 4096),
> > > +	};
> > > +	struct drm_i915_gem_execbuffer2 execbuf = {
> > > +		.buffers_ptr = to_user_pointer(&obj),
> > > +		.buffer_count = 1,
> > > +	};
> > > +	bool ret;
> > > +	const uint32_t bbe = MI_BATCH_BUFFER_END;
> > > +
> > > +	gem_write(fd, obj.handle, 0, &bbe, sizeof(bbe));
> > > +	gem_execbuf(fd, &execbuf);
> > > +
> > > +	obj.alignment = 0x2000;
> >
> > 8K? Shouldn't this be less than 4K?
>
> I'm not sure how kernel check will look like so positive value larger
> than 4K is sane for me. For example if in the kernel we will have:
>
> if (entry->alignment != 0 && entry->alignment != 0x1000)
>	return -EINVAL;

Sorry I am still not following why the alignment has to be > 4K. Since for
alignment we generally consider aligned to a 4K page, so an alignment value
which is multiple of 4K might not even be a correct test. I would just use
an alignment value of 64 here (kernel requires it to be a power of
2). Wouldn't that work? Thanks.

Re: [igt-dev] [PATCH i-g-t 1/7] lib/gem_submission: Add kernel exec object alignment capability

[Zbigniew Kempczyński]

On Wed, Oct 13, 2021 at 07:26:28PM -0700, Dixit, Ashutosh wrote:
> On Tue, 12 Oct 2021 22:27:45 -0700, Zbigniew Kempczyński wrote:
> >
> > On Tue, Oct 12, 2021 at 09:47:18PM -0700, Dixit, Ashutosh wrote:
> > > On Thu, 07 Oct 2021 23:54:26 -0700, Zbigniew Kempczyński wrote:
> > > >
> > > > +bool gem_allows_passing_alignment(int fd)
> > > > +{
> > > > +	struct drm_i915_gem_exec_object2 obj = {
> > > > +		.handle = gem_create(fd, 4096),
> > > > +	};
> > > > +	struct drm_i915_gem_execbuffer2 execbuf = {
> > > > +		.buffers_ptr = to_user_pointer(&obj),
> > > > +		.buffer_count = 1,
> > > > +	};
> > > > +	bool ret;
> > > > +	const uint32_t bbe = MI_BATCH_BUFFER_END;
> > > > +
> > > > +	gem_write(fd, obj.handle, 0, &bbe, sizeof(bbe));
> > > > +	gem_execbuf(fd, &execbuf);
> > > > +
> > > > +	obj.alignment = 0x2000;
> > >
> > > 8K? Shouldn't this be less than 4K?
> >
> > I'm not sure how kernel check will look like so positive value larger
> > than 4K is sane for me. For example if in the kernel we will have:
> >
> > if (entry->alignment != 0 && entry->alignment != 0x1000)
> >	return -EINVAL;
> 
> Sorry I am still not following why the alignment has to be > 4K. Since for
> alignment we generally consider aligned to a 4K page, so an alignment value
> which is multiple of 4K might not even be a correct test. I would just use
> an alignment value of 64 here (kernel requires it to be a power of
> 2). Wouldn't that work? Thanks.

Agree, on input any value which is power of two is correct. I just choosen
8K because it is a) page aligned b) power of two so definitely this value
can be used within kernel. 

alignment = 64 is a little bit tricky - it is correct but will be changed 
to minimum alignment before pinning so I would like to avoid such values.
I've spent some time to go over the pinning path according what has happen
with that 64 and I was surprised it is not used at all anywhere.

Resume: any value which is power of two is correct here, I just took 8K.

--
Zbigniew

Re: [igt-dev] [PATCH i-g-t 1/7] lib/gem_submission: Add kernel exec object alignment capability

[Dixit, Ashutosh]

On Thu, 14 Oct 2021 00:14:46 -0700, Zbigniew Kempczyński wrote:
>
> On Wed, Oct 13, 2021 at 07:26:28PM -0700, Dixit, Ashutosh wrote:
> > On Tue, 12 Oct 2021 22:27:45 -0700, Zbigniew Kempczyński wrote:
> > >
> > > On Tue, Oct 12, 2021 at 09:47:18PM -0700, Dixit, Ashutosh wrote:
> > > > On Thu, 07 Oct 2021 23:54:26 -0700, Zbigniew Kempczyński wrote:
> > > > >
> > > > > +bool gem_allows_passing_alignment(int fd)
> > > > > +{
> > > > > +	struct drm_i915_gem_exec_object2 obj = {
> > > > > +		.handle = gem_create(fd, 4096),
> > > > > +	};
> > > > > +	struct drm_i915_gem_execbuffer2 execbuf = {
> > > > > +		.buffers_ptr = to_user_pointer(&obj),
> > > > > +		.buffer_count = 1,
> > > > > +	};
> > > > > +	bool ret;
> > > > > +	const uint32_t bbe = MI_BATCH_BUFFER_END;
> > > > > +
> > > > > +	gem_write(fd, obj.handle, 0, &bbe, sizeof(bbe));
> > > > > +	gem_execbuf(fd, &execbuf);
> > > > > +
> > > > > +	obj.alignment = 0x2000;
> > > >
> > > > 8K? Shouldn't this be less than 4K?
> > >
> > > I'm not sure how kernel check will look like so positive value larger
> > > than 4K is sane for me. For example if in the kernel we will have:
> > >
> > > if (entry->alignment != 0 && entry->alignment != 0x1000)
> > >	return -EINVAL;
> >
> > Sorry I am still not following why the alignment has to be > 4K. Since for
> > alignment we generally consider aligned to a 4K page, so an alignment value
> > which is multiple of 4K might not even be a correct test. I would just use
> > an alignment value of 64 here (kernel requires it to be a power of
> > 2). Wouldn't that work? Thanks.
>
> Agree, on input any value which is power of two is correct. I just choosen
> 8K because it is a) page aligned b) power of two so definitely this value
> can be used within kernel.
>
> alignment = 64 is a little bit tricky - it is correct but will be changed
> to minimum alignment before pinning so I would like to avoid such values.
> I've spent some time to go over the pinning path according what has happen
> with that 64 and I was surprised it is not used at all anywhere.
>
> Resume: any value which is power of two is correct here, I just took 8K.

Yes I saw gem_exec_alignment later and it is using similar alignment
values. So I need to look some more to understand what this alignment is.

So please change the name to either gem_allows_obj_alignment or
gem_has_obj_alignment whichever you prefer. No need to resend the series,
please go ahead and merge the R-b patches. This one is also:

Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

[igt-dev] [PATCH i-g-t 2/7] lib/intel_batchbuffer: Detect and use kernel alignment capability

[Zbigniew Kempczyński]

For gens where relocations are supported kernel can set object offset
everywhere it wants but it honours the alignment setting.

For gens where we got no relocations and setting alignment is not
allowed in exec object we want to ensure allocator will still use it
to properly align the offset.

Detect kernel caps in alignment setting and use it for reloc/no-reloc
paths accordingly.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 lib/intel_batchbuffer.c | 9 +++++++--
 lib/intel_batchbuffer.h | 1 +
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 9c26fe207..ed7c25015 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -1335,6 +1335,7 @@ __intel_bb_create(int i915, uint32_t ctx, uint32_t size, bool do_relocs,
 
 	igt_assert(ibb);
 
+	ibb->allows_passing_alignment = gem_allows_passing_alignment(i915);
 	ibb->uses_full_ppgtt = gem_uses_full_ppgtt(i915);
 	ibb->devid = intel_get_drm_devid(i915);
 	ibb->gen = intel_gen(ibb->devid);
@@ -1783,6 +1784,7 @@ __add_to_cache(struct intel_bb *ibb, uint32_t handle)
 	igt_assert(object);
 
 	object->handle = handle;
+	object->alignment = 0;
 	found = tsearch((void *) object, &ibb->root, __compare_objects);
 
 	if (*found == object) {
@@ -1905,7 +1907,7 @@ intel_bb_add_object(struct intel_bb *ibb, uint32_t handle, uint64_t size,
 		   || ALIGN(offset, alignment) == offset);
 
 	object = __add_to_cache(ibb, handle);
-	object->alignment = alignment ?: 4096;
+	alignment = alignment ?: 4096;
 	__add_to_objects(ibb, object);
 
 	/*
@@ -1917,7 +1919,7 @@ intel_bb_add_object(struct intel_bb *ibb, uint32_t handle, uint64_t size,
 	if (INVALID_ADDR(object->offset)) {
 		if (INVALID_ADDR(offset)) {
 			offset = __intel_bb_get_offset(ibb, handle, size,
-						       object->alignment);
+						       alignment);
 		} else {
 			offset = offset & (ibb->gtt_size - 1);
 
@@ -1962,6 +1964,9 @@ intel_bb_add_object(struct intel_bb *ibb, uint32_t handle, uint64_t size,
 	if (ibb->uses_full_ppgtt && !ibb->enforce_relocs)
 		object->flags |= EXEC_OBJECT_PINNED;
 
+	if (ibb->allows_passing_alignment)
+		object->alignment = alignment;
+
 	return object;
 }
 
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index 58bddb1a1..728985274 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -476,6 +476,7 @@ struct intel_bb {
 	uint64_t gtt_size;
 	bool supports_48b_address;
 	bool uses_full_ppgtt;
+	bool allows_passing_alignment;
 
 	struct igt_pxp pxp;
 	uint32_t ctx;
-- 
2.26.0

Re: [igt-dev] [PATCH i-g-t 2/7] lib/intel_batchbuffer: Detect and use kernel alignment capability

[Dixit, Ashutosh]

On Thu, 07 Oct 2021 23:54:27 -0700, Zbigniew Kempczyński wrote:
>
> diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
> index 9c26fe207..ed7c25015 100644
> --- a/lib/intel_batchbuffer.c
> +++ b/lib/intel_batchbuffer.c
> @@ -1335,6 +1335,7 @@ __intel_bb_create(int i915, uint32_t ctx, uint32_t size, bool do_relocs,
>
>	igt_assert(ibb);
>
> +	ibb->allows_passing_alignment = gem_allows_passing_alignment(i915);
>	ibb->uses_full_ppgtt = gem_uses_full_ppgtt(i915);
>	ibb->devid = intel_get_drm_devid(i915);
>	ibb->gen = intel_gen(ibb->devid);
> @@ -1783,6 +1784,7 @@ __add_to_cache(struct intel_bb *ibb, uint32_t handle)
>	igt_assert(object);
>
>	object->handle = handle;
> +	object->alignment = 0;
>	found = tsearch((void *) object, &ibb->root, __compare_objects);
>
>	if (*found == object) {
> @@ -1905,7 +1907,7 @@ intel_bb_add_object(struct intel_bb *ibb, uint32_t handle, uint64_t size,
>		   || ALIGN(offset, alignment) == offset);
>
>	object = __add_to_cache(ibb, handle);
> -	object->alignment = alignment ?: 4096;
> +	alignment = alignment ?: 4096;

Can't we do:
	if (ibb->allows_passing_alignment)
		object->alignment = alignment ?: 4096;
So we don't need further changes in this function? Or it breaks something?

>	__add_to_objects(ibb, object);
>
>	/*
> @@ -1917,7 +1919,7 @@ intel_bb_add_object(struct intel_bb *ibb, uint32_t handle, uint64_t size,
>	if (INVALID_ADDR(object->offset)) {
>		if (INVALID_ADDR(offset)) {
>			offset = __intel_bb_get_offset(ibb, handle, size,
> -						       object->alignment);
> +						       alignment);
>		} else {
>			offset = offset & (ibb->gtt_size - 1);
>
> @@ -1962,6 +1964,9 @@ intel_bb_add_object(struct intel_bb *ibb, uint32_t handle, uint64_t size,
>	if (ibb->uses_full_ppgtt && !ibb->enforce_relocs)
>		object->flags |= EXEC_OBJECT_PINNED;
>
> +	if (ibb->allows_passing_alignment)
> +		object->alignment = alignment;
> +
>	return object;
>  }

Re: [igt-dev] [PATCH i-g-t 2/7] lib/intel_batchbuffer: Detect and use kernel alignment capability

[Zbigniew Kempczyński]

On Wed, Oct 13, 2021 at 07:37:22PM -0700, Dixit, Ashutosh wrote:
> On Thu, 07 Oct 2021 23:54:27 -0700, Zbigniew Kempczyński wrote:
> >
> > diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
> > index 9c26fe207..ed7c25015 100644
> > --- a/lib/intel_batchbuffer.c
> > +++ b/lib/intel_batchbuffer.c
> > @@ -1335,6 +1335,7 @@ __intel_bb_create(int i915, uint32_t ctx, uint32_t size, bool do_relocs,
> >
> >	igt_assert(ibb);
> >
> > +	ibb->allows_passing_alignment = gem_allows_passing_alignment(i915);
> >	ibb->uses_full_ppgtt = gem_uses_full_ppgtt(i915);
> >	ibb->devid = intel_get_drm_devid(i915);
> >	ibb->gen = intel_gen(ibb->devid);
> > @@ -1783,6 +1784,7 @@ __add_to_cache(struct intel_bb *ibb, uint32_t handle)
> >	igt_assert(object);
> >
> >	object->handle = handle;
> > +	object->alignment = 0;
> >	found = tsearch((void *) object, &ibb->root, __compare_objects);
> >
> >	if (*found == object) {
> > @@ -1905,7 +1907,7 @@ intel_bb_add_object(struct intel_bb *ibb, uint32_t handle, uint64_t size,
> >		   || ALIGN(offset, alignment) == offset);
> >
> >	object = __add_to_cache(ibb, handle);
> > -	object->alignment = alignment ?: 4096;
> > +	alignment = alignment ?: 4096;
> 
> Can't we do:
> 	if (ibb->allows_passing_alignment)
> 		object->alignment = alignment ?: 4096;
> So we don't need further changes in this function? Or it breaks something?

I think it will work at this place, object->alignment is touched twice:
1. first on __add_to_cache() and set to 0
2. second on finalizing object settings after acquiring offset

I added this on the bottom where object->... are filling with established
values. I just wanted to have all those settings in one place, not
object->alignment on the top and all the rest on the bottom. But there's
cosmetic and personal preference.

--
Zbigniew

> 
> >	__add_to_objects(ibb, object);
> >
> >	/*
> > @@ -1917,7 +1919,7 @@ intel_bb_add_object(struct intel_bb *ibb, uint32_t handle, uint64_t size,
> >	if (INVALID_ADDR(object->offset)) {
> >		if (INVALID_ADDR(offset)) {
> >			offset = __intel_bb_get_offset(ibb, handle, size,
> > -						       object->alignment);
> > +						       alignment);
> >		} else {
> >			offset = offset & (ibb->gtt_size - 1);
> >
> > @@ -1962,6 +1964,9 @@ intel_bb_add_object(struct intel_bb *ibb, uint32_t handle, uint64_t size,
> >	if (ibb->uses_full_ppgtt && !ibb->enforce_relocs)
> >		object->flags |= EXEC_OBJECT_PINNED;
> >
> > +	if (ibb->allows_passing_alignment)
> > +		object->alignment = alignment;
> > +
> >	return object;
> >  }

Re: [igt-dev] [PATCH i-g-t 2/7] lib/intel_batchbuffer: Detect and use kernel alignment capability

[Dixit, Ashutosh]

On Thu, 14 Oct 2021 00:25:29 -0700, Zbigniew Kempczyński wrote:
>
> On Wed, Oct 13, 2021 at 07:37:22PM -0700, Dixit, Ashutosh wrote:
> > On Thu, 07 Oct 2021 23:54:27 -0700, Zbigniew Kempczyński wrote:
> > >
> > > diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
> > > index 9c26fe207..ed7c25015 100644
> > > --- a/lib/intel_batchbuffer.c
> > > +++ b/lib/intel_batchbuffer.c
> > > @@ -1335,6 +1335,7 @@ __intel_bb_create(int i915, uint32_t ctx, uint32_t size, bool do_relocs,
> > >
> > >	igt_assert(ibb);
> > >
> > > +	ibb->allows_passing_alignment = gem_allows_passing_alignment(i915);
> > >	ibb->uses_full_ppgtt = gem_uses_full_ppgtt(i915);
> > >	ibb->devid = intel_get_drm_devid(i915);
> > >	ibb->gen = intel_gen(ibb->devid);
> > > @@ -1783,6 +1784,7 @@ __add_to_cache(struct intel_bb *ibb, uint32_t handle)
> > >	igt_assert(object);
> > >
> > >	object->handle = handle;
> > > +	object->alignment = 0;
> > >	found = tsearch((void *) object, &ibb->root, __compare_objects);
> > >
> > >	if (*found == object) {
> > > @@ -1905,7 +1907,7 @@ intel_bb_add_object(struct intel_bb *ibb, uint32_t handle, uint64_t size,
> > >		   || ALIGN(offset, alignment) == offset);
> > >
> > >	object = __add_to_cache(ibb, handle);
> > > -	object->alignment = alignment ?: 4096;
> > > +	alignment = alignment ?: 4096;
> >
> > Can't we do:
> >	if (ibb->allows_passing_alignment)
> >		object->alignment = alignment ?: 4096;
> > So we don't need further changes in this function? Or it breaks something?
>
> I think it will work at this place, object->alignment is touched twice:
> 1. first on __add_to_cache() and set to 0
> 2. second on finalizing object settings after acquiring offset
>
> I added this on the bottom where object->... are filling with established
> values. I just wanted to have all those settings in one place, not
> object->alignment on the top and all the rest on the bottom. But there's
> cosmetic and personal preference.

Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

[igt-dev] [PATCH i-g-t 3/7] tests/gem_exec_alignment: Add prerequisite alignment condition

[Zbigniew Kempczyński]

Skip the test if the kernel doesn't support passing object alignment.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 tests/i915/gem_exec_alignment.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tests/i915/gem_exec_alignment.c b/tests/i915/gem_exec_alignment.c
index c4611bd1e..f40b391c9 100644
--- a/tests/i915/gem_exec_alignment.c
+++ b/tests/i915/gem_exec_alignment.c
@@ -530,6 +530,7 @@ igt_main
 	igt_fixture {
 		fd = drm_open_driver(DRIVER_INTEL);
 		igt_require_gem(fd);
+		igt_require(gem_allows_passing_alignment(fd));
 	}
 
 	igt_subtest("single") /* basic! */
-- 
2.26.0

Re: [igt-dev] [PATCH i-g-t 3/7] tests/gem_exec_alignment: Add prerequisite alignment condition

[Dixit, Ashutosh]

On Thu, 07 Oct 2021 23:54:28 -0700, Zbigniew Kempczyński wrote:
>
> Skip the test if the kernel doesn't support passing object alignment.
>
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Petri Latvala <petri.latvala@intel.com>
> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> ---
>  tests/i915/gem_exec_alignment.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/tests/i915/gem_exec_alignment.c b/tests/i915/gem_exec_alignment.c
> index c4611bd1e..f40b391c9 100644
> --- a/tests/i915/gem_exec_alignment.c
> +++ b/tests/i915/gem_exec_alignment.c
> @@ -530,6 +530,7 @@ igt_main
>	igt_fixture {
>		fd = drm_open_driver(DRIVER_INTEL);
>		igt_require_gem(fd);
> +		igt_require(gem_allows_passing_alignment(fd));

How about renaming this function something like gem_allows_obj_alignment?
Otherwise this is:

Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

Re: [igt-dev] [PATCH i-g-t 3/7] tests/gem_exec_alignment: Add prerequisite alignment condition

[Zbigniew Kempczyński]

On Wed, Oct 13, 2021 at 09:12:36PM -0700, Dixit, Ashutosh wrote:
> On Thu, 07 Oct 2021 23:54:28 -0700, Zbigniew Kempczyński wrote:
> >
> > Skip the test if the kernel doesn't support passing object alignment.
> >
> > Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> > Cc: Petri Latvala <petri.latvala@intel.com>
> > Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> > ---
> >  tests/i915/gem_exec_alignment.c | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/tests/i915/gem_exec_alignment.c b/tests/i915/gem_exec_alignment.c
> > index c4611bd1e..f40b391c9 100644
> > --- a/tests/i915/gem_exec_alignment.c
> > +++ b/tests/i915/gem_exec_alignment.c
> > @@ -530,6 +530,7 @@ igt_main
> >	igt_fixture {
> >		fd = drm_open_driver(DRIVER_INTEL);
> >		igt_require_gem(fd);
> > +		igt_require(gem_allows_passing_alignment(fd));
> 
> How about renaming this function something like gem_allows_obj_alignment?
> Otherwise this is:

Yes, I like this name - it is much better than mine. I'll fix and resend.

--
Zbigniew

> 
> Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

[igt-dev] [PATCH i-g-t 4/7] tests/gem_evict_alignment: Skip if kernel doesn't support passing alignment

[Zbigniew Kempczyński]

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
---
 tests/i915/gem_evict_alignment.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tests/i915/gem_evict_alignment.c b/tests/i915/gem_evict_alignment.c
index e5176b9ba..ab1271788 100644
--- a/tests/i915/gem_evict_alignment.c
+++ b/tests/i915/gem_evict_alignment.c
@@ -198,6 +198,7 @@ igt_main
 		fd = drm_open_driver(DRIVER_INTEL);
 		igt_require_gem(fd);
 		gem_require_blitter(fd);
+		igt_require(gem_allows_passing_alignment(fd));
 		igt_fork_hang_detector(fd);
 	}
 
-- 
2.26.0

Re: [igt-dev] [PATCH i-g-t 4/7] tests/gem_evict_alignment: Skip if kernel doesn't support passing alignment

[Dixit, Ashutosh]

On Thu, 07 Oct 2021 23:54:29 -0700, Zbigniew Kempczyński wrote:
>
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> Cc: Petri Latvala <petri.latvala@intel.com>
> ---
>  tests/i915/gem_evict_alignment.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/tests/i915/gem_evict_alignment.c b/tests/i915/gem_evict_alignment.c
> index e5176b9ba..ab1271788 100644
> --- a/tests/i915/gem_evict_alignment.c
> +++ b/tests/i915/gem_evict_alignment.c
> @@ -198,6 +198,7 @@ igt_main
>		fd = drm_open_driver(DRIVER_INTEL);
>		igt_require_gem(fd);
>		gem_require_blitter(fd);
> +		igt_require(gem_allows_passing_alignment(fd));

Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

[igt-dev] [PATCH i-g-t 5/7] tests/i915_pm_rpm: Fix invalid alignment

[Zbigniew Kempczyński]

In theory kernel requires vma to be power of two aligned, but in
practice inserting vma requires alignment to be at least GTT min
alignment - which is page size atm. Change this alignment from 64->0
to allow test to run on gens where alignment must be zero in execbuf
as it will be page size aligned anyway.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 tests/i915/i915_pm_rpm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/i915/i915_pm_rpm.c b/tests/i915/i915_pm_rpm.c
index 62720d02b..576b4b466 100644
--- a/tests/i915/i915_pm_rpm.c
+++ b/tests/i915/i915_pm_rpm.c
@@ -1234,7 +1234,7 @@ static void submit_blt_cmd(uint32_t dst_handle, int dst_size,
 	relocs[0].write_domain = I915_GEM_DOMAIN_RENDER;
 
 	objs[0].handle = dst_handle;
-	objs[0].alignment = 64;
+	objs[0].alignment = 0;
 
 	objs[1].handle = batch_handle;
 	objs[1].relocation_count = !ahnd ? 1 : 0;
-- 
2.26.0

Re: [igt-dev] [PATCH i-g-t 5/7] tests/i915_pm_rpm: Fix invalid alignment

[Dixit, Ashutosh]

On Thu, 07 Oct 2021 23:54:30 -0700, Zbigniew Kempczyński wrote:
>
> In theory kernel requires vma to be power of two aligned, but in
> practice inserting vma requires alignment to be at least GTT min
> alignment - which is page size atm. Change this alignment from 64->0
> to allow test to run on gens where alignment must be zero in execbuf
> as it will be page size aligned anyway.
>
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Petri Latvala <petri.latvala@intel.com>
> Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
> ---
>  tests/i915/i915_pm_rpm.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/tests/i915/i915_pm_rpm.c b/tests/i915/i915_pm_rpm.c
> index 62720d02b..576b4b466 100644
> --- a/tests/i915/i915_pm_rpm.c
> +++ b/tests/i915/i915_pm_rpm.c
> @@ -1234,7 +1234,7 @@ static void submit_blt_cmd(uint32_t dst_handle, int dst_size,
>	relocs[0].write_domain = I915_GEM_DOMAIN_RENDER;
>
>	objs[0].handle = dst_handle;
> -	objs[0].alignment = 64;
> +	objs[0].alignment = 0;

Yes I agree alignment is probably useless in this test:

Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

[igt-dev] [PATCH i-g-t 6/7] benchmarks/gem_exec_fault: Add timeout argument

[Zbigniew Kempczyński]

Add timeout argument and change elapsed time to inner loop to
be more precise in timeout processing.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
---
 benchmarks/gem_exec_fault.c | 24 ++++++++++++++++++------
 1 file changed, 18 insertions(+), 6 deletions(-)

diff --git a/benchmarks/gem_exec_fault.c b/benchmarks/gem_exec_fault.c
index d53fab964..fe940b44c 100644
--- a/benchmarks/gem_exec_fault.c
+++ b/benchmarks/gem_exec_fault.c
@@ -49,6 +49,7 @@
 #include "ioctl_wrappers.h"
 
 #define ENGINE_FLAGS  (I915_EXEC_RING_MASK | I915_EXEC_BSD_MASK)
+#define DEFAULT_TIMEOUT 2.f
 
 static double elapsed(const struct timespec *start,
 		      const struct timespec *end)
@@ -64,7 +65,8 @@ static uint32_t batch(int fd, uint64_t size)
 	return handle;
 }
 
-static int loop(uint64_t size, unsigned ring, int reps, int ncpus, unsigned flags)
+static int loop(uint64_t size, unsigned ring, int reps, int ncpus,
+		unsigned flags, float timeout)
 {
 	struct drm_i915_gem_execbuffer2 execbuf;
 	struct drm_i915_gem_exec_object2 obj;
@@ -128,10 +130,14 @@ static int loop(uint64_t size, unsigned ring, int reps, int ncpus, unsigned flag
 					/* fault out */
 					obj.alignment = 1ull << 63;
 					__gem_execbuf(fd, &execbuf);
-				}
 
-				clock_gettime(CLOCK_MONOTONIC, &end);
-			} while (elapsed(&start, &end) < 2.);
+					clock_gettime(CLOCK_MONOTONIC, &end);
+					if (elapsed(&start, &end) >= timeout) {
+						timeout = -1.0;
+						break;
+					}
+				}
+			} while (timeout > 0);
 
 			gem_sync(fd, obj.handle);
 			clock_gettime(CLOCK_MONOTONIC, &end);
@@ -156,8 +162,9 @@ int main(int argc, char **argv)
 	int reps = 1;
 	int ncpus = 1;
 	int c;
+	float timeout = DEFAULT_TIMEOUT;
 
-	while ((c = getopt (argc, argv, "e:r:s:f")) != -1) {
+	while ((c = getopt (argc, argv, "e:r:s:ft:")) != -1) {
 		switch (c) {
 		case 'e':
 			if (strcmp(optarg, "rcs") == 0)
@@ -190,10 +197,15 @@ int main(int argc, char **argv)
 				size = 4096;
 			break;
 
+		case 't':
+			timeout = atof(optarg);
+			igt_assert_f(timeout > 0, "Timeout must be > 0\n");
+			break;
+
 		default:
 			break;
 		}
 	}
 
-	return loop(size, ring, reps, ncpus, flags);
+	return loop(size, ring, reps, ncpus, flags, timeout);
 }
-- 
2.26.0

Re: [igt-dev] [PATCH i-g-t 6/7] benchmarks/gem_exec_fault: Add timeout argument

[Dixit, Ashutosh]

On Thu, 07 Oct 2021 23:54:31 -0700, Zbigniew Kempczyński wrote:
>
> +static int loop(uint64_t size, unsigned ring, int reps, int ncpus,
> +		unsigned flags, float timeout)
>  {
>	struct drm_i915_gem_execbuffer2 execbuf;
>	struct drm_i915_gem_exec_object2 obj;
> @@ -128,10 +130,14 @@ static int loop(uint64_t size, unsigned ring, int reps, int ncpus, unsigned flag
>					/* fault out */
>					obj.alignment = 1ull << 63;
>					__gem_execbuf(fd, &execbuf);
> -				}
>
> -				clock_gettime(CLOCK_MONOTONIC, &end);
> -			} while (elapsed(&start, &end) < 2.);
> +					clock_gettime(CLOCK_MONOTONIC, &end);
> +					if (elapsed(&start, &end) >= timeout) {
> +						timeout = -1.0;

Just a small nit, I don't think we need to set it to -1 here. We can just
leave the "while (elapsed(&start, &end) < timeout);" check in the outer loop
too. So please change if you agree. Otherwise:

Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

> +						break;
> +					}
> +				}
> +			} while (timeout > 0);
>
>			gem_sync(fd, obj.handle);
>			clock_gettime(CLOCK_MONOTONIC, &end);

Re: [igt-dev] [PATCH i-g-t 6/7] benchmarks/gem_exec_fault: Add timeout argument

[Zbigniew Kempczyński]

On Wed, Oct 13, 2021 at 09:24:18PM -0700, Dixit, Ashutosh wrote:
> On Thu, 07 Oct 2021 23:54:31 -0700, Zbigniew Kempczyński wrote:
> >
> > +static int loop(uint64_t size, unsigned ring, int reps, int ncpus,
> > +		unsigned flags, float timeout)
> >  {
> >	struct drm_i915_gem_execbuffer2 execbuf;
> >	struct drm_i915_gem_exec_object2 obj;
> > @@ -128,10 +130,14 @@ static int loop(uint64_t size, unsigned ring, int reps, int ncpus, unsigned flag
> >					/* fault out */
> >					obj.alignment = 1ull << 63;
> >					__gem_execbuf(fd, &execbuf);
> > -				}
> >
> > -				clock_gettime(CLOCK_MONOTONIC, &end);
> > -			} while (elapsed(&start, &end) < 2.);
> > +					clock_gettime(CLOCK_MONOTONIC, &end);
> > +					if (elapsed(&start, &end) >= timeout) {
> > +						timeout = -1.0;
> 
> Just a small nit, I don't think we need to set it to -1 here. We can just
> leave the "while (elapsed(&start, &end) < timeout);" check in the outer loop
> too. So please change if you agree. Otherwise:

I just wanted to avoid calling elapsed() twice, that's why I changed to
simpler expression. Timeout cannot be negative so it is good as stop
condition to outer loop.

I dare get your r-b here.

--
Zbigniew

> 
> Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> 
> > +						break;
> > +					}
> > +				}
> > +			} while (timeout > 0);
> >
> >			gem_sync(fd, obj.handle);
> >			clock_gettime(CLOCK_MONOTONIC, &end);

Re: [igt-dev] [PATCH i-g-t 6/7] benchmarks/gem_exec_fault: Add timeout argument

[Dixit, Ashutosh]

On Thu, 14 Oct 2021 00:47:39 -0700, Zbigniew Kempczyński wrote:
> On Wed, Oct 13, 2021 at 09:24:18PM -0700, Dixit, Ashutosh wrote:
> > On Thu, 07 Oct 2021 23:54:31 -0700, Zbigniew Kempczyński wrote:
> > >
> > > +static int loop(uint64_t size, unsigned ring, int reps, int ncpus,
> > > +		unsigned flags, float timeout)
> > >  {
> > >	struct drm_i915_gem_execbuffer2 execbuf;
> > >	struct drm_i915_gem_exec_object2 obj;
> > > @@ -128,10 +130,14 @@ static int loop(uint64_t size, unsigned ring, int reps, int ncpus, unsigned flag
> > >					/* fault out */
> > >					obj.alignment = 1ull << 63;
> > >					__gem_execbuf(fd, &execbuf);
> > > -				}
> > >
> > > -				clock_gettime(CLOCK_MONOTONIC, &end);
> > > -			} while (elapsed(&start, &end) < 2.);
> > > +					clock_gettime(CLOCK_MONOTONIC, &end);
> > > +					if (elapsed(&start, &end) >= timeout) {
> > > +						timeout = -1.0;
> >
> > Just a small nit, I don't think we need to set it to -1 here. We can just
> > leave the "while (elapsed(&start, &end) < timeout);" check in the outer loop
> > too. So please change if you agree. Otherwise:
>
> I just wanted to avoid calling elapsed() twice, that's why I changed to
> simpler expression. Timeout cannot be negative so it is good as stop
> condition to outer loop.
>
> I dare get your r-b here.

Sure, just a matter of personal preference. Already R-b.

>
> --
> Zbigniew
>
> >
> > Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> >
> > > +						break;
> > > +					}
> > > +				}
> > > +			} while (timeout > 0);
> > >
> > >			gem_sync(fd, obj.handle);
> > >			clock_gettime(CLOCK_MONOTONIC, &end);

[igt-dev] [PATCH i-g-t 7/7] benchmarks/gem_exec_fault: Add softpin mode to support gens with ppgtt

[Zbigniew Kempczyński]

Alignment trick doesn't work properly for ppgtt gens - kernel is able
to keep previous offset and doesn't call unbind/bind. With softpin
on ppgtt we're able to enforce rebind and benchmark should behave
correctly on such gens.

To avoid inaccurate results kernel CONFIG_PROVE_LOCKING should be set
to N, otherwise kernel can call unbind/bind for same offset more than
one (backoff is not visible from userspace).

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 benchmarks/gem_exec_fault.c | 47 +++++++++++++++++++++++++++++++++----
 1 file changed, 43 insertions(+), 4 deletions(-)

diff --git a/benchmarks/gem_exec_fault.c b/benchmarks/gem_exec_fault.c
index fe940b44c..40f11f4f1 100644
--- a/benchmarks/gem_exec_fault.c
+++ b/benchmarks/gem_exec_fault.c
@@ -43,7 +43,9 @@
 #include "drm.h"
 #include "drmtest.h"
 #include "i915/gem_create.h"
+#include "i915/gem_submission.h"
 #include "igt_stats.h"
+#include "intel_allocator.h"
 #include "intel_io.h"
 #include "intel_reg.h"
 #include "ioctl_wrappers.h"
@@ -74,11 +76,28 @@ static int loop(uint64_t size, unsigned ring, int reps, int ncpus,
 	unsigned nengine;
 	double *shared;
 	int fd;
+	bool has_ppgtt;
 
 	shared = mmap(0, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0);
 
 	fd = drm_open_driver(DRIVER_INTEL);
 
+	/*
+	 * For older gens .alignment = 1ull << 63 lead do bind/unbind,
+	 * what doesn't work for newer gens with ppgtt.
+	 * For ppgtt case we use reloc allocator which would just assigns
+	 * new offset for each batch. This way we enforce bind/unbind vma
+	 * for each execbuf.
+	 */
+	has_ppgtt = gem_uses_full_ppgtt(fd);
+	if (has_ppgtt) {
+		igt_info("Using softpin mode\n");
+		intel_allocator_multiprocess_start();
+	} else {
+		igt_assert(gem_allows_passing_alignment(fd));
+		igt_info("Using alignment mode\n");
+	}
+
 	memset(&obj, 0, sizeof(obj));
 	obj.handle = batch(fd, 4096);
 
@@ -92,6 +111,7 @@ static int loop(uint64_t size, unsigned ring, int reps, int ncpus,
 		if (__gem_execbuf(fd, &execbuf))
 			return 77;
 	}
+
 	/* let the small object leak; ideally blocking the low address */
 
 	nengine = 0;
@@ -106,7 +126,7 @@ static int loop(uint64_t size, unsigned ring, int reps, int ncpus,
 		engines[nengine++] = ring;
 
 	if (size > 1ul << 31)
-		obj.flags |= 1 << 3;
+		obj.flags |= EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
 
 	while (reps--) {
 		memset(shared, 0, 4096);
@@ -114,10 +134,14 @@ static int loop(uint64_t size, unsigned ring, int reps, int ncpus,
 		igt_fork(child, ncpus) {
 			struct timespec start, end;
 			unsigned count = 0;
+			uint64_t ahnd = 0;
 
 			obj.handle = batch(fd, size);
 			obj.offset = -1;
 
+			if (has_ppgtt)
+				ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+
 			clock_gettime(CLOCK_MONOTONIC, &start);
 			do {
 				for (int inner = 0; inner < 1024; inner++) {
@@ -127,9 +151,14 @@ static int loop(uint64_t size, unsigned ring, int reps, int ncpus,
 					obj.alignment = 0;
 					gem_execbuf(fd, &execbuf);
 
-					/* fault out */
-					obj.alignment = 1ull << 63;
-					__gem_execbuf(fd, &execbuf);
+					if (ahnd) {
+						obj.offset = get_offset(ahnd, obj.handle, size, 0);
+						obj.flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+					} else {
+						/* fault out */
+						obj.alignment = 1ull << 63;
+						__gem_execbuf(fd, &execbuf);
+					}
 
 					clock_gettime(CLOCK_MONOTONIC, &end);
 					if (elapsed(&start, &end) >= timeout) {
@@ -144,6 +173,8 @@ static int loop(uint64_t size, unsigned ring, int reps, int ncpus,
 			shared[child] = 1e6*elapsed(&start, &end) / count / 2;
 
 			gem_close(fd, obj.handle);
+			if (ahnd)
+				intel_allocator_close(ahnd);
 		}
 		igt_waitchildren();
 
@@ -151,9 +182,17 @@ static int loop(uint64_t size, unsigned ring, int reps, int ncpus,
 			shared[ncpus] += shared[child];
 		printf("%7.3f\n", shared[ncpus] / ncpus);
 	}
+
+	if (has_ppgtt)
+		intel_allocator_multiprocess_stop();
+
 	return 0;
 }
 
+/*
+ * NOTE: Ensure prove locking in the kernel is off, otherwise results
+ * would be inaccurate.
+ */
 int main(int argc, char **argv)
 {
 	unsigned ring = I915_EXEC_RENDER;
-- 
2.26.0

Re: [igt-dev] [PATCH i-g-t 7/7] benchmarks/gem_exec_fault: Add softpin mode to support gens with ppgtt

[Dixit, Ashutosh]

On Thu, 07 Oct 2021 23:54:32 -0700, Zbigniew Kempczyński wrote:
>
> +	/*
> +	 * For older gens .alignment = 1ull << 63 lead do bind/unbind,
> +	 * what doesn't work for newer gens with ppgtt.
> +	 * For ppgtt case we use reloc allocator which would just assigns
> +	 * new offset for each batch. This way we enforce bind/unbind vma
> +	 * for each execbuf.

So assigning a new offset will cause a new fault-in (bind) but not sure if
it will cause an actual fault-out (unbind). Though I am not sure if there
is actually a way to force it to happen if this doesn't work? Is there a
way to verify that the unbind is actually happening?

Neither I am sure how setting the 'alignment = 1ull << 63' caused a fault
out in the older code.

> +	 */
> +	has_ppgtt = gem_uses_full_ppgtt(fd);
> +	if (has_ppgtt) {
> +		igt_info("Using softpin mode\n");
> +		intel_allocator_multiprocess_start();
> +	} else {
> +		igt_assert(gem_allows_passing_alignment(fd));

I think this should be igt_require for the test to skip rather than fail.

> +/*
> + * NOTE: Ensure prove locking in the kernel is off, otherwise results
> + * would be inaccurate.
> + */

This is really a debug setting, any such setting (say lockdep, kmemchek
etc.) will affect benchmarks. So not sure if this specifically needs to be
called out.

Re: [igt-dev] [PATCH i-g-t 7/7] benchmarks/gem_exec_fault: Add softpin mode to support gens with ppgtt

[Dixit, Ashutosh]

On Wed, 13 Oct 2021 22:01:22 -0700, Dixit, Ashutosh wrote:
>
> On Thu, 07 Oct 2021 23:54:32 -0700, Zbigniew Kempczyński wrote:
> >
> > +	/*
> > +	 * For older gens .alignment = 1ull << 63 lead do bind/unbind,
> > +	 * what doesn't work for newer gens with ppgtt.
> > +	 * For ppgtt case we use reloc allocator which would just assigns
> > +	 * new offset for each batch. This way we enforce bind/unbind vma
> > +	 * for each execbuf.
>
> So assigning a new offset will cause a new fault-in (bind) but not sure if
> it will cause an actual fault-out (unbind). Though I am not sure if there
> is actually a way to force it to happen if this doesn't work? Is there a
> way to verify that the unbind is actually happening?

Maybe if assign the same offset to a different object/page that will cause
a fault-out (unbind) followed by a fault-in (bind).

Re: [igt-dev] [PATCH i-g-t 7/7] benchmarks/gem_exec_fault: Add softpin mode to support gens with ppgtt

[Zbigniew Kempczyński]

On Wed, Oct 13, 2021 at 10:01:22PM -0700, Dixit, Ashutosh wrote:
> On Thu, 07 Oct 2021 23:54:32 -0700, Zbigniew Kempczyński wrote:
> >
> > +	/*
> > +	 * For older gens .alignment = 1ull << 63 lead do bind/unbind,
> > +	 * what doesn't work for newer gens with ppgtt.
> > +	 * For ppgtt case we use reloc allocator which would just assigns
> > +	 * new offset for each batch. This way we enforce bind/unbind vma
> > +	 * for each execbuf.
> 
> So assigning a new offset will cause a new fault-in (bind) but not sure if
> it will cause an actual fault-out (unbind). Though I am not sure if there
> is actually a way to force it to happen if this doesn't work? Is there a
> way to verify that the unbind is actually happening?
> 
> Neither I am sure how setting the 'alignment = 1ull << 63' caused a fault
> out in the older code.

I got no access to !ppgtt gen but for my understanding in __gem_execbuf()
we will enforce unbind (trying to get offset at 1ull << 63) what is impossible
so unbind path will occur and some error code will be returned. But after
this we got object unbound so next time on !ppgtt gens when we set 0 alignment
kernel will choose some free offset for us. 

> 
> > +	 */
> > +	has_ppgtt = gem_uses_full_ppgtt(fd);
> > +	if (has_ppgtt) {
> > +		igt_info("Using softpin mode\n");
> > +		intel_allocator_multiprocess_start();
> > +	} else {
> > +		igt_assert(gem_allows_passing_alignment(fd));
> 
> I think this should be igt_require for the test to skip rather than fail.

I would not, I think for !ppgtt we want to have possibility passing 
alignment and benchmark requires that. Fail is much better imo because 
it will show something wrong has happened in the kernel we don't support.
And it requires attention from our side whereas skip may suggest it is 
expected while is not.

> 
> > +/*
> > + * NOTE: Ensure prove locking in the kernel is off, otherwise results
> > + * would be inaccurate.
> > + */
> 
> This is really a debug setting, any such setting (say lockdep, kmemchek
> etc.) will affect benchmarks. So not sure if this specifically needs to be
> called out.

You're right - this comment is unnecessary here. Any debugging options
in the kernel will have influence on benchmarking so we shouldn't run
benchmarks there.

--
Zbigniew

[igt-dev] ✓ Fi.CI.BAT: success for Prepare IGTs to allow only zero alignment

[Patchwork]

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== Series Details ==

Series: Prepare IGTs to allow only zero alignment
URL   : https://patchwork.freedesktop.org/series/95597/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10697 -> IGTPW_6300
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/index.html

Known issues
------------

  Here are the changes found in IGTPW_6300 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_basic@query-info:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][1] ([fdo#109271])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/fi-kbl-soraka/igt@amdgpu/amd_basic@query-info.html

  * igt@amdgpu/amd_basic@semaphore:
    - fi-bdw-5557u:       NOTRUN -> [SKIP][2] ([fdo#109271]) +27 similar issues
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/fi-bdw-5557u/igt@amdgpu/amd_basic@semaphore.html

  * igt@amdgpu/amd_cs_nop@nop-compute0:
    - fi-ilk-650:         NOTRUN -> [SKIP][3] ([fdo#109271]) +35 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/fi-ilk-650/igt@amdgpu/amd_cs_nop@nop-compute0.html

  * igt@core_hotunplug@unbind-rebind:
    - fi-bdw-5557u:       NOTRUN -> [WARN][4] ([i915#3718])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/fi-bdw-5557u/igt@core_hotunplug@unbind-rebind.html

  * igt@kms_chamelium@dp-crc-fast:
    - fi-kbl-7500u:       [PASS][5] -> [FAIL][6] ([i915#1372])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
    - fi-bdw-5557u:       NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/fi-bdw-5557u/igt@kms_chamelium@dp-crc-fast.html

  * igt@kms_chamelium@dp-hpd-fast:
    - fi-ilk-650:         NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/fi-ilk-650/igt@kms_chamelium@dp-hpd-fast.html

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s3:
    - fi-tgl-1115g4:      [FAIL][9] ([i915#1888]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s3.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/fi-tgl-1115g4/igt@gem_exec_suspend@basic-s3.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-cml-u2:          [DMESG-WARN][11] ([i915#4269]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372
  [i915#1759]: https://gitlab.freedesktop.org/drm/intel/issues/1759
  [i915#1888]: https://gitlab.freedesktop.org/drm/intel/issues/1888
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#3718]: https://gitlab.freedesktop.org/drm/intel/issues/3718
  [i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269


Participating hosts (43 -> 38)
------------------------------

  Additional (1): fi-ilk-650 
  Missing    (6): fi-ilk-m540 bat-dg1-6 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 bat-jsl-1 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_6237 -> IGTPW_6300

  CI-20190529: 20190529
  CI_DRM_10697: f03304d71481e701bfdb0d6344741100542fec77 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_6300: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/index.html
  IGT_6237: 910b5caac6625d2bf0b6c1dde502451431bd0159 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/index.html

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[igt-dev] ✓ Fi.CI.IGT: success for Prepare IGTs to allow only zero alignment

[Patchwork]

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== Series Details ==

Series: Prepare IGTs to allow only zero alignment
URL   : https://patchwork.freedesktop.org/series/95597/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10697_full -> IGTPW_6300_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/index.html

Known issues
------------

  Here are the changes found in IGTPW_6300_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_create@create-massive:
    - shard-glk:          NOTRUN -> [DMESG-WARN][1] ([i915#3002])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-glk9/igt@gem_create@create-massive.html

  * igt@gem_ctx_persistence@process:
    - shard-snb:          NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1099]) +4 similar issues
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-snb6/igt@gem_ctx_persistence@process.html

  * igt@gem_eio@in-flight-contexts-immediate:
    - shard-iclb:         [PASS][3] -> [TIMEOUT][4] ([i915#3070])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/shard-iclb2/igt@gem_eio@in-flight-contexts-immediate.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-iclb5/igt@gem_eio@in-flight-contexts-immediate.html

  * igt@gem_eio@unwedge-stress:
    - shard-tglb:         [PASS][5] -> [TIMEOUT][6] ([i915#2369] / [i915#3063] / [i915#3648])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/shard-tglb8/igt@gem_eio@unwedge-stress.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-tglb3/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
    - shard-kbl:          NOTRUN -> [FAIL][7] ([i915#2842]) +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-kbl6/igt@gem_exec_fair@basic-none-solo@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-tglb:         [PASS][8] -> [FAIL][9] ([i915#2842]) +3 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/shard-tglb5/igt@gem_exec_fair@basic-pace-solo@rcs0.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-tglb8/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_exec_fair@basic-pace@vecs0:
    - shard-glk:          [PASS][10] -> [FAIL][11] ([i915#2842]) +4 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/shard-glk9/igt@gem_exec_fair@basic-pace@vecs0.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-glk7/igt@gem_exec_fair@basic-pace@vecs0.html

  * igt@gem_exec_whisper@basic-fds-priority:
    - shard-glk:          [PASS][12] -> [DMESG-WARN][13] ([i915#118])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/shard-glk5/igt@gem_exec_whisper@basic-fds-priority.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-glk8/igt@gem_exec_whisper@basic-fds-priority.html

  * igt@gem_huc_copy@huc-copy:
    - shard-apl:          NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#2190])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-apl1/igt@gem_huc_copy@huc-copy.html

  * igt@gem_pread@exhaustion:
    - shard-apl:          NOTRUN -> [WARN][15] ([i915#2658])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-apl1/igt@gem_pread@exhaustion.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-snb:          NOTRUN -> [WARN][16] ([i915#2658])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-snb7/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_pxp@verify-pxp-stale-buf-optout-execution:
    - shard-tglb:         NOTRUN -> [SKIP][17] ([i915#4270])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-tglb3/igt@gem_pxp@verify-pxp-stale-buf-optout-execution.html

  * igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-yf-tiled:
    - shard-iclb:         NOTRUN -> [SKIP][18] ([i915#768])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-iclb8/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-yf-tiled.html

  * igt@gem_softpin@noreloc-s3:
    - shard-kbl:          NOTRUN -> [DMESG-WARN][19] ([i915#180])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-kbl4/igt@gem_softpin@noreloc-s3.html

  * igt@gem_sync@basic-many-each:
    - shard-kbl:          [PASS][20] -> [INCOMPLETE][21] ([i915#4274])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/shard-kbl7/igt@gem_sync@basic-many-each.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-kbl3/igt@gem_sync@basic-many-each.html
    - shard-iclb:         [PASS][22] -> [INCOMPLETE][23] ([i915#4274])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/shard-iclb4/igt@gem_sync@basic-many-each.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-iclb6/igt@gem_sync@basic-many-each.html

  * igt@gem_userptr_blits@dmabuf-unsync:
    - shard-tglb:         NOTRUN -> [SKIP][24] ([i915#3297]) +1 similar issue
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-tglb8/igt@gem_userptr_blits@dmabuf-unsync.html

  * igt@gem_userptr_blits@input-checking:
    - shard-snb:          NOTRUN -> [DMESG-WARN][25] ([i915#3002])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-snb6/igt@gem_userptr_blits@input-checking.html

  * igt@gen7_exec_parse@load-register-reg:
    - shard-tglb:         NOTRUN -> [SKIP][26] ([fdo#109289])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-tglb3/igt@gen7_exec_parse@load-register-reg.html

  * igt@gen9_exec_parse@cmd-crossing-page:
    - shard-tglb:         NOTRUN -> [SKIP][27] ([i915#2856])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-tglb1/igt@gen9_exec_parse@cmd-crossing-page.html
    - shard-iclb:         NOTRUN -> [SKIP][28] ([i915#2856])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-iclb7/igt@gen9_exec_parse@cmd-crossing-page.html

  * igt@i915_pm_dc@dc6-dpms:
    - shard-kbl:          NOTRUN -> [FAIL][29] ([i915#454])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-kbl7/igt@i915_pm_dc@dc6-dpms.html

  * igt@kms_big_fb@linear-64bpp-rotate-270:
    - shard-tglb:         NOTRUN -> [SKIP][30] ([fdo#111614])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-tglb6/igt@kms_big_fb@linear-64bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-glk:          NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#3777])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-glk6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
    - shard-apl:          NOTRUN -> [SKIP][32] ([fdo#109271] / [i915#3777]) +2 similar issues
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-apl6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@yf-tiled-32bpp-rotate-270:
    - shard-tglb:         NOTRUN -> [SKIP][33] ([fdo#111615]) +3 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-tglb1/igt@kms_big_fb@yf-tiled-32bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-64bpp-rotate-270:
    - shard-iclb:         NOTRUN -> [SKIP][34] ([fdo#110723])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-iclb3/igt@kms_big_fb@yf-tiled-64bpp-rotate-270.html

  * igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs:
    - shard-glk:          NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#3886]) +4 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-glk5/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs.html
    - shard-tglb:         NOTRUN -> [SKIP][36] ([i915#3689] / [i915#3886])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-tglb3/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
    - shard-apl:          NOTRUN -> [SKIP][37] ([fdo#109271] / [i915#3886]) +5 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-apl3/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
    - shard-kbl:          NOTRUN -> [SKIP][38] ([fdo#109271] / [i915#3886]) +6 similar issues
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-kbl1/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][39] ([i915#3689]) +1 similar issue
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-tglb2/igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_ccs.html

  * igt@kms_chamelium@dp-hpd-storm-disable:
    - shard-glk:          NOTRUN -> [SKIP][40] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-glk4/igt@kms_chamelium@dp-hpd-storm-disable.html

  * igt@kms_chamelium@dp-mode-timings:
    - shard-apl:          NOTRUN -> [SKIP][41] ([fdo#109271] / [fdo#111827]) +20 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-apl2/igt@kms_chamelium@dp-mode-timings.html

  * igt@kms_chamelium@hdmi-hpd-storm:
    - shard-kbl:          NOTRUN -> [SKIP][42] ([fdo#109271] / [fdo#111827]) +13 similar issues
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-kbl6/igt@kms_chamelium@hdmi-hpd-storm.html

  * igt@kms_color_chamelium@pipe-a-ctm-blue-to-red:
    - shard-snb:          NOTRUN -> [SKIP][43] ([fdo#109271] / [fdo#111827]) +13 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-snb5/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html
    - shard-iclb:         NOTRUN -> [SKIP][44] ([fdo#109284] / [fdo#111827])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-iclb5/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html

  * igt@kms_color_chamelium@pipe-d-ctm-0-25:
    - shard-tglb:         NOTRUN -> [SKIP][45] ([fdo#109284] / [fdo#111827]) +3 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-tglb1/igt@kms_color_chamelium@pipe-d-ctm-0-25.html
    - shard-iclb:         NOTRUN -> [SKIP][46] ([fdo#109278] / [fdo#109284] / [fdo#111827])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-iclb3/igt@kms_color_chamelium@pipe-d-ctm-0-25.html

  * igt@kms_content_protection@srm:
    - shard-kbl:          NOTRUN -> [TIMEOUT][47] ([i915#1319])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-kbl4/igt@kms_content_protection@srm.html

  * igt@kms_cursor_crc@pipe-a-cursor-32x32-onscreen:
    - shard-tglb:         NOTRUN -> [SKIP][48] ([i915#3319])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-tglb3/igt@kms_cursor_crc@pipe-a-cursor-32x32-onscreen.html

  * igt@kms_cursor_crc@pipe-a-cursor-512x170-rapid-movement:
    - shard-tglb:         NOTRUN -> [SKIP][49] ([i915#3359])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-tglb5/igt@kms_cursor_crc@pipe-a-cursor-512x170-rapid-movement.html

  * igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque:
    - shard-kbl:          [PASS][50] -> [FAIL][51] ([i915#3444])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque.html
    - shard-iclb:         [PASS][52] -> [FAIL][53] ([i915#3444])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/shard-iclb8/igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-iclb7/igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque.html
    - shard-glk:          [PASS][54] -> [FAIL][55] ([i915#3444])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/shard-glk9/igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-glk5/igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque.html
    - shard-tglb:         [PASS][56] -> [FAIL][57] ([i915#2124] / [i915#4024])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/shard-tglb5/igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-tglb1/igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque.html

  * igt@kms_cursor_crc@pipe-b-cursor-suspend:
    - shard-apl:          NOTRUN -> [DMESG-WARN][58] ([i915#180]) +1 similar issue
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-apl3/igt@kms_cursor_crc@pipe-b-cursor-suspend.html

  * igt@kms_cursor_crc@pipe-d-cursor-128x42-offscreen:
    - shard-iclb:         NOTRUN -> [SKIP][59] ([fdo#109278]) +1 similar issue
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-iclb5/igt@kms_cursor_crc@pipe-d-cursor-128x42-offscreen.html

  * igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge:
    - shard-snb:          NOTRUN -> [SKIP][60] ([fdo#109271]) +352 similar issues
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-snb2/igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge.html

  * igt@kms_cursor_legacy@pipe-d-torture-bo:
    - shard-glk:          NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#533])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-glk5/igt@kms_cursor_legacy@pipe-d-torture-bo.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2:
    - shard-glk:          [PASS][62] -> [FAIL][63] ([i915#79])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@2x-flip-vs-rmfb:
    - shard-tglb:         NOTRUN -> [SKIP][64] ([fdo#111825]) +5 similar issues
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-tglb8/igt@kms_flip@2x-flip-vs-rmfb.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
    - shard-apl:          NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#2672])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-apl8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff:
    - shard-iclb:         NOTRUN -> [SKIP][66] ([fdo#109280]) +1 similar issue
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-onoff.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence:
    - shard-kbl:          NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#533]) +1 similar issue
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-kbl1/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html
    - shard-apl:          NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#533])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-apl3/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - shard-kbl:          [PASS][69] -> [DMESG-WARN][70] ([i915#180]) +2 similar issues
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/shard-kbl7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-kbl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
    - shard-apl:          NOTRUN -> [FAIL][71] ([fdo#108145] / [i915#265]) +1 similar issue
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-apl7/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html

  * igt@kms_plane_alpha_blend@pipe-b-alpha-basic:
    - shard-kbl:          NOTRUN -> [FAIL][72] ([fdo#108145] / [i915#265]) +3 similar issues
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-kbl2/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html

  * igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping:
    - shard-apl:          NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#2733])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-apl1/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html
    - shard-kbl:          NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#2733])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-kbl4/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html
    - shard-glk:          NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#2733])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-glk6/igt@kms_plane_scaling@scaler-with-clipping-clamping@pipe-c-scaler-with-clipping-clamping.html

  * igt@kms_psr2_sf@cursor-plane-update-sf:
    - shard-tglb:         NOTRUN -> [SKIP][76] ([i915#2920])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-tglb8/igt@kms_psr2_sf@cursor-plane-update-sf.html

  * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4:
    - shard-kbl:          NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#658]) +3 similar issues
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-kbl3/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-4.html

  * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3:
    - shard-apl:          NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#658]) +4 similar issues
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-apl2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-3.html

  * igt@kms_psr@psr2_cursor_mmap_cpu:
    - shard-iclb:         [PASS][79] -> [SKIP][80] ([fdo#109441]) +3 similar issues
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-iclb1/igt@kms_psr@psr2_cursor_mmap_cpu.html

  * igt@kms_psr@psr2_sprite_blt:
    - shard-tglb:         NOTRUN -> [FAIL][81] ([i915#132] / [i915#3467])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-tglb3/igt@kms_psr@psr2_sprite_blt.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-270:
    - shard-glk:          NOTRUN -> [SKIP][82] ([fdo#109271]) +50 similar issues
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-glk5/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html

  * igt@kms_vblank@pipe-b-query-forked-busy-hang:
    - shard-apl:          [PASS][83] -> [SKIP][84] ([fdo#109271])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/shard-apl3/igt@kms_vblank@pipe-b-query-forked-busy-hang.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-apl8/igt@kms_vblank@pipe-b-query-forked-busy-hang.html
    - shard-glk:          [PASS][85] -> [SKIP][86] ([fdo#109271])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/shard-glk4/igt@kms_vblank@pipe-b-query-forked-busy-hang.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-glk4/igt@kms_vblank@pipe-b-query-forked-busy-hang.html

  * igt@kms_vblank@pipe-c-ts-continuation-suspend:
    - shard-apl:          [PASS][87] -> [DMESG-WARN][88] ([i915#180])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/shard-apl7/igt@kms_vblank@pipe-c-ts-continuation-suspend.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-apl1/igt@kms_vblank@pipe-c-ts-continuation-suspend.html

  * igt@kms_writeback@writeback-invalid-parameters:
    - shard-apl:          NOTRUN -> [SKIP][89] ([fdo#109271] / [i915#2437]) +1 similar issue
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-apl8/igt@kms_writeback@writeback-invalid-parameters.html

  * igt@kms_writeback@writeback-pixel-formats:
    - shard-kbl:          NOTRUN -> [SKIP][90] ([fdo#109271] / [i915#2437])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-kbl4/igt@kms_writeback@writeback-pixel-formats.html

  * igt@nouveau_crc@pipe-b-ctx-flip-skip-current-frame:
    - shard-apl:          NOTRUN -> [SKIP][91] ([fdo#109271]) +264 similar issues
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-apl1/igt@nouveau_crc@pipe-b-ctx-flip-skip-current-frame.html

  * igt@nouveau_crc@pipe-b-source-outp-complete:
    - shard-tglb:         NOTRUN -> [SKIP][92] ([i915#2530]) +1 similar issue
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-tglb2/igt@nouveau_crc@pipe-b-source-outp-complete.html

  * igt@prime_nv_pcopy@test2:
    - shard-kbl:          NOTRUN -> [SKIP][93] ([fdo#109271]) +147 similar issues
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-kbl4/igt@prime_nv_pcopy@test2.html

  * igt@prime_nv_test@i915_nv_sharing:
    - shard-iclb:         NOTRUN -> [SKIP][94] ([fdo#109291])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-iclb7/igt@prime_nv_test@i915_nv_sharing.html

  * igt@prime_nv_test@nv_write_i915_gtt_mmap_read:
    - shard-tglb:         NOTRUN -> [SKIP][95] ([fdo#109291]) +1 similar issue
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-tglb1/igt@prime_nv_test@nv_write_i915_gtt_mmap_read.html

  * igt@sysfs_clients@fair-7:
    - shard-apl:          NOTRUN -> [SKIP][96] ([fdo#109271] / [i915#2994]) +4 similar issues
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-apl7/igt@sysfs_clients@fair-7.html

  * igt@sysfs_clients@recycle:
    - shard-glk:          NOTRUN -> [SKIP][97] ([fdo#109271] / [i915#2994])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-glk9/igt@sysfs_clients@recycle.html

  * igt@sysfs_clients@sema-25:
    - shard-kbl:          NOTRUN -> [SKIP][98] ([fdo#109271] / [i915#2994]) +1 similar issue
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-kbl7/igt@sysfs_clients@sema-25.html

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@preservation-s3@vcs0:
    - shard-kbl:          [DMESG-WARN][99] ([i915#180]) -> [PASS][100] +1 similar issue
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/shard-kbl3/igt@gem_ctx_isolation@preservation-s3@vcs0.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-kbl2/igt@gem_ctx_isolation@preservation-s3@vcs0.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
    - shard-glk:          [FAIL][101] ([i915#2842]) -> [PASS][102]
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/shard-glk9/igt@gem_exec_fair@basic-none-solo@rcs0.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-glk3/igt@gem_exec_fair@basic-none-solo@rcs0.html

  * igt@gem_exec_fair@basic-pace@bcs0:
    - shard-iclb:         [FAIL][103] ([i915#2842]) -> [PASS][104]
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/shard-iclb2/igt@gem_exec_fair@basic-pace@bcs0.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-iclb8/igt@gem_exec_fair@basic-pace@bcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
    - shard-kbl:          [FAIL][105] ([i915#2842]) -> [PASS][106] +1 similar issue
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/shard-kbl7/igt@gem_exec_fair@basic-pace@vcs1.html
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-kbl7/igt@gem_exec_fair@basic-pace@vcs1.html

  * igt@gem_huc_copy@huc-copy:
    - shard-tglb:         [SKIP][107] ([i915#2190]) -> [PASS][108]
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/shard-tglb6/igt@gem_huc_copy@huc-copy.html
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-tglb2/igt@gem_huc_copy@huc-copy.html

  * igt@i915_pm_dc@dc9-dpms:
    - shard-apl:          [SKIP][109] ([fdo#109271]) -> [PASS][110]
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/shard-apl6/igt@i915_pm_dc@dc9-dpms.html
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-apl8/igt@i915_pm_dc@dc9-dpms.html
    - shard-iclb:         [SKIP][111] -> [PASS][112]
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/shard-iclb3/igt@i915_pm_dc@dc9-dpms.html
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-iclb7/igt@i915_pm_dc@dc9-dpms.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-180:
    - shard-glk:          [DMESG-WARN][113] ([i915#118]) -> [PASS][114]
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/shard-glk5/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-glk2/igt@kms_big_fb@x-tiled-32bpp-rotate-180.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2:
    - shard-glk:          [FAIL][115] ([i915#79]) -> [PASS][116]
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/shard-glk2/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@ac-hdmi-a1-hdmi-a2.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
    - shard-apl:          [DMESG-WARN][117] ([i915#180]) -> [PASS][118]
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/shard-apl8/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-apl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html

  * igt@kms_psr@psr2_cursor_render:
    - shard-iclb:         [SKIP][119] ([fdo#109441]) -> [PASS][120] +2 similar issues
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/shard-iclb7/igt@kms_psr@psr2_cursor_render.html
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-iclb2/igt@kms_psr@psr2_cursor_render.html

  * igt@perf@polling-parameterized:
    - shard-iclb:         [FAIL][121] ([i915#1542]) -> [PASS][122]
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/shard-iclb4/igt@perf@polling-parameterized.html
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-iclb5/igt@perf@polling-parameterized.html

  
#### Warnings ####

  * igt@i915_pm_rc6_residency@rc6-fence:
    - shard-iclb:         [WARN][123] ([i915#1804] / [i915#2684]) -> [WARN][124] ([i915#2684])
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/shard-iclb4/igt@i915_pm_rc6_residency@rc6-fence.html
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-iclb2/igt@i915_pm_rc6_residency@rc6-fence.html

  * igt@i915_pm_rc6_residency@rc6-idle:
    - shard-iclb:         [WARN][125] ([i915#2684]) -> [WARN][126] ([i915#1804] / [i915#2684])
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/shard-iclb5/igt@i915_pm_rc6_residency@rc6-idle.html
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-iclb6/igt@i915_pm_rc6_residency@rc6-idle.html

  * igt@i915_selftest@live@gt_pm:
    - shard-tglb:         [DMESG-FAIL][127] ([i915#1759] / [i915#2291]) -> [DMESG-FAIL][128] ([i915#1759])
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/shard-tglb3/igt@i915_selftest@live@gt_pm.html
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-tglb3/igt@i915_selftest@live@gt_pm.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2:
    - shard-iclb:         [SKIP][129] ([i915#658]) -> [SKIP][130] ([i915#2920]) +1 similar issue
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/shard-iclb1/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5:
    - shard-iclb:         [SKIP][131] ([i915#2920]) -> [SKIP][132] ([i915#658]) +2 similar issues
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-iclb5/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html

  * igt@runner@aborted:
    - shard-kbl:          ([FAIL][133], [FAIL][134], [FAIL][135], [FAIL][136], [FAIL][137], [FAIL][138], [FAIL][139]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363] / [i915#602]) -> ([FAIL][140], [FAIL][141], [FAIL][142], [FAIL][143], [FAIL][144], [FAIL][145], [FAIL][146], [FAIL][147]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#2426] / [i915#3002] / [i915#3363])
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/shard-kbl6/igt@runner@aborted.html
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/shard-kbl6/igt@runner@aborted.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/shard-kbl4/igt@runner@aborted.html
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/shard-kbl7/igt@runner@aborted.html
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/shard-kbl4/igt@runner@aborted.html
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/shard-kbl1/igt@runner@aborted.html
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10697/shard-kbl3/igt@runner@aborted.html
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-kbl3/igt@runner@aborted.html
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-kbl3/igt@runner@aborted.html
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-kbl4/igt@runner@aborted.html
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-kbl7/igt@runner@aborted.html
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-kbl7/igt@runner@aborted.html
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-kbl6/igt@runner@aborted.html
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-kbl6/igt@runner@aborted.html
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/shard-kbl4/igt@runner@aborted.html
    - shard-iclb:         ([FAIL][148], [FAIL][149]) ([i915#3002]) -> ([FAIL][150], [FAIL][151], [FAIL][152]) ([i915#2426] / [i915#3002] / [i915#3690])
   [1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6300/index.html

[-- Attachment #2: Type: text/html, Size: 34103 bytes --]

[igt-dev] [PATCH i-g-t 0/7] Prepare IGTs to allow only zero alignment

[Zbigniew Kempczyński]

In the future we're planning to allow passing only zero alignment so
this is preparation step to introduce check and disable or fix 
igts which uses this constraint.

v2: rename to gem_allows_obj_alignment() (Ashutosh)
    addressing review comments from Ashutosh

Cc: Petri Latvala <petri.latvala@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>

Zbigniew Kempczyński (7):
  lib/gem_submission: Add kernel exec object alignment capability
  lib/intel_batchbuffer: Detect and use kernel alignment capability
  tests/gem_exec_alignment: Add prerequisite alignment condition
  tests/gem_evict_alignment: Skip if kernel doesn't support obj
    alignment
  tests/i915_pm_rpm: Fix invalid alignment
  benchmarks/gem_exec_fault: Add timeout argument
  benchmarks/gem_exec_fault: Add softpin mode to support gens with ppgtt

 benchmarks/gem_exec_fault.c      | 67 +++++++++++++++++++++++++++-----
 lib/i915/gem_submission.c        | 32 +++++++++++++++
 lib/i915/gem_submission.h        |  1 +
 lib/intel_batchbuffer.c          |  9 ++++-
 lib/intel_batchbuffer.h          |  1 +
 tests/i915/gem_evict_alignment.c |  1 +
 tests/i915/gem_exec_alignment.c  |  1 +
 tests/i915/i915_pm_rpm.c         |  2 +-
 8 files changed, 101 insertions(+), 13 deletions(-)

-- 
2.26.0

[igt-dev] [PATCH i-g-t 1/7] lib/gem_submission: Add kernel exec object alignment capability

[Zbigniew Kempczyński]

v2: rename to gem_allows_obj_alignment() (Ashutosh)

With newer gens passing non-zero alignment will be forbidden.
Add check which detects kernel supports it or not.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 lib/i915/gem_submission.c | 32 ++++++++++++++++++++++++++++++++
 lib/i915/gem_submission.h |  1 +
 2 files changed, 33 insertions(+)

diff --git a/lib/i915/gem_submission.c b/lib/i915/gem_submission.c
index f1af4f97c..2627b802c 100644
--- a/lib/i915/gem_submission.c
+++ b/lib/i915/gem_submission.c
@@ -472,3 +472,35 @@ bool gem_has_relocations(int i915)
 
 	return has_relocs;
 }
+
+/**
+ * gem_allows_obj_alignment
+ * @fd: opened i915 drm file descriptor
+ *
+ * Check does i915 driver allows setting object alignment in exec object to
+ * handle in kernel and adjust object offset accordingly.
+ *
+ * Returns: true if kernel supports setting offset to be aligned, otherwise
+ * false.
+ */
+bool gem_allows_obj_alignment(int fd)
+{
+	struct drm_i915_gem_exec_object2 obj = {
+		.handle = gem_create(fd, 4096),
+	};
+	struct drm_i915_gem_execbuffer2 execbuf = {
+		.buffers_ptr = to_user_pointer(&obj),
+		.buffer_count = 1,
+	};
+	bool ret;
+	const uint32_t bbe = MI_BATCH_BUFFER_END;
+
+	gem_write(fd, obj.handle, 0, &bbe, sizeof(bbe));
+	gem_execbuf(fd, &execbuf);
+
+	obj.alignment = 0x2000;
+	ret = __gem_execbuf(fd, &execbuf) == 0;
+	gem_close(fd, obj.handle);
+
+	return ret;
+}
diff --git a/lib/i915/gem_submission.h b/lib/i915/gem_submission.h
index 9b3e2a4e5..38dd24a99 100644
--- a/lib/i915/gem_submission.h
+++ b/lib/i915/gem_submission.h
@@ -55,5 +55,6 @@ unsigned int gem_submission_measure(int i915, const intel_ctx_cfg_t *cfg,
 
 void gem_test_all_engines(int fd);
 bool gem_has_relocations(int fd);
+bool gem_allows_obj_alignment(int fd);
 
 #endif /* GEM_SUBMISSION_H */
-- 
2.26.0