[igt-dev] [PATCH i-g-t 0/7] Prepare IGTs to allow only zero alignment

[igt-dev] [PATCH i-g-t 0/7] Prepare IGTs to allow only zero alignment

[Zbigniew Kempczyński]

In the future we're planning to allow passing only zero alignment so
this is preparation step to introduce check and disable or fix 
igts which uses this constraint.

v2: rename to gem_allows_obj_alignment() (Ashutosh)
    addressing review comments from Ashutosh

Cc: Petri Latvala <petri.latvala@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>

Zbigniew Kempczyński (7):
  lib/gem_submission: Add kernel exec object alignment capability
  lib/intel_batchbuffer: Detect and use kernel alignment capability
  tests/gem_exec_alignment: Add prerequisite alignment condition
  tests/gem_evict_alignment: Skip if kernel doesn't support obj
    alignment
  tests/i915_pm_rpm: Fix invalid alignment
  benchmarks/gem_exec_fault: Add timeout argument
  benchmarks/gem_exec_fault: Add softpin mode to support gens with ppgtt

 benchmarks/gem_exec_fault.c      | 67 +++++++++++++++++++++++++++-----
 lib/i915/gem_submission.c        | 32 +++++++++++++++
 lib/i915/gem_submission.h        |  1 +
 lib/intel_batchbuffer.c          |  9 ++++-
 lib/intel_batchbuffer.h          |  1 +
 tests/i915/gem_evict_alignment.c |  1 +
 tests/i915/gem_exec_alignment.c  |  1 +
 tests/i915/i915_pm_rpm.c         |  2 +-
 8 files changed, 101 insertions(+), 13 deletions(-)

-- 
2.26.0

[igt-dev] [PATCH i-g-t 1/7] lib/gem_submission: Add kernel exec object alignment capability

[Zbigniew Kempczyński]

v2: rename to gem_allows_obj_alignment() (Ashutosh)

With newer gens passing non-zero alignment will be forbidden.
Add check which detects kernel supports it or not.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 lib/i915/gem_submission.c | 32 ++++++++++++++++++++++++++++++++
 lib/i915/gem_submission.h |  1 +
 2 files changed, 33 insertions(+)

diff --git a/lib/i915/gem_submission.c b/lib/i915/gem_submission.c
index f1af4f97c..2627b802c 100644
--- a/lib/i915/gem_submission.c
+++ b/lib/i915/gem_submission.c
@@ -472,3 +472,35 @@ bool gem_has_relocations(int i915)
 
 	return has_relocs;
 }
+
+/**
+ * gem_allows_obj_alignment
+ * @fd: opened i915 drm file descriptor
+ *
+ * Check does i915 driver allows setting object alignment in exec object to
+ * handle in kernel and adjust object offset accordingly.
+ *
+ * Returns: true if kernel supports setting offset to be aligned, otherwise
+ * false.
+ */
+bool gem_allows_obj_alignment(int fd)
+{
+	struct drm_i915_gem_exec_object2 obj = {
+		.handle = gem_create(fd, 4096),
+	};
+	struct drm_i915_gem_execbuffer2 execbuf = {
+		.buffers_ptr = to_user_pointer(&obj),
+		.buffer_count = 1,
+	};
+	bool ret;
+	const uint32_t bbe = MI_BATCH_BUFFER_END;
+
+	gem_write(fd, obj.handle, 0, &bbe, sizeof(bbe));
+	gem_execbuf(fd, &execbuf);
+
+	obj.alignment = 0x2000;
+	ret = __gem_execbuf(fd, &execbuf) == 0;
+	gem_close(fd, obj.handle);
+
+	return ret;
+}
diff --git a/lib/i915/gem_submission.h b/lib/i915/gem_submission.h
index 9b3e2a4e5..38dd24a99 100644
--- a/lib/i915/gem_submission.h
+++ b/lib/i915/gem_submission.h
@@ -55,5 +55,6 @@ unsigned int gem_submission_measure(int i915, const intel_ctx_cfg_t *cfg,
 
 void gem_test_all_engines(int fd);
 bool gem_has_relocations(int fd);
+bool gem_allows_obj_alignment(int fd);
 
 #endif /* GEM_SUBMISSION_H */
-- 
2.26.0

[igt-dev] [PATCH i-g-t 2/7] lib/intel_batchbuffer: Detect and use kernel alignment capability

[Zbigniew Kempczyński]

For gens where relocations are supported kernel can set object offset
everywhere it wants but it honours the alignment setting.

For gens where we got no relocations and setting alignment is not
allowed in exec object we want to ensure allocator will still use it
to properly align the offset.

Detect kernel caps in alignment setting and use it for reloc/no-reloc
paths accordingly.

v2: rename to gem_allows_obj_alignment() (Ashutosh)

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 lib/intel_batchbuffer.c | 9 +++++++--
 lib/intel_batchbuffer.h | 1 +
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 9c26fe207..6fc81400a 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -1335,6 +1335,7 @@ __intel_bb_create(int i915, uint32_t ctx, uint32_t size, bool do_relocs,
 
 	igt_assert(ibb);
 
+	ibb->allows_obj_alignment = gem_allows_obj_alignment(i915);
 	ibb->uses_full_ppgtt = gem_uses_full_ppgtt(i915);
 	ibb->devid = intel_get_drm_devid(i915);
 	ibb->gen = intel_gen(ibb->devid);
@@ -1783,6 +1784,7 @@ __add_to_cache(struct intel_bb *ibb, uint32_t handle)
 	igt_assert(object);
 
 	object->handle = handle;
+	object->alignment = 0;
 	found = tsearch((void *) object, &ibb->root, __compare_objects);
 
 	if (*found == object) {
@@ -1905,7 +1907,7 @@ intel_bb_add_object(struct intel_bb *ibb, uint32_t handle, uint64_t size,
 		   || ALIGN(offset, alignment) == offset);
 
 	object = __add_to_cache(ibb, handle);
-	object->alignment = alignment ?: 4096;
+	alignment = alignment ?: 4096;
 	__add_to_objects(ibb, object);
 
 	/*
@@ -1917,7 +1919,7 @@ intel_bb_add_object(struct intel_bb *ibb, uint32_t handle, uint64_t size,
 	if (INVALID_ADDR(object->offset)) {
 		if (INVALID_ADDR(offset)) {
 			offset = __intel_bb_get_offset(ibb, handle, size,
-						       object->alignment);
+						       alignment);
 		} else {
 			offset = offset & (ibb->gtt_size - 1);
 
@@ -1962,6 +1964,9 @@ intel_bb_add_object(struct intel_bb *ibb, uint32_t handle, uint64_t size,
 	if (ibb->uses_full_ppgtt && !ibb->enforce_relocs)
 		object->flags |= EXEC_OBJECT_PINNED;
 
+	if (ibb->allows_obj_alignment)
+		object->alignment = alignment;
+
 	return object;
 }
 
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index 58bddb1a1..e76063075 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -476,6 +476,7 @@ struct intel_bb {
 	uint64_t gtt_size;
 	bool supports_48b_address;
 	bool uses_full_ppgtt;
+	bool allows_obj_alignment;
 
 	struct igt_pxp pxp;
 	uint32_t ctx;
-- 
2.26.0

[igt-dev] [PATCH i-g-t 3/7] tests/gem_exec_alignment: Add prerequisite alignment condition

[Zbigniew Kempczyński]

Skip the test if the kernel doesn't support passing object alignment.

v2: rename to gem_allows_obj_alignment() (Ashutosh)

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 tests/i915/gem_exec_alignment.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tests/i915/gem_exec_alignment.c b/tests/i915/gem_exec_alignment.c
index 68b95c869..c88fc3272 100644
--- a/tests/i915/gem_exec_alignment.c
+++ b/tests/i915/gem_exec_alignment.c
@@ -530,6 +530,7 @@ igt_main
 	igt_fixture {
 		fd = drm_open_driver(DRIVER_INTEL);
 		igt_require_gem(fd);
+		igt_require(gem_allows_obj_alignment(fd));
 	}
 
 	igt_subtest("single") /* basic! */
-- 
2.26.0

[igt-dev] [PATCH i-g-t 4/7] tests/gem_evict_alignment: Skip if kernel doesn't support obj alignment

[Zbigniew Kempczyński]

v2: rename to gem_allows_obj_alignment()

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 tests/i915/gem_evict_alignment.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tests/i915/gem_evict_alignment.c b/tests/i915/gem_evict_alignment.c
index e5176b9ba..4a05f7cdf 100644
--- a/tests/i915/gem_evict_alignment.c
+++ b/tests/i915/gem_evict_alignment.c
@@ -198,6 +198,7 @@ igt_main
 		fd = drm_open_driver(DRIVER_INTEL);
 		igt_require_gem(fd);
 		gem_require_blitter(fd);
+		igt_require(gem_allows_obj_alignment(fd));
 		igt_fork_hang_detector(fd);
 	}
 
-- 
2.26.0

[igt-dev] [PATCH i-g-t 5/7] tests/i915_pm_rpm: Fix invalid alignment

[Zbigniew Kempczyński]

In theory kernel requires vma to be power of two aligned, but in
practice inserting vma requires alignment to be at least GTT min
alignment - which is page size atm. Change this alignment from 64->0
to allow test to run on gens where alignment must be zero in execbuf
as it will be page size aligned anyway.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 tests/i915/i915_pm_rpm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/i915/i915_pm_rpm.c b/tests/i915/i915_pm_rpm.c
index 732aea6eb..648b0cffb 100644
--- a/tests/i915/i915_pm_rpm.c
+++ b/tests/i915/i915_pm_rpm.c
@@ -1234,7 +1234,7 @@ static void submit_blt_cmd(uint32_t dst_handle, int dst_size,
 	relocs[0].write_domain = I915_GEM_DOMAIN_RENDER;
 
 	objs[0].handle = dst_handle;
-	objs[0].alignment = 64;
+	objs[0].alignment = 0;
 
 	objs[1].handle = batch_handle;
 	objs[1].relocation_count = !ahnd ? 1 : 0;
-- 
2.26.0

[igt-dev] [PATCH i-g-t 6/7] benchmarks/gem_exec_fault: Add timeout argument

[Zbigniew Kempczyński]

Add timeout argument and change elapsed time to inner loop to
be more precise in timeout processing.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 benchmarks/gem_exec_fault.c | 24 ++++++++++++++++++------
 1 file changed, 18 insertions(+), 6 deletions(-)

diff --git a/benchmarks/gem_exec_fault.c b/benchmarks/gem_exec_fault.c
index d53fab964..fe940b44c 100644
--- a/benchmarks/gem_exec_fault.c
+++ b/benchmarks/gem_exec_fault.c
@@ -49,6 +49,7 @@
 #include "ioctl_wrappers.h"
 
 #define ENGINE_FLAGS  (I915_EXEC_RING_MASK | I915_EXEC_BSD_MASK)
+#define DEFAULT_TIMEOUT 2.f
 
 static double elapsed(const struct timespec *start,
 		      const struct timespec *end)
@@ -64,7 +65,8 @@ static uint32_t batch(int fd, uint64_t size)
 	return handle;
 }
 
-static int loop(uint64_t size, unsigned ring, int reps, int ncpus, unsigned flags)
+static int loop(uint64_t size, unsigned ring, int reps, int ncpus,
+		unsigned flags, float timeout)
 {
 	struct drm_i915_gem_execbuffer2 execbuf;
 	struct drm_i915_gem_exec_object2 obj;
@@ -128,10 +130,14 @@ static int loop(uint64_t size, unsigned ring, int reps, int ncpus, unsigned flag
 					/* fault out */
 					obj.alignment = 1ull << 63;
 					__gem_execbuf(fd, &execbuf);
-				}
 
-				clock_gettime(CLOCK_MONOTONIC, &end);
-			} while (elapsed(&start, &end) < 2.);
+					clock_gettime(CLOCK_MONOTONIC, &end);
+					if (elapsed(&start, &end) >= timeout) {
+						timeout = -1.0;
+						break;
+					}
+				}
+			} while (timeout > 0);
 
 			gem_sync(fd, obj.handle);
 			clock_gettime(CLOCK_MONOTONIC, &end);
@@ -156,8 +162,9 @@ int main(int argc, char **argv)
 	int reps = 1;
 	int ncpus = 1;
 	int c;
+	float timeout = DEFAULT_TIMEOUT;
 
-	while ((c = getopt (argc, argv, "e:r:s:f")) != -1) {
+	while ((c = getopt (argc, argv, "e:r:s:ft:")) != -1) {
 		switch (c) {
 		case 'e':
 			if (strcmp(optarg, "rcs") == 0)
@@ -190,10 +197,15 @@ int main(int argc, char **argv)
 				size = 4096;
 			break;
 
+		case 't':
+			timeout = atof(optarg);
+			igt_assert_f(timeout > 0, "Timeout must be > 0\n");
+			break;
+
 		default:
 			break;
 		}
 	}
 
-	return loop(size, ring, reps, ncpus, flags);
+	return loop(size, ring, reps, ncpus, flags, timeout);
 }
-- 
2.26.0

[igt-dev] [PATCH i-g-t 7/7] benchmarks/gem_exec_fault: Add softpin mode to support gens with ppgtt

[Zbigniew Kempczyński]

Alignment trick doesn't work properly for ppgtt gens - kernel is able
to keep previous offset and doesn't call unbind/bind. With softpin
on ppgtt we're able to enforce rebind and benchmark should behave
correctly on such gens.

To avoid inaccurate results kernel CONFIG_PROVE_LOCKING should be set
to N, otherwise kernel can call unbind/bind for same offset more than
one (backoff is not visible from userspace).

v2: rename to gem_allows_obj_alignment()

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 benchmarks/gem_exec_fault.c | 43 +++++++++++++++++++++++++++++++++----
 1 file changed, 39 insertions(+), 4 deletions(-)

diff --git a/benchmarks/gem_exec_fault.c b/benchmarks/gem_exec_fault.c
index fe940b44c..e04840717 100644
--- a/benchmarks/gem_exec_fault.c
+++ b/benchmarks/gem_exec_fault.c
@@ -43,7 +43,9 @@
 #include "drm.h"
 #include "drmtest.h"
 #include "i915/gem_create.h"
+#include "i915/gem_submission.h"
 #include "igt_stats.h"
+#include "intel_allocator.h"
 #include "intel_io.h"
 #include "intel_reg.h"
 #include "ioctl_wrappers.h"
@@ -74,11 +76,28 @@ static int loop(uint64_t size, unsigned ring, int reps, int ncpus,
 	unsigned nengine;
 	double *shared;
 	int fd;
+	bool has_ppgtt;
 
 	shared = mmap(0, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0);
 
 	fd = drm_open_driver(DRIVER_INTEL);
 
+	/*
+	 * For older gens .alignment = 1ull << 63 lead do bind/unbind,
+	 * what doesn't work for newer gens with ppgtt.
+	 * For ppgtt case we use reloc allocator which would just assigns
+	 * new offset for each batch. This way we enforce bind/unbind vma
+	 * for each execbuf.
+	 */
+	has_ppgtt = gem_uses_full_ppgtt(fd);
+	if (has_ppgtt) {
+		igt_info("Using softpin mode\n");
+		intel_allocator_multiprocess_start();
+	} else {
+		igt_assert(gem_allows_obj_alignment(fd));
+		igt_info("Using alignment mode\n");
+	}
+
 	memset(&obj, 0, sizeof(obj));
 	obj.handle = batch(fd, 4096);
 
@@ -92,6 +111,7 @@ static int loop(uint64_t size, unsigned ring, int reps, int ncpus,
 		if (__gem_execbuf(fd, &execbuf))
 			return 77;
 	}
+
 	/* let the small object leak; ideally blocking the low address */
 
 	nengine = 0;
@@ -106,7 +126,7 @@ static int loop(uint64_t size, unsigned ring, int reps, int ncpus,
 		engines[nengine++] = ring;
 
 	if (size > 1ul << 31)
-		obj.flags |= 1 << 3;
+		obj.flags |= EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
 
 	while (reps--) {
 		memset(shared, 0, 4096);
@@ -114,10 +134,14 @@ static int loop(uint64_t size, unsigned ring, int reps, int ncpus,
 		igt_fork(child, ncpus) {
 			struct timespec start, end;
 			unsigned count = 0;
+			uint64_t ahnd = 0;
 
 			obj.handle = batch(fd, size);
 			obj.offset = -1;
 
+			if (has_ppgtt)
+				ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+
 			clock_gettime(CLOCK_MONOTONIC, &start);
 			do {
 				for (int inner = 0; inner < 1024; inner++) {
@@ -127,9 +151,14 @@ static int loop(uint64_t size, unsigned ring, int reps, int ncpus,
 					obj.alignment = 0;
 					gem_execbuf(fd, &execbuf);
 
-					/* fault out */
-					obj.alignment = 1ull << 63;
-					__gem_execbuf(fd, &execbuf);
+					if (ahnd) {
+						obj.offset = get_offset(ahnd, obj.handle, size, 0);
+						obj.flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+					} else {
+						/* fault out */
+						obj.alignment = 1ull << 63;
+						__gem_execbuf(fd, &execbuf);
+					}
 
 					clock_gettime(CLOCK_MONOTONIC, &end);
 					if (elapsed(&start, &end) >= timeout) {
@@ -144,6 +173,8 @@ static int loop(uint64_t size, unsigned ring, int reps, int ncpus,
 			shared[child] = 1e6*elapsed(&start, &end) / count / 2;
 
 			gem_close(fd, obj.handle);
+			if (ahnd)
+				intel_allocator_close(ahnd);
 		}
 		igt_waitchildren();
 
@@ -151,6 +182,10 @@ static int loop(uint64_t size, unsigned ring, int reps, int ncpus,
 			shared[ncpus] += shared[child];
 		printf("%7.3f\n", shared[ncpus] / ncpus);
 	}
+
+	if (has_ppgtt)
+		intel_allocator_multiprocess_stop();
+
 	return 0;
 }
 
-- 
2.26.0

[igt-dev] ✓ Fi.CI.BAT: success for Prepare IGTs to allow only zero alignment (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 6934 bytes --]

== Series Details ==

Series: Prepare IGTs to allow only zero alignment (rev2)
URL   : https://patchwork.freedesktop.org/series/95597/
State : success

== Summary ==

CI Bug Log - changes from IGT_6245 -> IGTPW_6320
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/index.html

Known issues
------------

  Here are the changes found in IGTPW_6320 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_basic@semaphore:
    - fi-icl-y:           NOTRUN -> [SKIP][1] ([fdo#109315]) +17 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/fi-icl-y/igt@amdgpu/amd_basic@semaphore.html

  * igt@gem_huc_copy@huc-copy:
    - fi-icl-y:           NOTRUN -> [SKIP][2] ([i915#2190])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/fi-icl-y/igt@gem_huc_copy@huc-copy.html

  * igt@i915_selftest@live@late_gt_pm:
    - fi-bsw-nick:        [PASS][3] -> [DMESG-FAIL][4] ([i915#2927] / [i915#3428])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6245/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/fi-bsw-nick/igt@i915_selftest@live@late_gt_pm.html

  * igt@kms_chamelium@dp-crc-fast:
    - fi-icl-y:           NOTRUN -> [SKIP][5] ([fdo#109284] / [fdo#111827]) +8 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/fi-icl-y/igt@kms_chamelium@dp-crc-fast.html

  * igt@kms_chamelium@hdmi-edid-read:
    - fi-bdw-samus:       NOTRUN -> [SKIP][6] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/fi-bdw-samus/igt@kms_chamelium@hdmi-edid-read.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - fi-icl-y:           NOTRUN -> [SKIP][7] ([fdo#109278]) +2 similar issues
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/fi-icl-y/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_force_connector_basic@force-load-detect:
    - fi-icl-y:           NOTRUN -> [SKIP][8] ([fdo#109285])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/fi-icl-y/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
    - fi-bdw-samus:       NOTRUN -> [SKIP][9] ([fdo#109271]) +29 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/fi-bdw-samus/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_psr@primary_mmap_gtt:
    - fi-icl-y:           NOTRUN -> [SKIP][10] ([fdo#110189]) +3 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/fi-icl-y/igt@kms_psr@primary_mmap_gtt.html

  * igt@prime_vgem@basic-userptr:
    - fi-icl-y:           NOTRUN -> [SKIP][11] ([i915#3301])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/fi-icl-y/igt@prime_vgem@basic-userptr.html

  * igt@runner@aborted:
    - fi-bsw-nick:        NOTRUN -> [FAIL][12] ([fdo#109271] / [i915#1436] / [i915#3428])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/fi-bsw-nick/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@hangcheck:
    - {fi-jsl-1}:         [INCOMPLETE][13] ([i915#3057]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6245/fi-jsl-1/igt@i915_selftest@live@hangcheck.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/fi-jsl-1/igt@i915_selftest@live@hangcheck.html
    - {fi-hsw-gt1}:       [DMESG-WARN][15] ([i915#3303]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6245/fi-hsw-gt1/igt@i915_selftest@live@hangcheck.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/fi-hsw-gt1/igt@i915_selftest@live@hangcheck.html

  * igt@kms_flip@basic-flip-vs-modeset@c-dp1:
    - fi-cfl-8109u:       [FAIL][17] ([i915#4165]) -> [PASS][18] +1 similar issue
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6245/fi-cfl-8109u/igt@kms_flip@basic-flip-vs-modeset@c-dp1.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/fi-cfl-8109u/igt@kms_flip@basic-flip-vs-modeset@c-dp1.html

  * igt@kms_flip@basic-plain-flip@c-dp2:
    - fi-cfl-8109u:       [DMESG-WARN][19] ([i915#295]) -> [PASS][20] +2 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6245/fi-cfl-8109u/igt@kms_flip@basic-plain-flip@c-dp2.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/fi-cfl-8109u/igt@kms_flip@basic-plain-flip@c-dp2.html

  
#### Warnings ####

  * igt@kms_flip@basic-plain-flip@c-dp1:
    - fi-cfl-8109u:       [DMESG-WARN][21] ([i915#295]) -> [FAIL][22] ([i915#4165])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6245/fi-cfl-8109u/igt@kms_flip@basic-plain-flip@c-dp1.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/fi-cfl-8109u/igt@kms_flip@basic-plain-flip@c-dp1.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927
  [i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295
  [i915#3057]: https://gitlab.freedesktop.org/drm/intel/issues/3057
  [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428
  [i915#4165]: https://gitlab.freedesktop.org/drm/intel/issues/4165


Participating hosts (39 -> 36)
------------------------------

  Additional (2): fi-icl-y fi-bdw-samus 
  Missing    (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-dg1-1 fi-kbl-r 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_6245 -> IGTPW_6320

  CI-20190529: 20190529
  CI_DRM_10732: 3fdfa1de4774903b9cb4fb308102b5a2d762d829 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_6320: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/index.html
  IGT_6245: 477076d55a3cc53b8bfabae5af59114c8cd74827 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/index.html

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[igt-dev] ✓ Fi.CI.IGT: success for Prepare IGTs to allow only zero alignment (rev2)

[Patchwork]

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== Series Details ==

Series: Prepare IGTs to allow only zero alignment (rev2)
URL   : https://patchwork.freedesktop.org/series/95597/
State : success

== Summary ==

CI Bug Log - changes from IGT_6245_full -> IGTPW_6320_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/index.html

Known issues
------------

  Here are the changes found in IGTPW_6320_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@feature_discovery@chamelium:
    - shard-tglb:         NOTRUN -> [SKIP][1] ([fdo#111827])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-tglb6/igt@feature_discovery@chamelium.html
    - shard-iclb:         NOTRUN -> [SKIP][2] ([fdo#111827])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-iclb1/igt@feature_discovery@chamelium.html

  * igt@feature_discovery@display-3x:
    - shard-tglb:         NOTRUN -> [SKIP][3] ([i915#1839])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-tglb3/igt@feature_discovery@display-3x.html

  * igt@gem_create@create-massive:
    - shard-snb:          NOTRUN -> [DMESG-WARN][4] ([i915#3002])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-snb7/igt@gem_create@create-massive.html

  * igt@gem_ctx_isolation@preservation-s3@rcs0:
    - shard-apl:          NOTRUN -> [DMESG-WARN][5] ([i915#180]) +1 similar issue
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-apl6/igt@gem_ctx_isolation@preservation-s3@rcs0.html

  * igt@gem_ctx_persistence@engines-queued:
    - shard-snb:          NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1099]) +3 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-snb7/igt@gem_ctx_persistence@engines-queued.html

  * igt@gem_eio@unwedge-stress:
    - shard-snb:          NOTRUN -> [FAIL][7] ([i915#3354])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-snb6/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-kbl:          [PASS][8] -> [FAIL][9] ([i915#2846])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6245/shard-kbl2/igt@gem_exec_fair@basic-deadline.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-kbl6/igt@gem_exec_fair@basic-deadline.html
    - shard-glk:          [PASS][10] -> [FAIL][11] ([i915#2846])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6245/shard-glk2/igt@gem_exec_fair@basic-deadline.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-glk5/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-none-rrul@rcs0:
    - shard-kbl:          [PASS][12] -> [FAIL][13] ([i915#2842])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6245/shard-kbl2/igt@gem_exec_fair@basic-none-rrul@rcs0.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-kbl2/igt@gem_exec_fair@basic-none-rrul@rcs0.html

  * igt@gem_exec_fair@basic-pace@bcs0:
    - shard-tglb:         NOTRUN -> [FAIL][14] ([i915#2842]) +2 similar issues
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-tglb3/igt@gem_exec_fair@basic-pace@bcs0.html

  * igt@gem_exec_fair@basic-pace@vcs0:
    - shard-iclb:         NOTRUN -> [FAIL][15] ([i915#2842]) +2 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-iclb3/igt@gem_exec_fair@basic-pace@vcs0.html

  * igt@gem_exec_fair@basic-pace@vcs1:
    - shard-kbl:          NOTRUN -> [FAIL][16] ([i915#2842]) +1 similar issue
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-kbl7/igt@gem_exec_fair@basic-pace@vcs1.html

  * igt@gem_exec_params@secure-non-master:
    - shard-tglb:         NOTRUN -> [SKIP][17] ([fdo#112283])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-tglb5/igt@gem_exec_params@secure-non-master.html

  * igt@gem_pread@exhaustion:
    - shard-glk:          NOTRUN -> [WARN][18] ([i915#2658])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-glk4/igt@gem_pread@exhaustion.html

  * igt@gem_pxp@display-protected-crc:
    - shard-tglb:         NOTRUN -> [SKIP][19] ([i915#4270])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-tglb2/igt@gem_pxp@display-protected-crc.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-kbl:          NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#3323])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-kbl3/igt@gem_userptr_blits@dmabuf-sync.html
    - shard-iclb:         NOTRUN -> [SKIP][21] ([i915#3323])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-iclb6/igt@gem_userptr_blits@dmabuf-sync.html
    - shard-glk:          NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#3323])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-glk1/igt@gem_userptr_blits@dmabuf-sync.html
    - shard-tglb:         NOTRUN -> [SKIP][23] ([i915#3323])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-tglb5/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@unsync-unmap:
    - shard-tglb:         NOTRUN -> [SKIP][24] ([i915#3297])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-tglb2/igt@gem_userptr_blits@unsync-unmap.html

  * igt@gem_workarounds@suspend-resume-fd:
    - shard-apl:          [PASS][25] -> [DMESG-WARN][26] ([i915#180])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6245/shard-apl8/igt@gem_workarounds@suspend-resume-fd.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-apl6/igt@gem_workarounds@suspend-resume-fd.html

  * igt@gen9_exec_parse@bb-secure:
    - shard-tglb:         NOTRUN -> [SKIP][27] ([i915#2856])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-tglb2/igt@gen9_exec_parse@bb-secure.html

  * igt@i915_pm_backlight@fade_with_suspend:
    - shard-tglb:         [PASS][28] -> [INCOMPLETE][29] ([i915#456])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6245/shard-tglb8/igt@i915_pm_backlight@fade_with_suspend.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-tglb7/igt@i915_pm_backlight@fade_with_suspend.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-iclb:         [PASS][30] -> [FAIL][31] ([i915#454])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6245/shard-iclb5/igt@i915_pm_dc@dc6-psr.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-iclb6/igt@i915_pm_dc@dc6-psr.html

  * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
    - shard-kbl:          NOTRUN -> [SKIP][32] ([fdo#109271] / [i915#1937])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-kbl1/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html
    - shard-apl:          NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#1937])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-apl2/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html

  * igt@i915_pm_rpm@modeset-non-lpsp:
    - shard-tglb:         NOTRUN -> [SKIP][34] ([fdo#111644] / [i915#1397] / [i915#2411])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-tglb5/igt@i915_pm_rpm@modeset-non-lpsp.html

  * igt@i915_pm_sseu@full-enable:
    - shard-tglb:         NOTRUN -> [SKIP][35] ([fdo#109288])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-tglb3/igt@i915_pm_sseu@full-enable.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
    - shard-kbl:          [PASS][36] -> [DMESG-WARN][37] ([i915#180])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6245/shard-kbl4/igt@i915_suspend@fence-restore-tiled2untiled.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-kbl1/igt@i915_suspend@fence-restore-tiled2untiled.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
    - shard-tglb:         NOTRUN -> [SKIP][38] ([i915#1769])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-tglb2/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html

  * igt@kms_big_fb@linear-32bpp-rotate-0:
    - shard-glk:          [PASS][39] -> [DMESG-WARN][40] ([i915#118])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6245/shard-glk9/igt@kms_big_fb@linear-32bpp-rotate-0.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-glk6/igt@kms_big_fb@linear-32bpp-rotate-0.html

  * igt@kms_big_fb@x-tiled-16bpp-rotate-90:
    - shard-tglb:         NOTRUN -> [SKIP][41] ([fdo#111614])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-tglb6/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-apl:          NOTRUN -> [SKIP][42] ([fdo#109271] / [i915#3777])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-apl2/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0:
    - shard-iclb:         NOTRUN -> [SKIP][43] ([fdo#110723])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-iclb6/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html
    - shard-tglb:         NOTRUN -> [SKIP][44] ([fdo#111615]) +2 similar issues
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-tglb5/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html

  * igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][45] ([i915#3689]) +3 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-tglb3/igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_ccs.html

  * igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
    - shard-apl:          NOTRUN -> [SKIP][46] ([fdo#109271] / [i915#3886]) +10 similar issues
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-apl1/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
    - shard-tglb:         NOTRUN -> [SKIP][47] ([i915#3689] / [i915#3886]) +1 similar issue
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-tglb2/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
    - shard-iclb:         NOTRUN -> [SKIP][48] ([fdo#109278] / [i915#3886]) +1 similar issue
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-iclb6/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
    - shard-kbl:          NOTRUN -> [SKIP][49] ([fdo#109271] / [i915#3886]) +4 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-kbl2/igt@kms_ccs@pipe-c-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html

  * igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
    - shard-glk:          NOTRUN -> [SKIP][50] ([fdo#109271] / [i915#3886]) +5 similar issues
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-glk9/igt@kms_ccs@pipe-c-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_chamelium@dp-hpd-storm:
    - shard-iclb:         NOTRUN -> [SKIP][51] ([fdo#109284] / [fdo#111827]) +2 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-iclb8/igt@kms_chamelium@dp-hpd-storm.html

  * igt@kms_chamelium@hdmi-mode-timings:
    - shard-snb:          NOTRUN -> [SKIP][52] ([fdo#109271] / [fdo#111827]) +20 similar issues
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-snb6/igt@kms_chamelium@hdmi-mode-timings.html

  * igt@kms_chamelium@vga-hpd-after-suspend:
    - shard-tglb:         NOTRUN -> [SKIP][53] ([fdo#109284] / [fdo#111827]) +9 similar issues
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-tglb2/igt@kms_chamelium@vga-hpd-after-suspend.html

  * igt@kms_color_chamelium@pipe-a-ctm-blue-to-red:
    - shard-kbl:          NOTRUN -> [SKIP][54] ([fdo#109271] / [fdo#111827]) +11 similar issues
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-kbl1/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html

  * igt@kms_color_chamelium@pipe-b-ctm-0-5:
    - shard-glk:          NOTRUN -> [SKIP][55] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-glk6/igt@kms_color_chamelium@pipe-b-ctm-0-5.html

  * igt@kms_color_chamelium@pipe-c-ctm-0-25:
    - shard-apl:          NOTRUN -> [SKIP][56] ([fdo#109271] / [fdo#111827]) +18 similar issues
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-apl8/igt@kms_color_chamelium@pipe-c-ctm-0-25.html

  * igt@kms_color_chamelium@pipe-d-ctm-blue-to-red:
    - shard-iclb:         NOTRUN -> [SKIP][57] ([fdo#109278] / [fdo#109284] / [fdo#111827])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-iclb8/igt@kms_color_chamelium@pipe-d-ctm-blue-to-red.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-tglb:         NOTRUN -> [SKIP][58] ([fdo#111828]) +1 similar issue
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-tglb1/igt@kms_content_protection@atomic-dpms.html
    - shard-kbl:          NOTRUN -> [TIMEOUT][59] ([i915#1319])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-kbl6/igt@kms_content_protection@atomic-dpms.html
    - shard-iclb:         NOTRUN -> [SKIP][60] ([fdo#109300] / [fdo#111066])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-iclb8/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@lic:
    - shard-apl:          NOTRUN -> [TIMEOUT][61] ([i915#1319]) +1 similar issue
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-apl7/igt@kms_content_protection@lic.html

  * igt@kms_cursor_crc@pipe-a-cursor-32x10-offscreen:
    - shard-tglb:         NOTRUN -> [SKIP][62] ([i915#3359]) +3 similar issues
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-tglb2/igt@kms_cursor_crc@pipe-a-cursor-32x10-offscreen.html

  * igt@kms_cursor_crc@pipe-a-cursor-32x32-onscreen:
    - shard-iclb:         NOTRUN -> [SKIP][63] ([fdo#109278]) +7 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-iclb7/igt@kms_cursor_crc@pipe-a-cursor-32x32-onscreen.html
    - shard-tglb:         NOTRUN -> [SKIP][64] ([i915#3319]) +1 similar issue
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-tglb5/igt@kms_cursor_crc@pipe-a-cursor-32x32-onscreen.html

  * igt@kms_cursor_crc@pipe-a-cursor-512x170-random:
    - shard-tglb:         NOTRUN -> [SKIP][65] ([fdo#109279] / [i915#3359]) +2 similar issues
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-tglb7/igt@kms_cursor_crc@pipe-a-cursor-512x170-random.html
    - shard-iclb:         NOTRUN -> [SKIP][66] ([fdo#109278] / [fdo#109279]) +1 similar issue
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-iclb5/igt@kms_cursor_crc@pipe-a-cursor-512x170-random.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
    - shard-iclb:         NOTRUN -> [SKIP][67] ([fdo#109274] / [fdo#109278]) +1 similar issue
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-iclb8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html

  * igt@kms_cursor_legacy@pipe-d-single-bo:
    - shard-glk:          NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#533])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-glk9/igt@kms_cursor_legacy@pipe-d-single-bo.html
    - shard-kbl:          NOTRUN -> [SKIP][69] ([fdo#109271] / [i915#533])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-kbl1/igt@kms_cursor_legacy@pipe-d-single-bo.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-tglb:         NOTRUN -> [SKIP][70] ([i915#4103])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-tglb5/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_dsc@basic-dsc-enable:
    - shard-iclb:         NOTRUN -> [SKIP][71] ([i915#3840])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-iclb5/igt@kms_dsc@basic-dsc-enable.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-kbl:          [PASS][72] -> [INCOMPLETE][73] ([i915#180] / [i915#636])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6245/shard-kbl2/igt@kms_fbcon_fbt@fbc-suspend.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-tglb:         [PASS][74] -> [INCOMPLETE][75] ([i915#2411] / [i915#456])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6245/shard-tglb1/igt@kms_fbcon_fbt@psr-suspend.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-tglb7/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_flip@2x-flip-vs-fences-interruptible:
    - shard-iclb:         NOTRUN -> [SKIP][76] ([fdo#109274])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-iclb5/igt@kms_flip@2x-flip-vs-fences-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1:
    - shard-apl:          NOTRUN -> [DMESG-WARN][77] ([i915#180] / [i915#1982])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
    - shard-kbl:          NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#2672])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-kbl3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile:
    - shard-snb:          NOTRUN -> [SKIP][79] ([fdo#109271]) +342 similar issues
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-snb2/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile:
    - shard-iclb:         [PASS][80] -> [SKIP][81] ([i915#3701])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6245/shard-iclb3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt:
    - shard-tglb:         NOTRUN -> [SKIP][82] ([fdo#111825]) +21 similar issues
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-tglb3/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu:
    - shard-kbl:          NOTRUN -> [SKIP][83] ([fdo#109271]) +97 similar issues
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-kbl3/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-blt:
    - shard-iclb:         NOTRUN -> [SKIP][84] ([fdo#109280]) +5 similar issues
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-iclb8/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_hdr@static-toggle-dpms:
    - shard-tglb:         NOTRUN -> [SKIP][85] ([i915#1187])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-tglb2/igt@kms_hdr@static-toggle-dpms.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d:
    - shard-apl:          NOTRUN -> [SKIP][86] ([fdo#109271] / [i915#533]) +1 similar issue
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-apl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
    - shard-apl:          NOTRUN -> [FAIL][87] ([i915#265])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-apl3/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html

  * igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
    - shard-kbl:          NOTRUN -> [FAIL][88] ([fdo#108145] / [i915#265])
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-kbl2/igt@kms_plane_alpha_blend@pipe-b-alpha-7efc.html

  * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
    - shard-apl:          NOTRUN -> [FAIL][89] ([fdo#108145] / [i915#265])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-apl8/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html

  * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2:
    - shard-tglb:         NOTRUN -> [SKIP][90] ([i915#2920]) +1 similar issue
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-tglb5/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1:
    - shard-apl:          NOTRUN -> [SKIP][91] ([fdo#109271] / [i915#658])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-apl7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2:
    - shard-kbl:          NOTRUN -> [SKIP][92] ([fdo#109271] / [i915#658]) +1 similar issue
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-kbl3/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html
    - shard-glk:          NOTRUN -> [SKIP][93] ([fdo#109271] / [i915#658])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-glk3/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-2.html

  * igt@kms_psr@psr2_basic:
    - shard-tglb:         NOTRUN -> [FAIL][94] ([i915#132] / [i915#3467]) +1 similar issue
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-tglb8/igt@kms_psr@psr2_basic.html

  * igt@kms_psr@psr2_cursor_render:
    - shard-iclb:         [PASS][95] -> [SKIP][96] ([fdo#109441]) +1 similar issue
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6245/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-iclb5/igt@kms_psr@psr2_cursor_render.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-apl:          [PASS][97] -> [DMESG-WARN][98] ([i915#180] / [i915#295])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6245/shard-apl8/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-apl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html

  * igt@kms_vblank@pipe-d-ts-continuation-modeset-hang:
    - shard-glk:          NOTRUN -> [SKIP][99] ([fdo#109271]) +77 similar issues
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-glk5/igt@kms_vblank@pipe-d-ts-continuation-modeset-hang.html

  * igt@nouveau_crc@pipe-b-source-rg:
    - shard-iclb:         NOTRUN -> [SKIP][100] ([i915#2530])
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-iclb2/igt@nouveau_crc@pipe-b-source-rg.html
    - shard-tglb:         NOTRUN -> [SKIP][101] ([i915#2530]) +1 similar issue
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-tglb8/igt@nouveau_crc@pipe-b-source-rg.html

  * igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name:
    - shard-apl:          NOTRUN -> [SKIP][102] ([fdo#109271]) +189 similar issues
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-apl7/igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name.html
    - shard-tglb:         NOTRUN -> [SKIP][103] ([fdo#109291]) +3 similar issues
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-tglb1/igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name.html
    - shard-iclb:         NOTRUN -> [SKIP][104] ([fdo#109291]) +1 similar issue
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-iclb2/igt@prime_nv_api@i915_nv_reimport_twice_check_flink_name.html

  * igt@sysfs_clients@fair-3:
    - shard-tglb:         NOTRUN -> [SKIP][105] ([i915#2994]) +1 similar issue
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-tglb8/igt@sysfs_clients@fair-3.html

  * igt@sysfs_clients@fair-7:
    - shard-apl:          NOTRUN -> [SKIP][106] ([fdo#109271] / [i915#2994]) +5 similar issues
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-apl6/igt@sysfs_clients@fair-7.html

  * igt@sysfs_clients@sema-50:
    - shard-glk:          NOTRUN -> [SKIP][107] ([fdo#109271] / [i915#2994]) +2 similar issues
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-glk1/igt@sysfs_clients@sema-50.html

  * igt@sysfs_clients@split-10:
    - shard-iclb:         NOTRUN -> [SKIP][108] ([i915#2994])
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-iclb3/igt@sysfs_clients@split-10.html
    - shard-kbl:          NOTRUN -> [SKIP][109] ([fdo#109271] / [i915#2994])
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-kbl3/igt@sysfs_clients@split-10.html

  
#### Possible fixes ####

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-glk:          [FAIL][110] ([i915#2842]) -> [PASS][111] +1 similar issue
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6245/shard-glk8/igt@gem_exec_fair@basic-throttle@rcs0.html
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-glk1/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@i915_pm_dc@dc9-dpms:
    - shard-iclb:         [FAIL][112] ([i915#4275]) -> [PASS][113]
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6245/shard-iclb2/igt@i915_pm_dc@dc9-dpms.html
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-iclb5/igt@i915_pm_dc@dc9-dpms.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a1:
    - shard-glk:          [FAIL][114] ([i915#79]) -> [PASS][115]
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6245/shard-glk4/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a1.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-glk9/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-hdmi-a1.html

  * igt@kms_flip@flip-vs-suspend@c-dp1:
    - shard-kbl:          [DMESG-WARN][116] ([i915#180]) -> [PASS][117] +4 similar issues
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6245/shard-kbl1/igt@kms_flip@flip-vs-suspend@c-dp1.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-kbl7/igt@kms_flip@flip-vs-suspend@c-dp1.html

  * igt@kms_psr@psr2_suspend:
    - shard-iclb:         [SKIP][118] ([fdo#109441]) -> [PASS][119] +1 similar issue
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6245/shard-iclb5/igt@kms_psr@psr2_suspend.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-iclb2/igt@kms_psr@psr2_suspend.html

  
#### Warnings ####

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-iclb:         [FAIL][120] ([i915#2849]) -> [FAIL][121] ([i915#2842])
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6245/shard-iclb8/igt@gem_exec_fair@basic-throttle@rcs0.html
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-iclb6/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1:
    - shard-iclb:         [SKIP][122] ([i915#658]) -> [SKIP][123] ([i915#2920])
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6245/shard-iclb5/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4:
    - shard-iclb:         [SKIP][124] ([i915#2920]) -> [SKIP][125] ([i915#658]) +2 similar issues
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6245/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-iclb3/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-4.html

  * igt@runner@aborted:
    - shard-kbl:          ([FAIL][126], [FAIL][127], [FAIL][128], [FAIL][129]) ([i915#1436] / [i915#180] / [i915#3002] / [i915#3363]) -> ([FAIL][130], [FAIL][131], [FAIL][132], [FAIL][133]) ([i915#180] / [i915#3002] / [i915#3363] / [i915#92])
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6245/shard-kbl1/igt@runner@aborted.html
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6245/shard-kbl1/igt@runner@aborted.html
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6245/shard-kbl4/igt@runner@aborted.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6245/shard-kbl4/igt@runner@aborted.html
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-kbl1/igt@runner@aborted.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-kbl1/igt@runner@aborted.html
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-kbl6/igt@runner@aborted.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-kbl7/igt@runner@aborted.html
    - shard-apl:          [FAIL][134] ([i915#3002] / [i915#3363]) -> ([FAIL][135], [FAIL][136], [FAIL][137], [FAIL][138], [FAIL][139]) ([fdo#109271] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363])
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6245/shard-apl1/igt@runner@aborted.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-apl6/igt@runner@aborted.html
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-apl6/igt@runner@aborted.html
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-apl6/igt@runner@aborted.html
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-apl3/igt@runner@aborted.html
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/shard-apl1/igt@runner@aborted.html
    - shard-glk:          ([FAIL][140], [FAIL][141], [FAIL][142], [FAIL][143]) ([i915#1814] / [i915#2426] / [i915#3002] / [i915#3363] / [k.org#202321]) -> ([FAIL][144], [FAIL][145], [FAIL][146]) ([i915#2426] / [i915#3002] / [i915#3363] / [k.org#202321])
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6245/shard-glk2/igt@runner@aborted.html
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6245/shard-glk9/igt@runner@aborted.html
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_6245/shard-glk8/igt@runner@aborted.html
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_624

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_6320/index.html

[-- Attachment #2: Type: text/html, Size: 33660 bytes --]

Re: [igt-dev] [PATCH i-g-t 0/7] Prepare IGTs to allow only zero alignment

[Dixit, Ashutosh]

On Thu, 14 Oct 2021 01:19:10 -0700, Zbigniew Kempczyński wrote:
>
> In the future we're planning to allow passing only zero alignment so
> this is preparation step to introduce check and disable or fix
> igts which uses this constraint.
>
> v2: rename to gem_allows_obj_alignment() (Ashutosh)
>     addressing review comments from Ashutosh
>

For patches 1 through 6:

Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

For patch 7, I think the point below from my earlier email is still
unaddressed:

> So assigning a new offset will cause a new fault-in (bind) but not sure if
> it will cause an actual fault-out (unbind). Though I am not sure if there
> is actually a way to force it to happen if this doesn't work? Is there a
> way to verify that the unbind is actually happening?

Maybe if assign the same offset to a different object/page that will cause
a fault-out (unbind) followed by a fault-in (bind).

Re: [igt-dev] [PATCH i-g-t 0/7] Prepare IGTs to allow only zero alignment

[Zbigniew Kempczyński]

On Thu, Oct 14, 2021 at 08:28:30AM -0700, Dixit, Ashutosh wrote:
> On Thu, 14 Oct 2021 01:19:10 -0700, Zbigniew Kempczyński wrote:
> >
> > In the future we're planning to allow passing only zero alignment so
> > this is preparation step to introduce check and disable or fix
> > igts which uses this constraint.
> >
> > v2: rename to gem_allows_obj_alignment() (Ashutosh)
> >     addressing review comments from Ashutosh
> >
> 
> For patches 1 through 6:
> 
> Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> 
> For patch 7, I think the point below from my earlier email is still
> unaddressed:
> 
> > So assigning a new offset will cause a new fault-in (bind) but not sure if
> > it will cause an actual fault-out (unbind). Though I am not sure if there
> > is actually a way to force it to happen if this doesn't work? Is there a
> > way to verify that the unbind is actually happening?
> 
> Maybe if assign the same offset to a different object/page that will cause
> a fault-out (unbind) followed by a fault-in (bind).

For softpin case if you're changing the offset i915 will unbind/bind vma
in ppgtt, see eb_vma_misplaced() condition:

	if (flags & EXEC_OBJECT_PINNED &&
	    vma->node.start != entry->offset)
		return true;

so when you will go out from eb_pin_vma() with an error in else {} part
i915_vma_unbind() will be called. You can verify this using dynamic ftrace.

I'm not able to do this on !ppgtt due to lack of such gen.

--
Zbigniew

Re: [igt-dev] [PATCH i-g-t 0/7] Prepare IGTs to allow only zero alignment

[Dixit, Ashutosh]

On Thu, 14 Oct 2021 08:53:06 -0700, Zbigniew Kempczyński wrote:
>
> On Thu, Oct 14, 2021 at 08:28:30AM -0700, Dixit, Ashutosh wrote:
> > On Thu, 14 Oct 2021 01:19:10 -0700, Zbigniew Kempczyński wrote:
> > >
> > > In the future we're planning to allow passing only zero alignment so
> > > this is preparation step to introduce check and disable or fix
> > > igts which uses this constraint.
> > >
> > > v2: rename to gem_allows_obj_alignment() (Ashutosh)
> > >     addressing review comments from Ashutosh
> > >
> >
> > For patches 1 through 6:
> >
> > Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
> >
> > For patch 7, I think the point below from my earlier email is still
> > unaddressed:
> >
> > > So assigning a new offset will cause a new fault-in (bind) but not sure if
> > > it will cause an actual fault-out (unbind). Though I am not sure if there
> > > is actually a way to force it to happen if this doesn't work? Is there a
> > > way to verify that the unbind is actually happening?
> >
> > Maybe if assign the same offset to a different object/page that will cause
> > a fault-out (unbind) followed by a fault-in (bind).
>
> For softpin case if you're changing the offset i915 will unbind/bind vma
> in ppgtt, see eb_vma_misplaced() condition:
>
>	if (flags & EXEC_OBJECT_PINNED &&
>	    vma->node.start != entry->offset)
>		return true;
>
> so when you will go out from eb_pin_vma() with an error in else {} part
> i915_vma_unbind() will be called. You can verify this using dynamic ftrace.

Actually makes sense that if an object moves to a different offset that it
will be unbound from the previous offset. So yes this should work.

Re: [igt-dev] [PATCH i-g-t 7/7] benchmarks/gem_exec_fault: Add softpin mode to support gens with ppgtt

[Dixit, Ashutosh]

On Thu, 14 Oct 2021 01:19:17 -0700, Zbigniew Kempczyński wrote:
>
> @@ -127,9 +151,14 @@ static int loop(uint64_t size, unsigned ring, int reps, int ncpus,
>					obj.alignment = 0;
>					gem_execbuf(fd, &execbuf);
>
> -					/* fault out */
> -					obj.alignment = 1ull << 63;
> -					__gem_execbuf(fd, &execbuf);
> +					if (ahnd) {
> +						obj.offset = get_offset(ahnd, obj.handle, size, 0);
> +						obj.flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> +					} else {
> +						/* fault out */
> +						obj.alignment = 1ull << 63;
> +						__gem_execbuf(fd, &execbuf);
> +					}

Bug above, __gem_execbuf should be moved out of the else {}.

With the bug fixed this is:

Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

Re: [igt-dev] [PATCH i-g-t 7/7] benchmarks/gem_exec_fault: Add softpin mode to support gens with ppgtt

[Zbigniew Kempczyński]

On Thu, Oct 14, 2021 at 01:07:37PM -0700, Dixit, Ashutosh wrote:
> On Thu, 14 Oct 2021 01:19:17 -0700, Zbigniew Kempczyński wrote:
> >
> > @@ -127,9 +151,14 @@ static int loop(uint64_t size, unsigned ring, int reps, int ncpus,
> >					obj.alignment = 0;
> >					gem_execbuf(fd, &execbuf);
> >
> > -					/* fault out */
> > -					obj.alignment = 1ull << 63;
> > -					__gem_execbuf(fd, &execbuf);
> > +					if (ahnd) {
> > +						obj.offset = get_offset(ahnd, obj.handle, size, 0);
> > +						obj.flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> > +					} else {
> > +						/* fault out */
> > +						obj.alignment = 1ull << 63;
> > +						__gem_execbuf(fd, &execbuf);
> > +					}
> 
> Bug above, __gem_execbuf should be moved out of the else {}.

No, it shouldn't. Normal execbuf will lead to unbind/bind with new offset
and no 'alignment' fault-out execbuf is necessary.

--
Zbigniew

> 
> With the bug fixed this is:
> 
> Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

Re: [igt-dev] [PATCH i-g-t 7/7] benchmarks/gem_exec_fault: Add softpin mode to support gens with ppgtt

[Dixit, Ashutosh]

On Thu, 14 Oct 2021 19:49:05 -0700, Zbigniew Kempczyński wrote:
>
> On Thu, Oct 14, 2021 at 01:07:37PM -0700, Dixit, Ashutosh wrote:
> > On Thu, 14 Oct 2021 01:19:17 -0700, Zbigniew Kempczyński wrote:
> > >
> > > @@ -127,9 +151,14 @@ static int loop(uint64_t size, unsigned ring, int reps, int ncpus,
> > >					obj.alignment = 0;
> > >					gem_execbuf(fd, &execbuf);
> > >
> > > -					/* fault out */
> > > -					obj.alignment = 1ull << 63;
> > > -					__gem_execbuf(fd, &execbuf);
> > > +					if (ahnd) {
> > > +						obj.offset = get_offset(ahnd, obj.handle, size, 0);
> > > +						obj.flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> > > +					} else {
> > > +						/* fault out */
> > > +						obj.alignment = 1ull << 63;
> > > +						__gem_execbuf(fd, &execbuf);
> > > +					}
> >
> > Bug above, __gem_execbuf should be moved out of the else {}.
>
> No, it shouldn't. Normal execbuf will lead to unbind/bind with new offset
> and no 'alignment' fault-out execbuf is necessary.

Ah, you are right. Though in that case I think, if the loop has N
iterations, the number of binds is N and the number of unbinds will be (N -
1). Is it worth fixing that? Basically I think we might need to add a bind
outside the first iteration of the loop so that we have an unbind in the
first iteration itself. Then we will have N binds and N unbinds I think.

Re: [igt-dev] [PATCH i-g-t 7/7] benchmarks/gem_exec_fault: Add softpin mode to support gens with ppgtt

[Zbigniew Kempczyński]

On Thu, Oct 14, 2021 at 08:18:23PM -0700, Dixit, Ashutosh wrote:
> On Thu, 14 Oct 2021 19:49:05 -0700, Zbigniew Kempczyński wrote:
> >
> > On Thu, Oct 14, 2021 at 01:07:37PM -0700, Dixit, Ashutosh wrote:
> > > On Thu, 14 Oct 2021 01:19:17 -0700, Zbigniew Kempczyński wrote:
> > > >
> > > > @@ -127,9 +151,14 @@ static int loop(uint64_t size, unsigned ring, int reps, int ncpus,
> > > >					obj.alignment = 0;
> > > >					gem_execbuf(fd, &execbuf);
> > > >
> > > > -					/* fault out */
> > > > -					obj.alignment = 1ull << 63;
> > > > -					__gem_execbuf(fd, &execbuf);
> > > > +					if (ahnd) {
> > > > +						obj.offset = get_offset(ahnd, obj.handle, size, 0);
> > > > +						obj.flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> > > > +					} else {
> > > > +						/* fault out */
> > > > +						obj.alignment = 1ull << 63;
> > > > +						__gem_execbuf(fd, &execbuf);
> > > > +					}
> > >
> > > Bug above, __gem_execbuf should be moved out of the else {}.
> >
> > No, it shouldn't. Normal execbuf will lead to unbind/bind with new offset
> > and no 'alignment' fault-out execbuf is necessary.
> 
> Ah, you are right. Though in that case I think, if the loop has N
> iterations, the number of binds is N and the number of unbinds will be (N -
> 1). Is it worth fixing that? Basically I think we might need to add a bind
> outside the first iteration of the loop so that we have an unbind in the
> first iteration itself. Then we will have N binds and N unbinds I think.

You're right, for softpin case we got N-1. But I don't think we want to 
compare results between alignment / softpin paths but for dedicated changes
in the kernel. So then that missing unbind doesn't matter.

--
Zbigniew

Re: [igt-dev] [PATCH i-g-t 7/7] benchmarks/gem_exec_fault: Add softpin mode to support gens with ppgtt

[Dixit, Ashutosh]

On Thu, 14 Oct 2021 20:31:03 -0700, Zbigniew Kempczyński wrote:
>
> On Thu, Oct 14, 2021 at 08:18:23PM -0700, Dixit, Ashutosh wrote:
> > On Thu, 14 Oct 2021 19:49:05 -0700, Zbigniew Kempczyński wrote:
> > >
> > > On Thu, Oct 14, 2021 at 01:07:37PM -0700, Dixit, Ashutosh wrote:
> > > > On Thu, 14 Oct 2021 01:19:17 -0700, Zbigniew Kempczyński wrote:
> > > > >
> > > > > @@ -127,9 +151,14 @@ static int loop(uint64_t size, unsigned ring, int reps, int ncpus,
> > > > >					obj.alignment = 0;
> > > > >					gem_execbuf(fd, &execbuf);
> > > > >
> > > > > -					/* fault out */
> > > > > -					obj.alignment = 1ull << 63;
> > > > > -					__gem_execbuf(fd, &execbuf);
> > > > > +					if (ahnd) {
> > > > > +						obj.offset = get_offset(ahnd, obj.handle, size, 0);
> > > > > +						obj.flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> > > > > +					} else {
> > > > > +						/* fault out */
> > > > > +						obj.alignment = 1ull << 63;
> > > > > +						__gem_execbuf(fd, &execbuf);
> > > > > +					}
> > > >
> > > > Bug above, __gem_execbuf should be moved out of the else {}.
> > >
> > > No, it shouldn't. Normal execbuf will lead to unbind/bind with new offset
> > > and no 'alignment' fault-out execbuf is necessary.
> >
> > Ah, you are right. Though in that case I think, if the loop has N
> > iterations, the number of binds is N and the number of unbinds will be (N -
> > 1). Is it worth fixing that? Basically I think we might need to add a bind
> > outside the first iteration of the loop so that we have an unbind in the
> > first iteration itself. Then we will have N binds and N unbinds I think.
>
> You're right, for softpin case we got N-1. But I don't think we want to
> compare results between alignment / softpin paths but for dedicated changes
> in the kernel. So then that missing unbind doesn't matter.

I thought it is benchmarking the time taken for N binds and N unbinds so
not too sure how much difference N binds and N-1 unbinds make. Anyway
please go ahead and merge if you think it's fine.

Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

Re: [igt-dev] [PATCH i-g-t 7/7] benchmarks/gem_exec_fault: Add softpin mode to support gens with ppgtt

[Zbigniew Kempczyński]

On Thu, Oct 14, 2021 at 08:41:39PM -0700, Dixit, Ashutosh wrote:
> On Thu, 14 Oct 2021 20:31:03 -0700, Zbigniew Kempczyński wrote:
> >
> > On Thu, Oct 14, 2021 at 08:18:23PM -0700, Dixit, Ashutosh wrote:
> > > On Thu, 14 Oct 2021 19:49:05 -0700, Zbigniew Kempczyński wrote:
> > > >
> > > > On Thu, Oct 14, 2021 at 01:07:37PM -0700, Dixit, Ashutosh wrote:
> > > > > On Thu, 14 Oct 2021 01:19:17 -0700, Zbigniew Kempczyński wrote:
> > > > > >
> > > > > > @@ -127,9 +151,14 @@ static int loop(uint64_t size, unsigned ring, int reps, int ncpus,
> > > > > >					obj.alignment = 0;
> > > > > >					gem_execbuf(fd, &execbuf);
> > > > > >
> > > > > > -					/* fault out */
> > > > > > -					obj.alignment = 1ull << 63;
> > > > > > -					__gem_execbuf(fd, &execbuf);
> > > > > > +					if (ahnd) {
> > > > > > +						obj.offset = get_offset(ahnd, obj.handle, size, 0);
> > > > > > +						obj.flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
> > > > > > +					} else {
> > > > > > +						/* fault out */
> > > > > > +						obj.alignment = 1ull << 63;
> > > > > > +						__gem_execbuf(fd, &execbuf);
> > > > > > +					}
> > > > >
> > > > > Bug above, __gem_execbuf should be moved out of the else {}.
> > > >
> > > > No, it shouldn't. Normal execbuf will lead to unbind/bind with new offset
> > > > and no 'alignment' fault-out execbuf is necessary.
> > >
> > > Ah, you are right. Though in that case I think, if the loop has N
> > > iterations, the number of binds is N and the number of unbinds will be (N -
> > > 1). Is it worth fixing that? Basically I think we might need to add a bind
> > > outside the first iteration of the loop so that we have an unbind in the
> > > first iteration itself. Then we will have N binds and N unbinds I think.
> >
> > You're right, for softpin case we got N-1. But I don't think we want to
> > compare results between alignment / softpin paths but for dedicated changes
> > in the kernel. So then that missing unbind doesn't matter.
> 
> I thought it is benchmarking the time taken for N binds and N unbinds so
> not too sure how much difference N binds and N-1 unbinds make. Anyway
> please go ahead and merge if you think it's fine.
> 
> Reviewed-by: Ashutosh Dixit <ashutosh.dixit@intel.com>

Thank you for review. I think for benchmarking purposes last unbind 
is not so important - if we change kernel we will compare same number
of binds and unbinds and this imo does matter.

--
Zbigniew

Re: [igt-dev] [PATCH i-g-t 7/7] benchmarks/gem_exec_fault: Add softpin mode to support gens with ppgtt

[Zbigniew Kempczyński]

On Wed, Oct 13, 2021 at 10:01:22PM -0700, Dixit, Ashutosh wrote:
> On Thu, 07 Oct 2021 23:54:32 -0700, Zbigniew Kempczyński wrote:
> >
> > +	/*
> > +	 * For older gens .alignment = 1ull << 63 lead do bind/unbind,
> > +	 * what doesn't work for newer gens with ppgtt.
> > +	 * For ppgtt case we use reloc allocator which would just assigns
> > +	 * new offset for each batch. This way we enforce bind/unbind vma
> > +	 * for each execbuf.
> 
> So assigning a new offset will cause a new fault-in (bind) but not sure if
> it will cause an actual fault-out (unbind). Though I am not sure if there
> is actually a way to force it to happen if this doesn't work? Is there a
> way to verify that the unbind is actually happening?
> 
> Neither I am sure how setting the 'alignment = 1ull << 63' caused a fault
> out in the older code.

I got no access to !ppgtt gen but for my understanding in __gem_execbuf()
we will enforce unbind (trying to get offset at 1ull << 63) what is impossible
so unbind path will occur and some error code will be returned. But after
this we got object unbound so next time on !ppgtt gens when we set 0 alignment
kernel will choose some free offset for us. 

> 
> > +	 */
> > +	has_ppgtt = gem_uses_full_ppgtt(fd);
> > +	if (has_ppgtt) {
> > +		igt_info("Using softpin mode\n");
> > +		intel_allocator_multiprocess_start();
> > +	} else {
> > +		igt_assert(gem_allows_passing_alignment(fd));
> 
> I think this should be igt_require for the test to skip rather than fail.

I would not, I think for !ppgtt we want to have possibility passing 
alignment and benchmark requires that. Fail is much better imo because 
it will show something wrong has happened in the kernel we don't support.
And it requires attention from our side whereas skip may suggest it is 
expected while is not.

> 
> > +/*
> > + * NOTE: Ensure prove locking in the kernel is off, otherwise results
> > + * would be inaccurate.
> > + */
> 
> This is really a debug setting, any such setting (say lockdep, kmemchek
> etc.) will affect benchmarks. So not sure if this specifically needs to be
> called out.

You're right - this comment is unnecessary here. Any debugging options
in the kernel will have influence on benchmarking so we shouldn't run
benchmarks there.

--
Zbigniew

Re: [igt-dev] [PATCH i-g-t 7/7] benchmarks/gem_exec_fault: Add softpin mode to support gens with ppgtt

[Dixit, Ashutosh]

On Wed, 13 Oct 2021 22:01:22 -0700, Dixit, Ashutosh wrote:
>
> On Thu, 07 Oct 2021 23:54:32 -0700, Zbigniew Kempczyński wrote:
> >
> > +	/*
> > +	 * For older gens .alignment = 1ull << 63 lead do bind/unbind,
> > +	 * what doesn't work for newer gens with ppgtt.
> > +	 * For ppgtt case we use reloc allocator which would just assigns
> > +	 * new offset for each batch. This way we enforce bind/unbind vma
> > +	 * for each execbuf.
>
> So assigning a new offset will cause a new fault-in (bind) but not sure if
> it will cause an actual fault-out (unbind). Though I am not sure if there
> is actually a way to force it to happen if this doesn't work? Is there a
> way to verify that the unbind is actually happening?

Maybe if assign the same offset to a different object/page that will cause
a fault-out (unbind) followed by a fault-in (bind).

Re: [igt-dev] [PATCH i-g-t 7/7] benchmarks/gem_exec_fault: Add softpin mode to support gens with ppgtt

[Dixit, Ashutosh]

On Thu, 07 Oct 2021 23:54:32 -0700, Zbigniew Kempczyński wrote:
>
> +	/*
> +	 * For older gens .alignment = 1ull << 63 lead do bind/unbind,
> +	 * what doesn't work for newer gens with ppgtt.
> +	 * For ppgtt case we use reloc allocator which would just assigns
> +	 * new offset for each batch. This way we enforce bind/unbind vma
> +	 * for each execbuf.

So assigning a new offset will cause a new fault-in (bind) but not sure if
it will cause an actual fault-out (unbind). Though I am not sure if there
is actually a way to force it to happen if this doesn't work? Is there a
way to verify that the unbind is actually happening?

Neither I am sure how setting the 'alignment = 1ull << 63' caused a fault
out in the older code.

> +	 */
> +	has_ppgtt = gem_uses_full_ppgtt(fd);
> +	if (has_ppgtt) {
> +		igt_info("Using softpin mode\n");
> +		intel_allocator_multiprocess_start();
> +	} else {
> +		igt_assert(gem_allows_passing_alignment(fd));

I think this should be igt_require for the test to skip rather than fail.

> +/*
> + * NOTE: Ensure prove locking in the kernel is off, otherwise results
> + * would be inaccurate.
> + */

This is really a debug setting, any such setting (say lockdep, kmemchek
etc.) will affect benchmarks. So not sure if this specifically needs to be
called out.

[igt-dev] [PATCH i-g-t 7/7] benchmarks/gem_exec_fault: Add softpin mode to support gens with ppgtt

[Zbigniew Kempczyński]

Alignment trick doesn't work properly for ppgtt gens - kernel is able
to keep previous offset and doesn't call unbind/bind. With softpin
on ppgtt we're able to enforce rebind and benchmark should behave
correctly on such gens.

To avoid inaccurate results kernel CONFIG_PROVE_LOCKING should be set
to N, otherwise kernel can call unbind/bind for same offset more than
one (backoff is not visible from userspace).

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Petri Latvala <petri.latvala@intel.com>
Cc: Ashutosh Dixit <ashutosh.dixit@intel.com>
---
 benchmarks/gem_exec_fault.c | 47 +++++++++++++++++++++++++++++++++----
 1 file changed, 43 insertions(+), 4 deletions(-)

diff --git a/benchmarks/gem_exec_fault.c b/benchmarks/gem_exec_fault.c
index fe940b44c..40f11f4f1 100644
--- a/benchmarks/gem_exec_fault.c
+++ b/benchmarks/gem_exec_fault.c
@@ -43,7 +43,9 @@
 #include "drm.h"
 #include "drmtest.h"
 #include "i915/gem_create.h"
+#include "i915/gem_submission.h"
 #include "igt_stats.h"
+#include "intel_allocator.h"
 #include "intel_io.h"
 #include "intel_reg.h"
 #include "ioctl_wrappers.h"
@@ -74,11 +76,28 @@ static int loop(uint64_t size, unsigned ring, int reps, int ncpus,
 	unsigned nengine;
 	double *shared;
 	int fd;
+	bool has_ppgtt;
 
 	shared = mmap(0, 4096, PROT_WRITE, MAP_SHARED | MAP_ANON, -1, 0);
 
 	fd = drm_open_driver(DRIVER_INTEL);
 
+	/*
+	 * For older gens .alignment = 1ull << 63 lead do bind/unbind,
+	 * what doesn't work for newer gens with ppgtt.
+	 * For ppgtt case we use reloc allocator which would just assigns
+	 * new offset for each batch. This way we enforce bind/unbind vma
+	 * for each execbuf.
+	 */
+	has_ppgtt = gem_uses_full_ppgtt(fd);
+	if (has_ppgtt) {
+		igt_info("Using softpin mode\n");
+		intel_allocator_multiprocess_start();
+	} else {
+		igt_assert(gem_allows_passing_alignment(fd));
+		igt_info("Using alignment mode\n");
+	}
+
 	memset(&obj, 0, sizeof(obj));
 	obj.handle = batch(fd, 4096);
 
@@ -92,6 +111,7 @@ static int loop(uint64_t size, unsigned ring, int reps, int ncpus,
 		if (__gem_execbuf(fd, &execbuf))
 			return 77;
 	}
+
 	/* let the small object leak; ideally blocking the low address */
 
 	nengine = 0;
@@ -106,7 +126,7 @@ static int loop(uint64_t size, unsigned ring, int reps, int ncpus,
 		engines[nengine++] = ring;
 
 	if (size > 1ul << 31)
-		obj.flags |= 1 << 3;
+		obj.flags |= EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
 
 	while (reps--) {
 		memset(shared, 0, 4096);
@@ -114,10 +134,14 @@ static int loop(uint64_t size, unsigned ring, int reps, int ncpus,
 		igt_fork(child, ncpus) {
 			struct timespec start, end;
 			unsigned count = 0;
+			uint64_t ahnd = 0;
 
 			obj.handle = batch(fd, size);
 			obj.offset = -1;
 
+			if (has_ppgtt)
+				ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_RELOC);
+
 			clock_gettime(CLOCK_MONOTONIC, &start);
 			do {
 				for (int inner = 0; inner < 1024; inner++) {
@@ -127,9 +151,14 @@ static int loop(uint64_t size, unsigned ring, int reps, int ncpus,
 					obj.alignment = 0;
 					gem_execbuf(fd, &execbuf);
 
-					/* fault out */
-					obj.alignment = 1ull << 63;
-					__gem_execbuf(fd, &execbuf);
+					if (ahnd) {
+						obj.offset = get_offset(ahnd, obj.handle, size, 0);
+						obj.flags |= EXEC_OBJECT_PINNED | EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
+					} else {
+						/* fault out */
+						obj.alignment = 1ull << 63;
+						__gem_execbuf(fd, &execbuf);
+					}
 
 					clock_gettime(CLOCK_MONOTONIC, &end);
 					if (elapsed(&start, &end) >= timeout) {
@@ -144,6 +173,8 @@ static int loop(uint64_t size, unsigned ring, int reps, int ncpus,
 			shared[child] = 1e6*elapsed(&start, &end) / count / 2;
 
 			gem_close(fd, obj.handle);
+			if (ahnd)
+				intel_allocator_close(ahnd);
 		}
 		igt_waitchildren();
 
@@ -151,9 +182,17 @@ static int loop(uint64_t size, unsigned ring, int reps, int ncpus,
 			shared[ncpus] += shared[child];
 		printf("%7.3f\n", shared[ncpus] / ncpus);
 	}
+
+	if (has_ppgtt)
+		intel_allocator_multiprocess_stop();
+
 	return 0;
 }
 
+/*
+ * NOTE: Ensure prove locking in the kernel is off, otherwise results
+ * would be inaccurate.
+ */
 int main(int argc, char **argv)
 {
 	unsigned ring = I915_EXEC_RENDER;
-- 
2.26.0