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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org, stable@vger.kernel.org,
	"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
	"Thomas Hellström" <thomas.hellstrom@intel.com>
Subject: [PATCH 2/4] drm/i915: Convert unconditional clflush to drm_clflush_virt_range()
Date: Thu, 14 Oct 2021 12:09:39 +0300	[thread overview]
Message-ID: <20211014090941.12159-3-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20211014090941.12159-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

This one is apparently a "clflush for good measure", so bit more
justification (if you can call it that) than some of the others.
Convert to drm_clflush_virt_range() again so that machines without
clflush will survive the ordeal.

Cc: stable@vger.kernel.org
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Thomas Hellström <thomas.hellstrom@intel.com> #v1
Fixes: 12ca695d2c1e ("drm/i915: Do not share hwsp across contexts any more, v8.")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_timeline.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c b/drivers/gpu/drm/i915/gt/intel_timeline.c
index 1257f4f11e66..23d7328892ed 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.c
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
@@ -225,7 +225,7 @@ void intel_timeline_reset_seqno(const struct intel_timeline *tl)
 
 	memset(hwsp_seqno + 1, 0, TIMELINE_SEQNO_BYTES - sizeof(*hwsp_seqno));
 	WRITE_ONCE(*hwsp_seqno, tl->seqno);
-	clflush(hwsp_seqno);
+	drm_clflush_virt_range(hwsp_seqno, TIMELINE_SEQNO_BYTES);
 }
 
 void intel_timeline_enter(struct intel_timeline *tl)
-- 
2.32.0


WARNING: multiple messages have this Message-ID (diff)
From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org, stable@vger.kernel.org,
	"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
	"Thomas Hellström" <thomas.hellstrom@intel.com>
Subject: [Intel-gfx] [PATCH 2/4] drm/i915: Convert unconditional clflush to drm_clflush_virt_range()
Date: Thu, 14 Oct 2021 12:09:39 +0300	[thread overview]
Message-ID: <20211014090941.12159-3-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20211014090941.12159-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

This one is apparently a "clflush for good measure", so bit more
justification (if you can call it that) than some of the others.
Convert to drm_clflush_virt_range() again so that machines without
clflush will survive the ordeal.

Cc: stable@vger.kernel.org
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Thomas Hellström <thomas.hellstrom@intel.com> #v1
Fixes: 12ca695d2c1e ("drm/i915: Do not share hwsp across contexts any more, v8.")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/gt/intel_timeline.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c b/drivers/gpu/drm/i915/gt/intel_timeline.c
index 1257f4f11e66..23d7328892ed 100644
--- a/drivers/gpu/drm/i915/gt/intel_timeline.c
+++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
@@ -225,7 +225,7 @@ void intel_timeline_reset_seqno(const struct intel_timeline *tl)
 
 	memset(hwsp_seqno + 1, 0, TIMELINE_SEQNO_BYTES - sizeof(*hwsp_seqno));
 	WRITE_ONCE(*hwsp_seqno, tl->seqno);
-	clflush(hwsp_seqno);
+	drm_clflush_virt_range(hwsp_seqno, TIMELINE_SEQNO_BYTES);
 }
 
 void intel_timeline_enter(struct intel_timeline *tl)
-- 
2.32.0


  parent reply	other threads:[~2021-10-14  9:10 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-14  9:09 [PATCH 0/4] drm/i915: Make the driver not oops on load on old machines Ville Syrjala
2021-10-14  9:09 ` [Intel-gfx] " Ville Syrjala
2021-10-14  9:09 ` [PATCH 1/4] drm/i915: Replace the unconditional clflush with drm_clflush_virt_range() Ville Syrjala
2021-10-14  9:09   ` [Intel-gfx] " Ville Syrjala
2021-10-14  9:09 ` Ville Syrjala [this message]
2021-10-14  9:09   ` [Intel-gfx] [PATCH 2/4] drm/i915: Convert unconditional clflush to drm_clflush_virt_range() Ville Syrjala
2021-10-14  9:09 ` [PATCH 3/4] drm/i915: Catch yet another unconditioal clflush Ville Syrjala
2021-10-14  9:09   ` [Intel-gfx] " Ville Syrjala
2021-10-14  9:09 ` [PATCH 4/4] drm/i915: Fix oops on platforms w/o hpd support Ville Syrjala
2021-10-14  9:09   ` [Intel-gfx] " Ville Syrjala
2021-10-14  9:18   ` Jani Nikula
2021-10-14  9:18     ` [Intel-gfx] " Jani Nikula
2021-10-14  9:20     ` Jani Nikula
2021-10-14  9:20       ` [Intel-gfx] " Jani Nikula
2021-10-14  9:27       ` Ville Syrjälä
2021-10-14  9:27         ` [Intel-gfx] " Ville Syrjälä
2021-10-14  9:29     ` Ville Syrjälä
2021-10-14  9:29       ` [Intel-gfx] " Ville Syrjälä
2021-10-14  9:31       ` Sarvela, Tomi P
2021-10-14  9:31         ` [Intel-gfx] " Sarvela, Tomi P
2021-10-14  9:36         ` Ville Syrjälä
2021-10-14  9:36           ` [Intel-gfx] " Ville Syrjälä
2021-10-14  9:42           ` Sarvela, Tomi P
2021-10-14  9:42             ` [Intel-gfx] " Sarvela, Tomi P
2021-10-14 10:07 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Make the driver not oops on load on old machines Patchwork
2021-10-14 11:24 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-10-17 23:54 ` [PATCH 0/4] " Dave Airlie
2021-10-17 23:54   ` [Intel-gfx] " Dave Airlie
2021-10-19  9:08   ` Ville Syrjälä
2021-10-19  9:08     ` [Intel-gfx] " Ville Syrjälä

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