* [RFC PATCH 1/4] mm: modify pte format for Svnapot
@ 2021-10-18 1:59 Qinglin Pan
2021-10-18 1:59 ` [RFC PATCH 2/4] mm: support Svnapot in physical page linear-mapping Qinglin Pan
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Qinglin Pan @ 2021-10-18 1:59 UTC (permalink / raw)
To: linux-riscv; +Cc: xuyinan, Qinglin Pan
From: Qinglin Pan <panqinglin2020@iscas.ac.cn>
Svnapot is a RISC-V extension for marking contiguous 4K pages as a non-4K
page. Its concept proof will complete soon and this patch set is for using
Svnapot in Linux Kernel's boot process and hugetlb fs.
The draft spec about Svnapot can be found here:
https://github.com/riscv/virtual-memory/blob/main/specs/
This patch modifies PTE definition for Svnapot, and creates some functions in
pgtable.h to mark a PTE as napot and check if it is a Svnapot PTE.
Until now, only 64KB napot size is supported in draft spec, so some macros
has only 64KB version.
The qemu which we use to test this patchset can be in this repo:
https://github.com/plctlab/plct-qemu/tree/plct-virtmem-dev
Yours,
Qinglin
Signed-off-by: Qinglin Pan <panqinglin2020@iscas.ac.cn>
---
arch/riscv/include/asm/pgtable-bits.h | 29 +++++++++++++++++++++++++++
arch/riscv/include/asm/pgtable.h | 23 ++++++++++++++++++++-
2 files changed, 51 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
index 2ee413912926..8369e4d45919 100644
--- a/arch/riscv/include/asm/pgtable-bits.h
+++ b/arch/riscv/include/asm/pgtable-bits.h
@@ -24,6 +24,26 @@
#define _PAGE_DIRTY (1 << 7) /* Set by hardware on any write */
#define _PAGE_SOFT (1 << 8) /* Reserved for software */
+#define _PAGE_RESERVE_0_SHIFT 54
+#define _PAGE_RESERVE_1_SHIFT 55
+#define _PAGE_RESERVE_2_SHIFT 56
+#define _PAGE_RESERVE_3_SHIFT 57
+#define _PAGE_RESERVE_4_SHIFT 58
+#define _PAGE_RESERVE_5_SHIFT 59
+#define _PAGE_RESERVE_6_SHIFT 60
+#define _PAGE_RESERVE_7_SHIFT 61
+#define _PAGE_RESERVE_8_SHIFT 62
+#define _PAGE_NAPOT_SHIFT 63
+#define _PAGE_RESERVE_0 (1UL << 54)
+#define _PAGE_RESERVE_1 (1UL << 55)
+#define _PAGE_RESERVE_2 (1UL << 56)
+#define _PAGE_RESERVE_3 (1UL << 57)
+#define _PAGE_RESERVE_4 (1UL << 58)
+#define _PAGE_RESERVE_5 (1UL << 59)
+#define _PAGE_RESERVE_6 (1UL << 60)
+#define _PAGE_RESERVE_7 (1UL << 61)
+#define _PAGE_RESERVE_8 (1UL << 62)
+
#define _PAGE_SPECIAL _PAGE_SOFT
#define _PAGE_TABLE _PAGE_PRESENT
@@ -34,6 +54,15 @@
#define _PAGE_PROT_NONE _PAGE_READ
#define _PAGE_PFN_SHIFT 10
+#define _PAGE_PFN_MASK (_PAGE_RESERVE_0 - (1UL << _PAGE_PFN_SHIFT))
+/* now Svnapot only supports 64KB*/
+#define NAPOT_CONT64KB_ORDER 4UL
+#define NAPOT_CONT64KB_SHIFT (NAPOT_CONT64KB_ORDER + PAGE_SHIFT)
+#define NAPOT_CONT64KB_SIZE (1UL << NAPOT_CONT64KB_SHIFT)
+#define NAPOT_CONT64KB_MASK (NAPOT_CONT64KB_SIZE - 1)
+#define NAPOT_64KB_PTE_NUM (1UL << NAPOT_CONT64KB_ORDER)
+#define _PAGE_NAPOT (1UL << _PAGE_NAPOT_SHIFT)
+#define NAPOT_64KB_MASK (7UL << _PAGE_PFN_SHIFT)
/* Set of bits to preserve across pte_modify() */
#define _PAGE_CHG_MASK (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ | \
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index 39b550310ec6..adacb877433d 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -251,7 +251,11 @@ static inline pte_t pud_pte(pud_t pud)
/* Yields the page frame number (PFN) of a page table entry */
static inline unsigned long pte_pfn(pte_t pte)
{
- return (pte_val(pte) >> _PAGE_PFN_SHIFT);
+ unsigned long val = pte_val(pte);
+ unsigned long is_napot = val >> _PAGE_NAPOT_SHIFT;
+ unsigned long pfn_field = (val & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT;
+ unsigned long res = (pfn_field - is_napot) & pfn_field;
+ return res;
}
#define pte_page(x) pfn_to_page(pte_pfn(x))
@@ -304,6 +308,23 @@ static inline int pte_special(pte_t pte)
return pte_val(pte) & _PAGE_SPECIAL;
}
+static inline unsigned long pte_napot(pte_t pte)
+{
+ return pte_val(pte) & _PAGE_NAPOT;
+}
+
+static inline pte_t pte_mknapot(pte_t pte, unsigned int order)
+{
+ unsigned long napot_bits = (1UL << (order - 1)) << _PAGE_PFN_SHIFT;
+ unsigned long lower_prot =
+ pte_val(pte) & ((1UL << _PAGE_PFN_SHIFT) - 1UL);
+ unsigned long upper_prot = (pte_val(pte) >> _PAGE_PFN_SHIFT)
+ << _PAGE_PFN_SHIFT;
+
+ return __pte(upper_prot | napot_bits | lower_prot | _PAGE_NAPOT);
+}
+
+
/* static inline pte_t pte_rdprotect(pte_t pte) */
static inline pte_t pte_wrprotect(pte_t pte)
--
2.32.0
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* [RFC PATCH 2/4] mm: support Svnapot in physical page linear-mapping
2021-10-18 1:59 [RFC PATCH 1/4] mm: modify pte format for Svnapot Qinglin Pan
@ 2021-10-18 1:59 ` Qinglin Pan
2021-10-18 1:59 ` [RFC PATCH 3/4] mm: support Svnapot in hugetlb page Qinglin Pan
2021-10-18 1:59 ` [RFC PATCH 4/4] mm: support Svnapot in huge vmap Qinglin Pan
2 siblings, 0 replies; 5+ messages in thread
From: Qinglin Pan @ 2021-10-18 1:59 UTC (permalink / raw)
To: linux-riscv; +Cc: xuyinan, Qinglin Pan
From: Qinglin Pan <panqinglin2020@iscas.ac.cn>
Svnapot is powerful when a physical region is going to mapped to a
virtual region. Kernel will do like this when mapping all allocable
physical pages to kernel vm space. This patch modify the
create_pte_mapping function used in linear-mapping procedure, so the
kernel can be able to use Svnapot when both address and length of
physical region are 64KB align. Code here will be executed only when
other size huge page is not suitable, so it can be an addition of
PMD_SIZE and PUD_SIZE mapping.
It is tested by setting qemu's memory to a 262272k region, and the
kernel can boot successfully.
Signed-off-by: Qinglin Pan <panqinglin2020@iscas.ac.cn>
---
arch/riscv/mm/init.c | 23 ++++++++++++++++++-----
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
index c0cddf0fc22d..60a8e1dca79a 100644
--- a/arch/riscv/mm/init.c
+++ b/arch/riscv/mm/init.c
@@ -314,8 +314,18 @@ static void __init create_pte_mapping(pte_t *ptep,
phys_addr_t sz, pgprot_t prot)
{
uintptr_t pte_idx = pte_index(va);
-
- BUG_ON(sz != PAGE_SIZE);
+ pte_t pte;
+
+ WARN_ON(sz != NAPOT_CONT64KB_SIZE && sz != PAGE_SIZE);
+ if (sz == NAPOT_CONT64KB_SIZE) {
+ do {
+ pte = pfn_pte(PFN_DOWN(pa), prot);
+ ptep[pte_idx] = pte_mknapot(pte, NAPOT_CONT64KB_ORDER);
+ pte_idx++;
+ sz -= PAGE_SIZE;
+ } while (sz > 0);
+ return;
+ }
if (pte_none(ptep[pte_idx]))
ptep[pte_idx] = pfn_pte(PFN_DOWN(pa), prot);
@@ -444,10 +454,13 @@ void __init create_pgd_mapping(pgd_t *pgdp,
static uintptr_t __init best_map_size(phys_addr_t base, phys_addr_t size)
{
/* Upgrade to PMD_SIZE mappings whenever possible */
- if ((base & (PMD_SIZE - 1)) || (size & (PMD_SIZE - 1)))
- return PAGE_SIZE;
+ if (!((base | size) & (PMD_SIZE - 1)))
+ return PMD_SIZE;
+
+ if (!((base | size) & (NAPOT_CONT64KB_SIZE - 1)))
+ return NAPOT_CONT64KB_SIZE;
- return PMD_SIZE;
+ return PAGE_SIZE;
}
#ifdef CONFIG_XIP_KERNEL
--
2.32.0
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* [RFC PATCH 3/4] mm: support Svnapot in hugetlb page
2021-10-18 1:59 [RFC PATCH 1/4] mm: modify pte format for Svnapot Qinglin Pan
2021-10-18 1:59 ` [RFC PATCH 2/4] mm: support Svnapot in physical page linear-mapping Qinglin Pan
@ 2021-10-18 1:59 ` Qinglin Pan
2021-10-18 1:59 ` [RFC PATCH 4/4] mm: support Svnapot in huge vmap Qinglin Pan
2 siblings, 0 replies; 5+ messages in thread
From: Qinglin Pan @ 2021-10-18 1:59 UTC (permalink / raw)
To: linux-riscv; +Cc: xuyinan, Qinglin Pan
From: Qinglin Pan <panqinglin2020@iscas.ac.cn>
Svnapot can be used to support 64KB hugetlb page, so it can become a new
option when using hugetlbfs. This patch adds a basic implementation of
hugetlb page, and support 64KB as a size in it by using Svnapot.
For test, boot kernel with command line contains "hugepagesz=64K
hugepages=20" and run a simple test like this:
int main() {
void *addr;
addr = mmap(NULL, 64 * 1024, PROT_WRITE | PROT_READ,
MAP_PRIVATE | MAP_ANONYMOUS | MAP_HUGETLB | MAP_HUGE_64KB, -1, 0);
printf("back from mmap \n");
long *ptr = (long *)addr;
unsigned int i = 0;
for(; i < 8 * 1024;i += 512) {
printf("%lp \n", ptr);
*ptr = 0xdeafabcd12345678;
ptr += 512;
}
ptr = (long *)addr;
i = 0;
for(; i < 8 * 1024;i += 512) {
if (*ptr != 0xdeafabcd12345678) {
printf("failed! 0x%lx \n", *ptr);
break;
}
ptr += 512;
}
if(i == 8 * 1024)
printf("simple test passed!\n");
}
And it should be passed.
Signed-off-by: Qinglin Pan <panqinglin2020@iscas.ac.cn>
---
arch/riscv/Kconfig | 2 +-
arch/riscv/include/asm/hugetlb.h | 29 +++-
arch/riscv/include/asm/page.h | 2 +-
arch/riscv/mm/hugetlbpage.c | 227 +++++++++++++++++++++++++++++++
4 files changed, 257 insertions(+), 3 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 301a54233c7e..0ae025686faf 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -176,7 +176,7 @@ config ARCH_SELECT_MEMORY_MODEL
def_bool ARCH_SPARSEMEM_ENABLE
config ARCH_WANT_GENERAL_HUGETLB
- def_bool y
+ def_bool !HUGETLB_PAGE
config ARCH_SUPPORTS_UPROBES
def_bool y
diff --git a/arch/riscv/include/asm/hugetlb.h b/arch/riscv/include/asm/hugetlb.h
index a5c2ca1d1cd8..fa99fb9226f7 100644
--- a/arch/riscv/include/asm/hugetlb.h
+++ b/arch/riscv/include/asm/hugetlb.h
@@ -2,7 +2,34 @@
#ifndef _ASM_RISCV_HUGETLB_H
#define _ASM_RISCV_HUGETLB_H
-#include <asm-generic/hugetlb.h>
#include <asm/page.h>
+extern pte_t arch_make_huge_pte(pte_t entry, unsigned int shift,
+ vm_flags_t flags);
+#define arch_make_huge_pte arch_make_huge_pte
+#define __HAVE_ARCH_HUGE_SET_HUGE_PTE_AT
+extern void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
+ pte_t *ptep, pte_t pte);
+#define __HAVE_ARCH_HUGE_PTEP_GET_AND_CLEAR
+extern pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
+ unsigned long addr, pte_t *ptep);
+#define __HAVE_ARCH_HUGE_PTEP_CLEAR_FLUSH
+extern void huge_ptep_clear_flush(struct vm_area_struct *vma,
+ unsigned long addr, pte_t *ptep);
+#define __HAVE_ARCH_HUGE_PTEP_SET_ACCESS_FLAGS
+extern int huge_ptep_set_access_flags(struct vm_area_struct *vma,
+ unsigned long addr, pte_t *ptep,
+ pte_t pte, int dirty);
+#define __HAVE_ARCH_HUGE_PTEP_SET_WRPROTECT
+extern void huge_ptep_set_wrprotect(struct mm_struct *mm,
+ unsigned long addr, pte_t *ptep);
+#define __HAVE_ARCH_HUGE_PTE_CLEAR
+extern void huge_pte_clear(struct mm_struct *mm, unsigned long addr,
+ pte_t *ptep, unsigned long sz);
+#define set_huge_swap_pte_at riscv_set_huge_swap_pte_at
+extern void riscv_set_huge_swap_pte_at(struct mm_struct *mm, unsigned long addr,
+ pte_t *ptep, pte_t pte, unsigned long sz);
+
+#include <asm-generic/hugetlb.h>
+
#endif /* _ASM_RISCV_HUGETLB_H */
diff --git a/arch/riscv/include/asm/page.h b/arch/riscv/include/asm/page.h
index 109c97e991a6..e67506dbcd53 100644
--- a/arch/riscv/include/asm/page.h
+++ b/arch/riscv/include/asm/page.h
@@ -17,7 +17,7 @@
#define PAGE_MASK (~(PAGE_SIZE - 1))
#ifdef CONFIG_64BIT
-#define HUGE_MAX_HSTATE 2
+#define HUGE_MAX_HSTATE 3
#else
#define HUGE_MAX_HSTATE 1
#endif
diff --git a/arch/riscv/mm/hugetlbpage.c b/arch/riscv/mm/hugetlbpage.c
index 932dadfdca54..b88a8dbfec3e 100644
--- a/arch/riscv/mm/hugetlbpage.c
+++ b/arch/riscv/mm/hugetlbpage.c
@@ -2,6 +2,224 @@
#include <linux/hugetlb.h>
#include <linux/err.h>
+pte_t *huge_pte_alloc(struct mm_struct *mm, struct vm_area_struct *vma,
+ unsigned long addr, unsigned long sz)
+{
+ pgd_t *pgdp = pgd_offset(mm, addr);
+ p4d_t *p4dp = p4d_alloc(mm, pgdp, addr);
+ pud_t *pudp = pud_alloc(mm, p4dp, addr);
+ pmd_t *pmdp = pmd_alloc(mm, pudp, addr);
+
+ if (sz == NAPOT_CONT64KB_SIZE) {
+ if (!pmdp)
+ return NULL;
+ WARN_ON(addr & (sz - 1));
+ return pte_alloc_map(mm, pmdp, addr);
+ }
+
+ return NULL;
+}
+
+pte_t *huge_pte_offset(struct mm_struct *mm,
+ unsigned long addr, unsigned long sz)
+{
+ pgd_t *pgdp;
+ p4d_t *p4dp;
+ pud_t *pudp;
+ pmd_t *pmdp;
+ pte_t *ptep = NULL;
+
+ pgdp = pgd_offset(mm, addr);
+ if (!pgd_present(READ_ONCE(*pgdp)))
+ return NULL;
+
+ p4dp = p4d_offset(pgdp, addr);
+ if (!p4d_present(READ_ONCE(*p4dp)))
+ return NULL;
+
+ pudp = pud_offset(p4dp, addr);
+ if (!pud_present(READ_ONCE(*pudp)))
+ return NULL;
+
+ pmdp = pmd_offset(pudp, addr);
+ if (!pmd_present(READ_ONCE(*pmdp)))
+ return NULL;
+
+ if (sz == NAPOT_CONT64KB_SIZE)
+ ptep = pte_offset_kernel(pmdp, (addr & ~NAPOT_CONT64KB_MASK));
+
+ return ptep;
+}
+
+int napot_pte_num(pte_t pte)
+{
+ if (!(pte_val(pte) & NAPOT_64KB_MASK))
+ return NAPOT_64KB_PTE_NUM;
+
+ pr_warn("%s: unrecognized napot pte size 0x%lx\n",
+ __func__, pte_val(pte));
+ return 1;
+}
+
+static pte_t get_clear_flush(struct mm_struct *mm,
+ unsigned long addr,
+ pte_t *ptep,
+ unsigned long pte_num)
+{
+ pte_t orig_pte = huge_ptep_get(ptep);
+ bool valid = pte_val(orig_pte);
+ unsigned long i, saddr = addr;
+
+ for (i = 0; i < pte_num; i++, addr += PAGE_SIZE, ptep++) {
+ pte_t pte = ptep_get_and_clear(mm, addr, ptep);
+
+ if (pte_dirty(pte))
+ orig_pte = pte_mkdirty(orig_pte);
+
+ if (pte_young(pte))
+ orig_pte = pte_mkyoung(orig_pte);
+ }
+
+ if (valid) {
+ struct vm_area_struct vma = TLB_FLUSH_VMA(mm, 0);
+
+ flush_tlb_range(&vma, saddr, addr);
+ }
+ return orig_pte;
+}
+
+static void clear_flush(struct mm_struct *mm,
+ unsigned long addr,
+ pte_t *ptep,
+ unsigned long pte_num)
+{
+ struct vm_area_struct vma = TLB_FLUSH_VMA(mm, 0);
+ unsigned long i, saddr = addr;
+
+ for (i = 0; i < pte_num; i++, addr += PAGE_SIZE, ptep++)
+ pte_clear(mm, addr, ptep);
+
+ flush_tlb_range(&vma, saddr, addr);
+}
+
+pte_t arch_make_huge_pte(pte_t entry, unsigned int shift,
+ vm_flags_t flags)
+{
+ if (shift == NAPOT_CONT64KB_SHIFT)
+ entry = pte_mknapot(entry, NAPOT_CONT64KB_SHIFT - PAGE_SHIFT);
+
+ return entry;
+}
+
+void set_huge_pte_at(struct mm_struct *mm, unsigned long addr,
+ pte_t *ptep, pte_t pte)
+{
+ int i;
+ int pte_num;
+
+ if (!pte_napot(pte)) {
+ set_pte_at(mm, addr, ptep, pte);
+ return;
+ }
+
+ pte_num = napot_pte_num(pte);
+ for (i = 0; i < pte_num; i++, ptep++, addr += PAGE_SIZE)
+ set_pte_at(mm, addr, ptep, pte);
+}
+
+int huge_ptep_set_access_flags(struct vm_area_struct *vma,
+ unsigned long addr, pte_t *ptep,
+ pte_t pte, int dirty)
+{
+ pte_t orig_pte;
+ int i;
+ int pte_num;
+
+ if (!pte_napot(pte))
+ return ptep_set_access_flags(vma, addr, ptep, pte, dirty);
+
+ pte_num = napot_pte_num(pte);
+ ptep = huge_pte_offset(vma->vm_mm, addr, NAPOT_CONT64KB_SIZE);
+ orig_pte = huge_ptep_get(ptep);
+
+ if (pte_dirty(orig_pte))
+ pte = pte_mkdirty(pte);
+
+ if (pte_young(orig_pte))
+ pte = pte_mkyoung(pte);
+
+ for (i = 0; i < pte_num; i++, addr += PAGE_SIZE, ptep++)
+ ptep_set_access_flags(vma, addr, ptep, pte, dirty);
+
+ return true;
+}
+
+pte_t huge_ptep_get_and_clear(struct mm_struct *mm,
+ unsigned long addr, pte_t *ptep)
+{
+ int pte_num;
+ pte_t orig_pte = huge_ptep_get(ptep);
+
+ if (!pte_napot(orig_pte))
+ return ptep_get_and_clear(mm, addr, ptep);
+
+ pte_num = napot_pte_num(orig_pte);
+ return get_clear_flush(mm, addr, ptep, pte_num);
+}
+
+void huge_ptep_set_wrprotect(struct mm_struct *mm,
+ unsigned long addr, pte_t *ptep)
+{
+ int i;
+ int pte_num;
+ pte_t pte = READ_ONCE(*ptep);
+
+ if (!pte_napot(pte))
+ return ptep_set_wrprotect(mm, addr, ptep);
+
+ pte_num = napot_pte_num(pte);
+ ptep = huge_pte_offset(mm, addr, NAPOT_CONT64KB_SIZE);
+
+ for (i = 0; i < pte_num; i++, addr += PAGE_SIZE, ptep++)
+ ptep_set_wrprotect(mm, addr, ptep);
+}
+
+void huge_ptep_clear_flush(struct vm_area_struct *vma,
+ unsigned long addr, pte_t *ptep)
+{
+ int pte_num;
+ pte_t pte = READ_ONCE(*ptep);
+
+ if (!pte_napot(pte)) {
+ ptep_clear_flush(vma, addr, ptep);
+ return;
+ }
+
+ pte_num = napot_pte_num(pte);
+ clear_flush(vma->vm_mm, addr, ptep, pte_num);
+}
+
+void huge_pte_clear(struct mm_struct *mm, unsigned long addr,
+ pte_t *ptep, unsigned long sz)
+{
+ int i, pte_num;
+
+ pte_num = napot_pte_num(READ_ONCE(*ptep));
+ for (i = 0; i < pte_num; i++, addr += PAGE_SIZE, ptep++)
+ pte_clear(mm, addr, ptep);
+}
+
+void riscv_set_huge_swap_pte_at(struct mm_struct *mm, unsigned long addr,
+ pte_t *ptep, pte_t pte, unsigned long sz)
+{
+ int i, pte_num;
+
+ pte_num = napot_pte_num(READ_ONCE(*ptep));
+
+ for (i = 0; i < pte_num; i++, ptep++)
+ set_pte(ptep, pte);
+}
+
int pud_huge(pud_t pud)
{
return pud_leaf(pud);
@@ -18,6 +236,8 @@ bool __init arch_hugetlb_valid_size(unsigned long size)
return true;
else if (IS_ENABLED(CONFIG_64BIT) && size == PUD_SIZE)
return true;
+ else if (size == NAPOT_CONT64KB_SIZE)
+ return true;
else
return false;
}
@@ -32,3 +252,10 @@ static __init int gigantic_pages_init(void)
}
arch_initcall(gigantic_pages_init);
#endif
+
+static int __init hugetlbpage_init(void)
+{
+ hugetlb_add_hstate(NAPOT_CONT64KB_SHIFT - PAGE_SHIFT);
+ return 0;
+}
+arch_initcall(hugetlbpage_init);
--
2.32.0
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* [RFC PATCH 4/4] mm: support Svnapot in huge vmap
2021-10-18 1:59 [RFC PATCH 1/4] mm: modify pte format for Svnapot Qinglin Pan
2021-10-18 1:59 ` [RFC PATCH 2/4] mm: support Svnapot in physical page linear-mapping Qinglin Pan
2021-10-18 1:59 ` [RFC PATCH 3/4] mm: support Svnapot in hugetlb page Qinglin Pan
@ 2021-10-18 1:59 ` Qinglin Pan
2 siblings, 0 replies; 5+ messages in thread
From: Qinglin Pan @ 2021-10-18 1:59 UTC (permalink / raw)
To: linux-riscv; +Cc: xuyinan, Qinglin Pan
From: Qinglin Pan <panqinglin2020@iscas.ac.cn>
The HAVE_ARCH_HUGE_VMAP option can be used to help implement arch
special huge vmap size. This patch selects this option by default and
re-writes the arch_vmap_pte_range_map_size for Svnapot 64KB size.
It can be tested when booting kernel in qemu with pci device, which
will make the kernel to call pci driver using ioremap, and the
re-written function will be called.
Signed-off-by: Qinglin Pan <panqinglin2020@iscas.ac.cn>
---
arch/riscv/Kconfig | 1 +
arch/riscv/include/asm/pgtable.h | 35 ++++++++++++++++++++++++++++++++
arch/riscv/include/asm/vmalloc.h | 18 ++++++++++++++++
3 files changed, 54 insertions(+)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 0ae025686faf..4a57fd56daf8 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -13,6 +13,7 @@ config 32BIT
config RISCV
def_bool y
select ARCH_CLOCKSOURCE_INIT
+ select HAVE_ARCH_HUGE_VMAP
select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
select ARCH_HAS_BINFMT_FLAT
select ARCH_HAS_DEBUG_VM_PGTABLE
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index adacb877433d..218d95d30bfa 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -642,6 +642,41 @@ static inline pmd_t pmdp_establish(struct vm_area_struct *vma,
}
#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
+static inline int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot)
+{
+ return 0;
+}
+
+static inline int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot)
+{
+ return 0;
+}
+
+static inline int pud_clear_huge(pud_t *pud)
+{
+ return 0;
+}
+
+static inline int pmd_clear_huge(pmd_t *pmd)
+{
+ return 0;
+}
+
+static inline int p4d_free_pud_page(p4d_t *p4d, unsigned long addr)
+{
+ return 0;
+}
+
+static inline int pud_free_pmd_page(pud_t *pud, unsigned long addr)
+{
+ return 0;
+}
+
+static inline int pmd_free_pte_page(pmd_t *pmd, unsigned long addr)
+{
+ return 0;
+}
+
/*
* Encode and decode a swap entry
*
diff --git a/arch/riscv/include/asm/vmalloc.h b/arch/riscv/include/asm/vmalloc.h
index ff9abc00d139..fecfa24d6a13 100644
--- a/arch/riscv/include/asm/vmalloc.h
+++ b/arch/riscv/include/asm/vmalloc.h
@@ -1,4 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _ASM_RISCV_VMALLOC_H
#define _ASM_RISCV_VMALLOC_H
+#include <asm/pgtable-bits.h>
+
+#define arch_vmap_pte_range_map_size arch_vmap_pte_range_map_size
+static inline unsigned long arch_vmap_pte_range_map_size(unsigned long addr, unsigned long end,
+ u64 pfn, unsigned int max_page_shift)
+{
+ bool is_napot_addr = !(addr & NAPOT_CONT64KB_MASK);
+ bool pfn_align_napot = !(pfn & (NAPOT_64KB_PTE_NUM - 1UL));
+ bool space_enough = ((end - addr) >= NAPOT_CONT64KB_SIZE);
+
+ if (is_napot_addr && pfn_align_napot && space_enough
+ && max_page_shift >= NAPOT_CONT64KB_SHIFT)
+ return NAPOT_CONT64KB_SIZE;
+
+ return PAGE_SIZE;
+}
+
#endif /* _ASM_RISCV_VMALLOC_H */
--
2.32.0
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* [RFC PATCH 1/4] mm: modify pte format for Svnapot
@ 2021-10-18 2:22 Qinglin Pan
0 siblings, 0 replies; 5+ messages in thread
From: Qinglin Pan @ 2021-10-18 2:22 UTC (permalink / raw)
To: paul.walmsley, palmer, aou; +Cc: linux-riscv, Qinglin Pan
From: Qinglin Pan <panqinglin2020@iscas.ac.cn>
Svnapot is a RISC-V extension for marking contiguous 4K pages as a non-4K
page. Its concept proof will complete soon and this patch set is for using
Svnapot in Linux Kernel's boot process and hugetlb fs.
The draft spec about Svnapot can be found here:
https://github.com/riscv/virtual-memory/blob/main/specs/
This patch modifies PTE definition for Svnapot, and creates some functions in
pgtable.h to mark a PTE as napot and check if it is a Svnapot PTE.
Until now, only 64KB napot size is supported in draft spec, so some macros
has only 64KB version.
The qemu which we use to test this patchset can be in this repo:
https://github.com/plctlab/plct-qemu/tree/plct-virtmem-dev
Yours,
Qinglin
Signed-off-by: Qinglin Pan <panqinglin2020@iscas.ac.cn>
---
arch/riscv/include/asm/pgtable-bits.h | 29 +++++++++++++++++++++++++++
arch/riscv/include/asm/pgtable.h | 23 ++++++++++++++++++++-
2 files changed, 51 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/pgtable-bits.h b/arch/riscv/include/asm/pgtable-bits.h
index 2ee413912926..8369e4d45919 100644
--- a/arch/riscv/include/asm/pgtable-bits.h
+++ b/arch/riscv/include/asm/pgtable-bits.h
@@ -24,6 +24,26 @@
#define _PAGE_DIRTY (1 << 7) /* Set by hardware on any write */
#define _PAGE_SOFT (1 << 8) /* Reserved for software */
+#define _PAGE_RESERVE_0_SHIFT 54
+#define _PAGE_RESERVE_1_SHIFT 55
+#define _PAGE_RESERVE_2_SHIFT 56
+#define _PAGE_RESERVE_3_SHIFT 57
+#define _PAGE_RESERVE_4_SHIFT 58
+#define _PAGE_RESERVE_5_SHIFT 59
+#define _PAGE_RESERVE_6_SHIFT 60
+#define _PAGE_RESERVE_7_SHIFT 61
+#define _PAGE_RESERVE_8_SHIFT 62
+#define _PAGE_NAPOT_SHIFT 63
+#define _PAGE_RESERVE_0 (1UL << 54)
+#define _PAGE_RESERVE_1 (1UL << 55)
+#define _PAGE_RESERVE_2 (1UL << 56)
+#define _PAGE_RESERVE_3 (1UL << 57)
+#define _PAGE_RESERVE_4 (1UL << 58)
+#define _PAGE_RESERVE_5 (1UL << 59)
+#define _PAGE_RESERVE_6 (1UL << 60)
+#define _PAGE_RESERVE_7 (1UL << 61)
+#define _PAGE_RESERVE_8 (1UL << 62)
+
#define _PAGE_SPECIAL _PAGE_SOFT
#define _PAGE_TABLE _PAGE_PRESENT
@@ -34,6 +54,15 @@
#define _PAGE_PROT_NONE _PAGE_READ
#define _PAGE_PFN_SHIFT 10
+#define _PAGE_PFN_MASK (_PAGE_RESERVE_0 - (1UL << _PAGE_PFN_SHIFT))
+/* now Svnapot only supports 64KB*/
+#define NAPOT_CONT64KB_ORDER 4UL
+#define NAPOT_CONT64KB_SHIFT (NAPOT_CONT64KB_ORDER + PAGE_SHIFT)
+#define NAPOT_CONT64KB_SIZE (1UL << NAPOT_CONT64KB_SHIFT)
+#define NAPOT_CONT64KB_MASK (NAPOT_CONT64KB_SIZE - 1)
+#define NAPOT_64KB_PTE_NUM (1UL << NAPOT_CONT64KB_ORDER)
+#define _PAGE_NAPOT (1UL << _PAGE_NAPOT_SHIFT)
+#define NAPOT_64KB_MASK (7UL << _PAGE_PFN_SHIFT)
/* Set of bits to preserve across pte_modify() */
#define _PAGE_CHG_MASK (~(unsigned long)(_PAGE_PRESENT | _PAGE_READ | \
diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
index 39b550310ec6..adacb877433d 100644
--- a/arch/riscv/include/asm/pgtable.h
+++ b/arch/riscv/include/asm/pgtable.h
@@ -251,7 +251,11 @@ static inline pte_t pud_pte(pud_t pud)
/* Yields the page frame number (PFN) of a page table entry */
static inline unsigned long pte_pfn(pte_t pte)
{
- return (pte_val(pte) >> _PAGE_PFN_SHIFT);
+ unsigned long val = pte_val(pte);
+ unsigned long is_napot = val >> _PAGE_NAPOT_SHIFT;
+ unsigned long pfn_field = (val & _PAGE_PFN_MASK) >> _PAGE_PFN_SHIFT;
+ unsigned long res = (pfn_field - is_napot) & pfn_field;
+ return res;
}
#define pte_page(x) pfn_to_page(pte_pfn(x))
@@ -304,6 +308,23 @@ static inline int pte_special(pte_t pte)
return pte_val(pte) & _PAGE_SPECIAL;
}
+static inline unsigned long pte_napot(pte_t pte)
+{
+ return pte_val(pte) & _PAGE_NAPOT;
+}
+
+static inline pte_t pte_mknapot(pte_t pte, unsigned int order)
+{
+ unsigned long napot_bits = (1UL << (order - 1)) << _PAGE_PFN_SHIFT;
+ unsigned long lower_prot =
+ pte_val(pte) & ((1UL << _PAGE_PFN_SHIFT) - 1UL);
+ unsigned long upper_prot = (pte_val(pte) >> _PAGE_PFN_SHIFT)
+ << _PAGE_PFN_SHIFT;
+
+ return __pte(upper_prot | napot_bits | lower_prot | _PAGE_NAPOT);
+}
+
+
/* static inline pte_t pte_rdprotect(pte_t pte) */
static inline pte_t pte_wrprotect(pte_t pte)
--
2.32.0
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^ permalink raw reply related [flat|nested] 5+ messages in thread
end of thread, other threads:[~2021-10-18 2:23 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-10-18 1:59 [RFC PATCH 1/4] mm: modify pte format for Svnapot Qinglin Pan
2021-10-18 1:59 ` [RFC PATCH 2/4] mm: support Svnapot in physical page linear-mapping Qinglin Pan
2021-10-18 1:59 ` [RFC PATCH 3/4] mm: support Svnapot in hugetlb page Qinglin Pan
2021-10-18 1:59 ` [RFC PATCH 4/4] mm: support Svnapot in huge vmap Qinglin Pan
2021-10-18 2:22 [RFC PATCH 1/4] mm: modify pte format for Svnapot Qinglin Pan
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