From: "Paweł Anikiel" <pan@semihalf.com> To: dinguyen@kernel.org, robh+dt@kernel.org, arnd@arndb.de, olof@lixom.net, soc@kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, upstream@semihalf.com, mw@semihalf.com, jam@semihalf.com, ka@semihalf.com, tn@semihalf.com, amstan@google.com, "Paweł Anikiel" <pan@semihalf.com>, "Joanna Brozek" <jbrozek@antmicro.com>, "Mariusz Glebocki" <mglebocki@antmicro.com>, "Tomasz Gorochowik" <tgorochowik@antmicro.com>, "Maciej Mikunda" <mmikunda@antmicro.com> Subject: [PATCH v4 2/2] dts: socfpga: Add Mercury+ AA1 devicetree Date: Tue, 19 Oct 2021 16:12:28 +0200 [thread overview] Message-ID: <20211019141228.1271617-3-pan@semihalf.com> (raw) In-Reply-To: <20211019141228.1271617-1-pan@semihalf.com> Add support for the Mercury+ AA1 module for Arria 10 SoC FPGA. Signed-off-by: Paweł Anikiel <pan@semihalf.com> Signed-off-by: Joanna Brozek <jbrozek@antmicro.com> Signed-off-by: Mariusz Glebocki <mglebocki@antmicro.com> Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com> Signed-off-by: Maciej Mikunda <mmikunda@antmicro.com> --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/socfpga_arria10_mercury_aa1.dts | 105 ++++++++++++++++++ 2 files changed, 106 insertions(+) create mode 100644 arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7e0934180724..803702883122 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1075,6 +1075,7 @@ dtb-$(CONFIG_ARCH_S5PV210) += \ s5pv210-torbreck.dtb dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \ socfpga_arria5_socdk.dtb \ + socfpga_arria10_mercury_aa1.dtb \ socfpga_arria10_socdk_nand.dtb \ socfpga_arria10_socdk_qspi.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ diff --git a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts new file mode 100644 index 000000000000..d77d0c3d71b9 --- /dev/null +++ b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "socfpga_arria10.dtsi" + +/ { + + model = "Enclustra Mercury AA1"; + compatible = "altr,socfpga-arria10", "altr,socfpga"; + + memory@0 { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x80000000>; /* 2GB */ + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; +}; + +&eccmgr { + sdmmca-ecc@ff8c2c00 { + compatible = "altr,socfpga-sdmmc-ecc"; + reg = <0xff8c2c00 0x400>; + altr,ecc-parent = <&mmc>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, + <47 IRQ_TYPE_LEVEL_HIGH>, + <16 IRQ_TYPE_LEVEL_HIGH>, + <48 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&gmac0 { + phy-mode = "rgmii"; + phy-addr = <0xffffffff>; /* probe for phy addr */ + + max-frame-size = <3800>; + status = "okay"; + + phy-handle = <&phy3>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy3: ethernet-phy@3 { + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <1860>; /* 960ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + reg = <3>; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + isl12022: isl12022@6f { + status = "okay"; + compatible = "isil,isl12022"; + reg = <0x6f>; + }; +}; + +/* Following mappings are taken from arria10 socdk dts */ +&mmc { + status = "okay"; + cap-sd-highspeed; + broken-cd; + bus-width = <4>; +}; + +&osc1 { + clock-frequency = <33330000>; +}; + +&uart1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; +}; -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: "Paweł Anikiel" <pan@semihalf.com> To: dinguyen@kernel.org, robh+dt@kernel.org, arnd@arndb.de, olof@lixom.net, soc@kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, upstream@semihalf.com, mw@semihalf.com, jam@semihalf.com, ka@semihalf.com, tn@semihalf.com, amstan@google.com, "Paweł Anikiel" <pan@semihalf.com>, "Joanna Brozek" <jbrozek@antmicro.com>, "Mariusz Glebocki" <mglebocki@antmicro.com>, "Tomasz Gorochowik" <tgorochowik@antmicro.com>, "Maciej Mikunda" <mmikunda@antmicro.com> Subject: [PATCH v4 2/2] dts: socfpga: Add Mercury+ AA1 devicetree Date: Tue, 19 Oct 2021 16:12:28 +0200 [thread overview] Message-ID: <20211019141228.1271617-3-pan@semihalf.com> (raw) Message-ID: <20211019141228.y5ZsWyc4qYFRFkCkR9DU2uAHp_BBOXuR_G2w-sk-qMo@z> (raw) In-Reply-To: <20211019141228.1271617-1-pan@semihalf.com> Add support for the Mercury+ AA1 module for Arria 10 SoC FPGA. Signed-off-by: Paweł Anikiel <pan@semihalf.com> Signed-off-by: Joanna Brozek <jbrozek@antmicro.com> Signed-off-by: Mariusz Glebocki <mglebocki@antmicro.com> Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com> Signed-off-by: Maciej Mikunda <mmikunda@antmicro.com> --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/socfpga_arria10_mercury_aa1.dts | 105 ++++++++++++++++++ 2 files changed, 106 insertions(+) create mode 100644 arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7e0934180724..803702883122 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1075,6 +1075,7 @@ dtb-$(CONFIG_ARCH_S5PV210) += \ s5pv210-torbreck.dtb dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \ socfpga_arria5_socdk.dtb \ + socfpga_arria10_mercury_aa1.dtb \ socfpga_arria10_socdk_nand.dtb \ socfpga_arria10_socdk_qspi.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ diff --git a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts new file mode 100644 index 000000000000..d77d0c3d71b9 --- /dev/null +++ b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "socfpga_arria10.dtsi" + +/ { + + model = "Enclustra Mercury AA1"; + compatible = "altr,socfpga-arria10", "altr,socfpga"; + + memory@0 { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x80000000>; /* 2GB */ + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; +}; + +&eccmgr { + sdmmca-ecc@ff8c2c00 { + compatible = "altr,socfpga-sdmmc-ecc"; + reg = <0xff8c2c00 0x400>; + altr,ecc-parent = <&mmc>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, + <47 IRQ_TYPE_LEVEL_HIGH>, + <16 IRQ_TYPE_LEVEL_HIGH>, + <48 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&gmac0 { + phy-mode = "rgmii"; + phy-addr = <0xffffffff>; /* probe for phy addr */ + + max-frame-size = <3800>; + status = "okay"; + + phy-handle = <&phy3>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy3: ethernet-phy@3 { + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <1860>; /* 960ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + reg = <3>; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + isl12022: isl12022@6f { + status = "okay"; + compatible = "isil,isl12022"; + reg = <0x6f>; + }; +}; + +/* Following mappings are taken from arria10 socdk dts */ +&mmc { + status = "okay"; + cap-sd-highspeed; + broken-cd; + bus-width = <4>; +}; + +&osc1 { + clock-frequency = <33330000>; +}; + +&uart1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; +}; -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-10-19 14:13 UTC|newest] Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-10-19 14:12 [PATCH v4 0/2] Add support for the Mercury+ AA1 module Paweł Anikiel 2021-10-19 14:12 ` Paweł Anikiel 2021-10-19 14:12 ` [PATCH v4 1/2] socfpga: dts: move arria10 aliases to socfpga_arria10.dtsi Paweł Anikiel 2021-10-19 14:12 ` Paweł Anikiel 2021-10-20 13:33 ` Arnd Bergmann 2021-10-20 13:33 ` Arnd Bergmann 2021-10-20 15:52 ` Paweł Anikiel 2021-10-20 15:52 ` Paweł Anikiel 2021-10-19 14:12 ` Paweł Anikiel [this message] 2021-10-19 14:12 ` [PATCH v4 2/2] dts: socfpga: Add Mercury+ AA1 devicetree Paweł Anikiel
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