All of lore.kernel.org
 help / color / mirror / Atom feed
* [PATCH] drm/amdgpu: Consolidate VCN firmware setup code
@ 2021-10-19 15:56 Alex Deucher
  2021-10-19 16:17 ` James Zhu
  0 siblings, 1 reply; 2+ messages in thread
From: Alex Deucher @ 2021-10-19 15:56 UTC (permalink / raw)
  To: amd-gfx; +Cc: Alex Deucher

Roughly the same code was present in all VCN versions.
Consolidate it into a single function.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 25 +++++++++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h |  2 ++
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c   | 10 +---------
 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c   | 10 +---------
 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c   | 17 +----------------
 drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c   | 20 +-------------------
 6 files changed, 31 insertions(+), 53 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index c7d316850570..dc823349f870 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -949,3 +949,28 @@ enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring)
 		return AMDGPU_RING_PRIO_0;
 	}
 }
+
+void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev)
+{
+	int i;
+	unsigned int idx;
+
+	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+		const struct common_firmware_header *hdr;
+		hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
+
+		for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
+			if (adev->vcn.harvest_config & (1 << i))
+				continue;
+			if (i == 0)
+				idx = AMDGPU_UCODE_ID_VCN;
+			else
+				idx = AMDGPU_UCODE_ID_VCN1;
+			adev->firmware.ucode[idx].ucode_id = idx;
+			adev->firmware.ucode[idx].fw = adev->vcn.fw;
+			adev->firmware.fw_size +=
+				ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
+		}
+		dev_info(adev->dev, "Will use PSP to load VCN firmware\n");
+	}
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 795cbaa02ff8..bfa27ea94804 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -310,4 +310,6 @@ int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout);
 
 enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring);
 
+void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev);
+
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index ad0d2564087c..d54d720b3cf6 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -111,15 +111,7 @@ static int vcn_v1_0_sw_init(void *handle)
 	/* Override the work func */
 	adev->vcn.idle_work.work.func = vcn_v1_0_idle_work_handler;
 
-	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
-		const struct common_firmware_header *hdr;
-		hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
-		adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
-		adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
-		adev->firmware.fw_size +=
-			ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
-		dev_info(adev->dev, "Will use PSP to load VCN firmware\n");
-	}
+	amdgpu_vcn_setup_ucode(adev);
 
 	r = amdgpu_vcn_resume(adev);
 	if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 091d8c0f6801..3883df5b31ab 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -115,15 +115,7 @@ static int vcn_v2_0_sw_init(void *handle)
 	if (r)
 		return r;
 
-	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
-		const struct common_firmware_header *hdr;
-		hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
-		adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
-		adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
-		adev->firmware.fw_size +=
-			ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
-		dev_info(adev->dev, "Will use PSP to load VCN firmware\n");
-	}
+	amdgpu_vcn_setup_ucode(adev);
 
 	r = amdgpu_vcn_resume(adev);
 	if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index 59f469bab005..44fc4c218433 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -139,22 +139,7 @@ static int vcn_v2_5_sw_init(void *handle)
 	if (r)
 		return r;
 
-	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
-		const struct common_firmware_header *hdr;
-		hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
-		adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
-		adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
-		adev->firmware.fw_size +=
-			ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
-
-		if (adev->vcn.num_vcn_inst == VCN25_MAX_HW_INSTANCES_ARCTURUS) {
-			adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].ucode_id = AMDGPU_UCODE_ID_VCN1;
-			adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].fw = adev->vcn.fw;
-			adev->firmware.fw_size +=
-				ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
-		}
-		dev_info(adev->dev, "Will use PSP to load VCN firmware\n");
-	}
+	amdgpu_vcn_setup_ucode(adev);
 
 	r = amdgpu_vcn_resume(adev);
 	if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index e311303a5e01..57b62fb04750 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -123,7 +123,6 @@ static int vcn_v3_0_sw_init(void *handle)
 {
 	struct amdgpu_ring *ring;
 	int i, j, r;
-	unsigned int idx;
 	int vcn_doorbell_index = 0;
 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
@@ -131,24 +130,7 @@ static int vcn_v3_0_sw_init(void *handle)
 	if (r)
 		return r;
 
-	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
-		const struct common_firmware_header *hdr;
-		hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
-
-		for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
-			if (adev->vcn.harvest_config & (1 << i))
-				continue;
-			if (i == 0)
-				idx = AMDGPU_UCODE_ID_VCN;
-			else
-				idx = AMDGPU_UCODE_ID_VCN1;
-			adev->firmware.ucode[idx].ucode_id = idx;
-			adev->firmware.ucode[idx].fw = adev->vcn.fw;
-			adev->firmware.fw_size +=
-				ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
-		}
-		dev_info(adev->dev, "Will use PSP to load VCN firmware\n");
-	}
+	amdgpu_vcn_setup_ucode(adev);
 
 	r = amdgpu_vcn_resume(adev);
 	if (r)
-- 
2.31.1


^ permalink raw reply related	[flat|nested] 2+ messages in thread
* Re: [PATCH] drm/amdgpu: Consolidate VCN firmware setup code
  2021-10-19 15:56 [PATCH] drm/amdgpu: Consolidate VCN firmware setup code Alex Deucher
@ 2021-10-19 16:17 ` James Zhu
  0 siblings, 0 replies; 2+ messages in thread
From: James Zhu @ 2021-10-19 16:17 UTC (permalink / raw)
  To: amd-gfx

[-- Attachment #1: Type: text/plain, Size: 6820 bytes --]

With two nit-pick below.

ThispatchisReviewed-by:JamesZhu<James.Zhu@amd.com>

On 2021-10-19 11:56 a.m., Alex Deucher wrote:
> Roughly the same code was present in all VCN versions.
> Consolidate it into a single function.
>
> Signed-off-by: Alex Deucher<alexander.deucher@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 25 +++++++++++++++++++++++++
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h |  2 ++
>   drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c   | 10 +---------
>   drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c   | 10 +---------
>   drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c   | 17 +----------------
>   drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c   | 20 +-------------------
>   6 files changed, 31 insertions(+), 53 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> index c7d316850570..dc823349f870 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> @@ -949,3 +949,28 @@ enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring)
>   		return AMDGPU_RING_PRIO_0;
>   	}
>   }
> +
> +void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev)
> +{
> +	int i;
> +	unsigned int idx;
> +
> +	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
> +		const struct common_firmware_header *hdr;
> +		hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
> +
> +		for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
> +			if (adev->vcn.harvest_config & (1 << i))
> +				continue;
[JZ] Add check if i > 2.
> +			if (i == 0)
> +				idx = AMDGPU_UCODE_ID_VCN;
> +			else
> +				idx = AMDGPU_UCODE_ID_VCN1;
> +			adev->firmware.ucode[idx].ucode_id = idx;
> +			adev->firmware.ucode[idx].fw = adev->vcn.fw;
> +			adev->firmware.fw_size +=
> +				ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
> +		}
> +		dev_info(adev->dev, "Will use PSP to load VCN firmware\n");
[JZ] DRM_DEV_INFO can be used instead .
> +	}
> +}
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> index 795cbaa02ff8..bfa27ea94804 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> @@ -310,4 +310,6 @@ int amdgpu_vcn_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout);
>   
>   enum amdgpu_ring_priority_level amdgpu_vcn_get_enc_ring_prio(int ring);
>   
> +void amdgpu_vcn_setup_ucode(struct amdgpu_device *adev);
> +
>   #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> index ad0d2564087c..d54d720b3cf6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> @@ -111,15 +111,7 @@ static int vcn_v1_0_sw_init(void *handle)
>   	/* Override the work func */
>   	adev->vcn.idle_work.work.func = vcn_v1_0_idle_work_handler;
>   
> -	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
> -		const struct common_firmware_header *hdr;
> -		hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
> -		adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
> -		adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
> -		adev->firmware.fw_size +=
> -			ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
> -		dev_info(adev->dev, "Will use PSP to load VCN firmware\n");
> -	}
> +	amdgpu_vcn_setup_ucode(adev);
>   
>   	r = amdgpu_vcn_resume(adev);
>   	if (r)
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> index 091d8c0f6801..3883df5b31ab 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> @@ -115,15 +115,7 @@ static int vcn_v2_0_sw_init(void *handle)
>   	if (r)
>   		return r;
>   
> -	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
> -		const struct common_firmware_header *hdr;
> -		hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
> -		adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
> -		adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
> -		adev->firmware.fw_size +=
> -			ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
> -		dev_info(adev->dev, "Will use PSP to load VCN firmware\n");
> -	}
> +	amdgpu_vcn_setup_ucode(adev);
>   
>   	r = amdgpu_vcn_resume(adev);
>   	if (r)
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> index 59f469bab005..44fc4c218433 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> @@ -139,22 +139,7 @@ static int vcn_v2_5_sw_init(void *handle)
>   	if (r)
>   		return r;
>   
> -	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
> -		const struct common_firmware_header *hdr;
> -		hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
> -		adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
> -		adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
> -		adev->firmware.fw_size +=
> -			ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
> -
> -		if (adev->vcn.num_vcn_inst == VCN25_MAX_HW_INSTANCES_ARCTURUS) {
> -			adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].ucode_id = AMDGPU_UCODE_ID_VCN1;
> -			adev->firmware.ucode[AMDGPU_UCODE_ID_VCN1].fw = adev->vcn.fw;
> -			adev->firmware.fw_size +=
> -				ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
> -		}
> -		dev_info(adev->dev, "Will use PSP to load VCN firmware\n");
> -	}
> +	amdgpu_vcn_setup_ucode(adev);
>   
>   	r = amdgpu_vcn_resume(adev);
>   	if (r)
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> index e311303a5e01..57b62fb04750 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> @@ -123,7 +123,6 @@ static int vcn_v3_0_sw_init(void *handle)
>   {
>   	struct amdgpu_ring *ring;
>   	int i, j, r;
> -	unsigned int idx;
>   	int vcn_doorbell_index = 0;
>   	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>   
> @@ -131,24 +130,7 @@ static int vcn_v3_0_sw_init(void *handle)
>   	if (r)
>   		return r;
>   
> -	if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
> -		const struct common_firmware_header *hdr;
> -		hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
> -
> -		for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
> -			if (adev->vcn.harvest_config & (1 << i))
> -				continue;
> -			if (i == 0)
> -				idx = AMDGPU_UCODE_ID_VCN;
> -			else
> -				idx = AMDGPU_UCODE_ID_VCN1;
> -			adev->firmware.ucode[idx].ucode_id = idx;
> -			adev->firmware.ucode[idx].fw = adev->vcn.fw;
> -			adev->firmware.fw_size +=
> -				ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
> -		}
> -		dev_info(adev->dev, "Will use PSP to load VCN firmware\n");
> -	}
> +	amdgpu_vcn_setup_ucode(adev);
>   
>   	r = amdgpu_vcn_resume(adev);
>   	if (r)

[-- Attachment #2: Type: text/html, Size: 7884 bytes --]

^ permalink raw reply	[flat|nested] 2+ messages in thread
end of thread, other threads:[~2021-10-19 16:17 UTC | newest]

Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-10-19 15:56 [PATCH] drm/amdgpu: Consolidate VCN firmware setup code Alex Deucher
2021-10-19 16:17 ` James Zhu

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.