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From: Claudiu Beznea <claudiu.beznea@microchip.com>
To: <nicolas.ferre@microchip.com>, <alexandre.belloni@bootlin.com>,
	<ludovic.desroches@microchip.com>, <robh+dt@kernel.org>
Cc: <linux-arm-kernel@lists.infradead.org>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	Eugen Hristev <eugen.hristev@microchip.com>,
	Claudiu Beznea <claudiu.beznea@microchip.com>
Subject: [PATCH 1/3] ARM: dts: at91: sama7g5: add rtc node
Date: Wed, 20 Oct 2021 12:46:54 +0300	[thread overview]
Message-ID: <20211020094656.3343242-2-claudiu.beznea@microchip.com> (raw)
In-Reply-To: <20211020094656.3343242-1-claudiu.beznea@microchip.com>

From: Eugen Hristev <eugen.hristev@microchip.com>

Add RTC node.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
[claudiu.beznea: add sama7g5 compatible as the IP has 2 extra registers
 compared with sam9x60]
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 arch/arm/boot/dts/sama7g5.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi
index 6a9d74a9e1ac..e16a337fd100 100644
--- a/arch/arm/boot/dts/sama7g5.dtsi
+++ b/arch/arm/boot/dts/sama7g5.dtsi
@@ -152,6 +152,13 @@ gpbr: gpbr@e001d060 {
 			reg = <0xe001d060 0x48>;
 		};
 
+		rtc: rtc@e001d0a8 {
+			compatible = "microchip,sama7g5-rtc", "microchip,sam9x60-rtc";
+			reg = <0xe001d0a8 0x30>;
+			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk32k 1>;
+		};
+
 		ps_wdt: watchdog@e001d180 {
 			compatible = "microchip,sama7g5-wdt";
 			reg = <0xe001d180 0x24>;
-- 
2.25.1


WARNING: multiple messages have this Message-ID (diff)
From: Claudiu Beznea <claudiu.beznea@microchip.com>
To: <nicolas.ferre@microchip.com>, <alexandre.belloni@bootlin.com>,
	<ludovic.desroches@microchip.com>, <robh+dt@kernel.org>
Cc: <linux-arm-kernel@lists.infradead.org>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	Eugen Hristev <eugen.hristev@microchip.com>,
	Claudiu Beznea <claudiu.beznea@microchip.com>
Subject: [PATCH 1/3] ARM: dts: at91: sama7g5: add rtc node
Date: Wed, 20 Oct 2021 12:46:54 +0300	[thread overview]
Message-ID: <20211020094656.3343242-2-claudiu.beznea@microchip.com> (raw)
In-Reply-To: <20211020094656.3343242-1-claudiu.beznea@microchip.com>

From: Eugen Hristev <eugen.hristev@microchip.com>

Add RTC node.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
[claudiu.beznea: add sama7g5 compatible as the IP has 2 extra registers
 compared with sam9x60]
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
 arch/arm/boot/dts/sama7g5.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi
index 6a9d74a9e1ac..e16a337fd100 100644
--- a/arch/arm/boot/dts/sama7g5.dtsi
+++ b/arch/arm/boot/dts/sama7g5.dtsi
@@ -152,6 +152,13 @@ gpbr: gpbr@e001d060 {
 			reg = <0xe001d060 0x48>;
 		};
 
+		rtc: rtc@e001d0a8 {
+			compatible = "microchip,sama7g5-rtc", "microchip,sam9x60-rtc";
+			reg = <0xe001d0a8 0x30>;
+			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk32k 1>;
+		};
+
 		ps_wdt: watchdog@e001d180 {
 			compatible = "microchip,sama7g5-wdt";
 			reg = <0xe001d180 0x24>;
-- 
2.25.1


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  reply	other threads:[~2021-10-20  9:47 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-20  9:46 [PATCH 0/3] ARM: dts: at91: enable leftover IPs Claudiu Beznea
2021-10-20  9:46 ` Claudiu Beznea
2021-10-20  9:46 ` Claudiu Beznea [this message]
2021-10-20  9:46   ` [PATCH 1/3] ARM: dts: at91: sama7g5: add rtc node Claudiu Beznea
2021-10-20  9:46 ` [PATCH 2/3] ARM: dts: at91: sama7g5: add tcb nodes Claudiu Beznea
2021-10-20  9:46   ` Claudiu Beznea
2021-10-20  9:46 ` [PATCH 3/3] ARM: dts: at91: sama7g5-ek: use blocks 0 and 1 of TCB0 as cs and ce Claudiu Beznea
2021-10-20  9:46   ` Claudiu Beznea
2021-10-21 11:47 ` [PATCH 0/3] ARM: dts: at91: enable leftover IPs Nicolas Ferre
2021-10-21 11:47   ` Nicolas Ferre

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