* [Intel-gfx] [PATCH v4 00/11] drm/i915: Simplify handling of modifiers
@ 2021-10-20 19:51 Imre Deak
2021-10-20 19:51 ` [Intel-gfx] [PATCH v4 01/11] drm/i915: Add a table with a descriptor for all i915 modifiers Imre Deak
` (14 more replies)
0 siblings, 15 replies; 19+ messages in thread
From: Imre Deak @ 2021-10-20 19:51 UTC (permalink / raw)
To: intel-gfx; +Cc: Juha-Pekka Heikkila, Ville Syrjälä, Jani Nikula
This is v4 of [1] addressing review comments from Jani and Ville in
patch 1 and 9.
[1] https://patchwork.freedesktop.org/series/95579/
Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Imre Deak (11):
drm/i915: Add a table with a descriptor for all i915 modifiers
drm/i915: Move intel_get_format_info() to intel_fb.c
drm/i915: Add tiling attribute to the modifier descriptor
drm/i915: Simplify the modifier check for interlaced scanout support
drm/i915: Unexport is_semiplanar_uv_plane()
drm/i915: Move intel_format_info_is_yuv_semiplanar() to intel_fb.c
drm/i915: Add a platform independent way to get the RC CCS CC plane
drm/i915: Handle CCS CC planes separately from CCS AUX planes
drm/i915: Add a platform independent way to check for CCS AUX planes
drm/i915: Move is_ccs_modifier() to intel_fb.c
drm/i915: Add functions to check for RC CCS CC and MC CCS modifiers
drivers/gpu/drm/i915/display/i9xx_plane.c | 30 +-
.../gpu/drm/i915/display/intel_atomic_plane.c | 1 +
drivers/gpu/drm/i915/display/intel_cursor.c | 19 +-
drivers/gpu/drm/i915/display/intel_display.c | 150 +----
drivers/gpu/drm/i915/display/intel_display.h | 3 -
.../drm/i915/display/intel_display_types.h | 17 -
drivers/gpu/drm/i915/display/intel_fb.c | 526 ++++++++++++++++--
drivers/gpu/drm/i915/display/intel_fb.h | 30 +-
drivers/gpu/drm/i915/display/intel_sprite.c | 35 +-
drivers/gpu/drm/i915/display/skl_scaler.c | 1 +
.../drm/i915/display/skl_universal_plane.c | 206 ++-----
drivers/gpu/drm/i915/intel_pm.c | 1 +
12 files changed, 612 insertions(+), 407 deletions(-)
--
2.27.0
^ permalink raw reply [flat|nested] 19+ messages in thread* [Intel-gfx] [PATCH v4 01/11] drm/i915: Add a table with a descriptor for all i915 modifiers 2021-10-20 19:51 [Intel-gfx] [PATCH v4 00/11] drm/i915: Simplify handling of modifiers Imre Deak @ 2021-10-20 19:51 ` Imre Deak 2021-10-21 10:14 ` Jani Nikula 2021-10-20 19:51 ` [Intel-gfx] [PATCH v4 02/11] drm/i915: Move intel_get_format_info() to intel_fb.c Imre Deak ` (13 subsequent siblings) 14 siblings, 1 reply; 19+ messages in thread From: Imre Deak @ 2021-10-20 19:51 UTC (permalink / raw) To: intel-gfx; +Cc: Ville Syrjälä, Juha-Pekka Heikkila, Jani Nikula Add a table describing all the framebuffer modifiers used by i915 at one place. This has the benefit of deduplicating the listing of supported modifiers for each platform and checking the support of these modifiers on a given plane. This also simplifies in a similar way getting some attribute for a modifier, for instance checking if the modifier is a CCS modifier type. While at it drop the cursor plane filtering from skl_plane_has_rc_ccs(), as the cursor plane is registered with DRM core elsewhere. v1: Unchanged. v2: - Keep the plane caps calculation in the plane code and pass an enum with these caps to intel_fb_get_modifiers(). (Ville) - Get the modifiers calling intel_fb_get_modifiers() in i9xx_plane.c as well. v3: - s/.id/.modifier/ (Ville) - Keep modifier_desc vs. plane_cap filter conditions consistent. (Ville) - Drop redundant cursor plane check from skl_plane_has_rc_ccs(). (Ville) - Use from, until display version fields in modifier_desc instead of a mask. (Jani) - Unexport struct intel_modifier_desc, separate its decl and init. (Jani) - Remove enum pipe, plane_id forward decls from intel_fb.h, which are not needed after v2. v4: - Reuse IS_DISPLAY_VER() instead of open-coding it. (Jani) - Preserve the current modifier order exposed to user space. (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> (v3) --- drivers/gpu/drm/i915/display/i9xx_plane.c | 30 +-- drivers/gpu/drm/i915/display/intel_cursor.c | 19 +- .../drm/i915/display/intel_display_types.h | 1 - drivers/gpu/drm/i915/display/intel_fb.c | 152 +++++++++++++++ drivers/gpu/drm/i915/display/intel_fb.h | 13 ++ drivers/gpu/drm/i915/display/intel_sprite.c | 35 +--- drivers/gpu/drm/i915/display/skl_scaler.c | 1 + .../drm/i915/display/skl_universal_plane.c | 178 +++++------------- 8 files changed, 245 insertions(+), 184 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index b1439ba78f67b..a939accff7ee2 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -60,22 +60,11 @@ static const u32 vlv_primary_formats[] = { DRM_FORMAT_XBGR16161616F, }; -static const u64 i9xx_format_modifiers[] = { - I915_FORMAT_MOD_X_TILED, - DRM_FORMAT_MOD_LINEAR, - DRM_FORMAT_MOD_INVALID -}; - static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane, u32 format, u64 modifier) { - switch (modifier) { - case DRM_FORMAT_MOD_LINEAR: - case I915_FORMAT_MOD_X_TILED: - break; - default: + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier)) return false; - } switch (format) { case DRM_FORMAT_C8: @@ -92,13 +81,8 @@ static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane, static bool i965_plane_format_mod_supported(struct drm_plane *_plane, u32 format, u64 modifier) { - switch (modifier) { - case DRM_FORMAT_MOD_LINEAR: - case I915_FORMAT_MOD_X_TILED: - break; - default: + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier)) return false; - } switch (format) { case DRM_FORMAT_C8: @@ -768,6 +752,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) struct intel_plane *plane; const struct drm_plane_funcs *plane_funcs; unsigned int supported_rotations; + const u64 *modifiers; const u32 *formats; int num_formats; int ret, zpos; @@ -875,21 +860,26 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) plane->disable_flip_done = ilk_primary_disable_flip_done; } + modifiers = intel_fb_plane_get_modifiers(dev_priv, PLANE_HAS_TILING); + if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, 0, plane_funcs, formats, num_formats, - i9xx_format_modifiers, + modifiers, DRM_PLANE_TYPE_PRIMARY, "primary %c", pipe_name(pipe)); else ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, 0, plane_funcs, formats, num_formats, - i9xx_format_modifiers, + modifiers, DRM_PLANE_TYPE_PRIMARY, "plane %c", plane_name(plane->i9xx_plane)); + + kfree(modifiers); + if (ret) goto fail; diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index 11842f2126130..6b08d8bca5cd4 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -28,11 +28,6 @@ static const u32 intel_cursor_formats[] = { DRM_FORMAT_ARGB8888, }; -static const u64 cursor_format_modifiers[] = { - DRM_FORMAT_MOD_LINEAR, - DRM_FORMAT_MOD_INVALID -}; - static u32 intel_cursor_base(const struct intel_plane_state *plane_state) { struct drm_i915_private *dev_priv = @@ -605,8 +600,10 @@ static bool i9xx_cursor_get_hw_state(struct intel_plane *plane, static bool intel_cursor_format_mod_supported(struct drm_plane *_plane, u32 format, u64 modifier) { - return modifier == DRM_FORMAT_MOD_LINEAR && - format == DRM_FORMAT_ARGB8888; + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier)) + return false; + + return format == DRM_FORMAT_ARGB8888; } static int @@ -754,6 +751,7 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, { struct intel_plane *cursor; int ret, zpos; + u64 *modifiers; cursor = intel_plane_alloc(); if (IS_ERR(cursor)) @@ -784,13 +782,18 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv)) cursor->cursor.size = ~0; + modifiers = intel_fb_plane_get_modifiers(dev_priv, PLANE_HAS_NO_CAPS); + ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base, 0, &intel_cursor_plane_funcs, intel_cursor_formats, ARRAY_SIZE(intel_cursor_formats), - cursor_format_modifiers, + modifiers, DRM_PLANE_TYPE_CURSOR, "cursor %c", pipe_name(pipe)); + + kfree(modifiers); + if (ret) goto fail; diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 1e42bf901263c..a4930a56bfa82 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1336,7 +1336,6 @@ struct intel_plane { enum plane_id id; enum pipe pipe; bool has_fbc; - bool has_ccs; bool need_async_flip_disable_wa; u32 frontbuffer_bit; diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index fa1f375e696bf..cf4748daf2acf 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -13,6 +13,158 @@ #define check_array_bounds(i915, a, i) drm_WARN_ON(&(i915)->drm, (i) >= ARRAY_SIZE(a)) +struct intel_modifier_desc { + u64 modifier; + struct { + u8 from; + u8 until; + } display_ver; +#define DISPLAY_VER_ALL { 0, -1 } + + u8 is_linear:1; + + struct { +#define INTEL_CCS_RC BIT(0) +#define INTEL_CCS_RC_CC BIT(1) +#define INTEL_CCS_MC BIT(2) + +#define INTEL_CCS_ANY (INTEL_CCS_RC | INTEL_CCS_RC_CC | INTEL_CCS_MC) + u8 type:3; + } ccs; +}; + +static const struct intel_modifier_desc intel_modifiers[] = { + { + .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, + .display_ver = { 12, 13 }, + + .ccs.type = INTEL_CCS_MC, + }, + { + .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, + .display_ver = { 12, 13 }, + + .ccs.type = INTEL_CCS_RC, + }, + { + .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC, + .display_ver = { 12, 13 }, + + .ccs.type = INTEL_CCS_RC_CC, + }, + { + .modifier = I915_FORMAT_MOD_Yf_TILED_CCS, + .display_ver = { 9, 11 }, + + .ccs.type = INTEL_CCS_RC, + }, + { + .modifier = I915_FORMAT_MOD_Y_TILED_CCS, + .display_ver = { 9, 11 }, + + .ccs.type = INTEL_CCS_RC, + }, + { + .modifier = I915_FORMAT_MOD_Yf_TILED, + .display_ver = { 9, 11 }, + }, + { + .modifier = I915_FORMAT_MOD_Y_TILED, + .display_ver = { 9, 13 }, + }, + { + .modifier = I915_FORMAT_MOD_X_TILED, + .display_ver = DISPLAY_VER_ALL, + }, + { + .modifier = DRM_FORMAT_MOD_LINEAR, + .display_ver = DISPLAY_VER_ALL, + + .is_linear = true, + }, +}; + +static bool is_ccs_type_modifier(const struct intel_modifier_desc *md, u8 ccs_type) +{ + return md->ccs.type & ccs_type; +} + +static bool plane_has_modifier(struct drm_i915_private *i915, + enum intel_plane_caps plane_caps, + const struct intel_modifier_desc *md) +{ + if (!IS_DISPLAY_VER(i915, md->display_ver.from, md->display_ver.until)) + return false; + + if (!md->is_linear && + !(plane_caps & PLANE_HAS_TILING)) + return false; + + if (is_ccs_type_modifier(md, INTEL_CCS_RC | INTEL_CCS_RC_CC) && + !(plane_caps & PLANE_HAS_CCS_RC)) + return false; + + if (is_ccs_type_modifier(md, INTEL_CCS_MC) && + !(plane_caps & PLANE_HAS_CCS_MC)) + return false; + + return true; +} + +/** + * intel_fb_plane_get_modifiers: Get the modifiers for the given platform and plane capabilities + * @i915: i915 device instance + * @plane_caps: capabilities for the plane the modifiers are queried for + * + * Returns: + * Returns the list of modifiers allowed by the @i915 platform and @plane_caps. + * The caller must free the returned buffer. + */ +u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915, + enum intel_plane_caps plane_caps) +{ + u64 *list, *p; + int count = 1; /* +1 for invalid modifier terminator */ + int i; + + for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) { + if (plane_has_modifier(i915, plane_caps, &intel_modifiers[i])) + count++; + } + + list = kmalloc_array(count, sizeof(*list), GFP_KERNEL); + if (drm_WARN_ON(&i915->drm, !list)) + return NULL; + + p = list; + for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) { + if (plane_has_modifier(i915, plane_caps, &intel_modifiers[i])) + *p++ = intel_modifiers[i].modifier; + } + *p++ = DRM_FORMAT_MOD_INVALID; + + return list; +} + +/** + * intel_fb_plane_supports_modifier: Determine if a modifier is supported by the given plane + * @plane: Plane to check the modifier support for + * @modifier: The modifier to check the support for + * + * Returns: + * %true if the @modifier is supported on @plane. + */ +bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier) +{ + int i; + + for (i = 0; i < plane->base.modifier_count; i++) + if (plane->base.modifiers[i] == modifier) + return true; + + return false; +} + bool is_ccs_plane(const struct drm_framebuffer *fb, int plane) { if (!is_ccs_modifier(fb->modifier)) diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h index 1cbdd84502bdd..0f77e81e69d29 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.h +++ b/drivers/gpu/drm/i915/display/intel_fb.h @@ -6,6 +6,7 @@ #ifndef __INTEL_FB_H__ #define __INTEL_FB_H__ +#include <linux/bits.h> #include <linux/types.h> struct drm_device; @@ -16,13 +17,25 @@ struct drm_i915_private; struct drm_mode_fb_cmd2; struct intel_fb_view; struct intel_framebuffer; +struct intel_plane; struct intel_plane_state; +enum intel_plane_caps { + PLANE_HAS_NO_CAPS = 0, + PLANE_HAS_TILING = BIT(0), + PLANE_HAS_CCS_RC = BIT(1), + PLANE_HAS_CCS_MC = BIT(2), +}; + bool is_ccs_plane(const struct drm_framebuffer *fb, int plane); bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane); bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane); bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane); +u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915, + enum intel_plane_caps plane_caps); +bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier); + bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane); int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane); diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index 08116f41da26a..2f4f47ab9da03 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -45,6 +45,7 @@ #include "intel_atomic_plane.h" #include "intel_de.h" #include "intel_display_types.h" +#include "intel_fb.h" #include "intel_frontbuffer.h" #include "intel_sprite.h" #include "i9xx_plane.h" @@ -1575,12 +1576,6 @@ static const u32 g4x_plane_formats[] = { DRM_FORMAT_VYUY, }; -static const u64 i9xx_plane_format_modifiers[] = { - I915_FORMAT_MOD_X_TILED, - DRM_FORMAT_MOD_LINEAR, - DRM_FORMAT_MOD_INVALID -}; - static const u32 snb_plane_formats[] = { DRM_FORMAT_XRGB8888, DRM_FORMAT_XBGR8888, @@ -1629,13 +1624,8 @@ static const u32 chv_pipe_b_sprite_formats[] = { static bool g4x_sprite_format_mod_supported(struct drm_plane *_plane, u32 format, u64 modifier) { - switch (modifier) { - case DRM_FORMAT_MOD_LINEAR: - case I915_FORMAT_MOD_X_TILED: - break; - default: + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier)) return false; - } switch (format) { case DRM_FORMAT_XRGB8888: @@ -1655,13 +1645,8 @@ static bool g4x_sprite_format_mod_supported(struct drm_plane *_plane, static bool snb_sprite_format_mod_supported(struct drm_plane *_plane, u32 format, u64 modifier) { - switch (modifier) { - case DRM_FORMAT_MOD_LINEAR: - case I915_FORMAT_MOD_X_TILED: - break; - default: + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier)) return false; - } switch (format) { case DRM_FORMAT_XRGB8888: @@ -1686,13 +1671,8 @@ static bool snb_sprite_format_mod_supported(struct drm_plane *_plane, static bool vlv_sprite_format_mod_supported(struct drm_plane *_plane, u32 format, u64 modifier) { - switch (modifier) { - case DRM_FORMAT_MOD_LINEAR: - case I915_FORMAT_MOD_X_TILED: - break; - default: + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier)) return false; - } switch (format) { case DRM_FORMAT_C8: @@ -1776,7 +1756,6 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, formats = vlv_plane_formats; num_formats = ARRAY_SIZE(vlv_plane_formats); } - modifiers = i9xx_plane_format_modifiers; plane_funcs = &vlv_sprite_funcs; } else if (DISPLAY_VER(dev_priv) >= 7) { @@ -1795,7 +1774,6 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, formats = snb_plane_formats; num_formats = ARRAY_SIZE(snb_plane_formats); - modifiers = i9xx_plane_format_modifiers; plane_funcs = &snb_sprite_funcs; } else { @@ -1806,7 +1784,6 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, plane->max_stride = g4x_sprite_max_stride; plane->min_cdclk = g4x_sprite_min_cdclk; - modifiers = i9xx_plane_format_modifiers; if (IS_SANDYBRIDGE(dev_priv)) { formats = snb_plane_formats; num_formats = ARRAY_SIZE(snb_plane_formats); @@ -1833,11 +1810,15 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, plane->id = PLANE_SPRITE0 + sprite; plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id); + modifiers = intel_fb_plane_get_modifiers(dev_priv, PLANE_HAS_TILING); + ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, 0, plane_funcs, formats, num_formats, modifiers, DRM_PLANE_TYPE_OVERLAY, "sprite %c", sprite_name(pipe, sprite)); + kfree(modifiers); + if (ret) goto fail; diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c index 37eabeff8197f..c2e94118566b6 100644 --- a/drivers/gpu/drm/i915/display/skl_scaler.c +++ b/drivers/gpu/drm/i915/display/skl_scaler.c @@ -4,6 +4,7 @@ */ #include "intel_de.h" #include "intel_display_types.h" +#include "intel_fb.h" #include "skl_scaler.h" #include "skl_universal_plane.h" diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 7444b88829ea7..7ee2114e420b7 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -163,50 +163,6 @@ static const u32 icl_hdr_plane_formats[] = { DRM_FORMAT_XVYU16161616, }; -static const u64 skl_plane_format_modifiers_noccs[] = { - I915_FORMAT_MOD_Yf_TILED, - I915_FORMAT_MOD_Y_TILED, - I915_FORMAT_MOD_X_TILED, - DRM_FORMAT_MOD_LINEAR, - DRM_FORMAT_MOD_INVALID -}; - -static const u64 skl_plane_format_modifiers_ccs[] = { - I915_FORMAT_MOD_Yf_TILED_CCS, - I915_FORMAT_MOD_Y_TILED_CCS, - I915_FORMAT_MOD_Yf_TILED, - I915_FORMAT_MOD_Y_TILED, - I915_FORMAT_MOD_X_TILED, - DRM_FORMAT_MOD_LINEAR, - DRM_FORMAT_MOD_INVALID -}; - -static const u64 gen12_plane_format_modifiers_mc_ccs[] = { - I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, - I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, - I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC, - I915_FORMAT_MOD_Y_TILED, - I915_FORMAT_MOD_X_TILED, - DRM_FORMAT_MOD_LINEAR, - DRM_FORMAT_MOD_INVALID -}; - -static const u64 gen12_plane_format_modifiers_rc_ccs[] = { - I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, - I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC, - I915_FORMAT_MOD_Y_TILED, - I915_FORMAT_MOD_X_TILED, - DRM_FORMAT_MOD_LINEAR, - DRM_FORMAT_MOD_INVALID -}; - -static const u64 adlp_step_a_plane_format_modifiers[] = { - I915_FORMAT_MOD_Y_TILED, - I915_FORMAT_MOD_X_TILED, - DRM_FORMAT_MOD_LINEAR, - DRM_FORMAT_MOD_INVALID -}; - int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) { switch (format) { @@ -1882,42 +1838,13 @@ static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv, } } -static bool skl_plane_has_ccs(struct drm_i915_private *dev_priv, - enum pipe pipe, enum plane_id plane_id) -{ - if (plane_id == PLANE_CURSOR) - return false; - - if (DISPLAY_VER(dev_priv) >= 11) - return true; - - if (IS_GEMINILAKE(dev_priv)) - return pipe != PIPE_C; - - return pipe != PIPE_C && - (plane_id == PLANE_PRIMARY || - plane_id == PLANE_SPRITE0); -} - static bool skl_plane_format_mod_supported(struct drm_plane *_plane, u32 format, u64 modifier) { struct intel_plane *plane = to_intel_plane(_plane); - switch (modifier) { - case DRM_FORMAT_MOD_LINEAR: - case I915_FORMAT_MOD_X_TILED: - case I915_FORMAT_MOD_Y_TILED: - case I915_FORMAT_MOD_Yf_TILED: - break; - case I915_FORMAT_MOD_Y_TILED_CCS: - case I915_FORMAT_MOD_Yf_TILED_CCS: - if (!plane->has_ccs) - return false; - break; - default: + if (!intel_fb_plane_supports_modifier(plane, modifier)) return false; - } switch (format) { case DRM_FORMAT_XRGB8888: @@ -1965,45 +1892,13 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane, } } -static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv, - enum plane_id plane_id) -{ - /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */ - if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) || - IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_D0)) - return false; - - /* Wa_22011186057 */ - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) - return false; - - return plane_id < PLANE_SPRITE4; -} - static bool gen12_plane_format_mod_supported(struct drm_plane *_plane, u32 format, u64 modifier) { - struct drm_i915_private *dev_priv = to_i915(_plane->dev); struct intel_plane *plane = to_intel_plane(_plane); - switch (modifier) { - case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: - if (!gen12_plane_supports_mc_ccs(dev_priv, plane->id)) - return false; - fallthrough; - case DRM_FORMAT_MOD_LINEAR: - case I915_FORMAT_MOD_X_TILED: - case I915_FORMAT_MOD_Y_TILED: - break; - case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: - case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: - /* Wa_22011186057 */ - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) - return false; - break; - default: + if (!intel_fb_plane_supports_modifier(plane, modifier)) return false; - } switch (format) { case DRM_FORMAT_XRGB8888: @@ -2051,18 +1946,6 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane, } } -static const u64 *gen12_get_plane_modifiers(struct drm_i915_private *dev_priv, - enum plane_id plane_id) -{ - /* Wa_22011186057 */ - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) - return adlp_step_a_plane_format_modifiers; - else if (gen12_plane_supports_mc_ccs(dev_priv, plane_id)) - return gen12_plane_format_modifiers_mc_ccs; - else - return gen12_plane_format_modifiers_rc_ccs; -} - static const struct drm_plane_funcs skl_plane_funcs = { .update_plane = drm_atomic_helper_update_plane, .disable_plane = drm_atomic_helper_disable_plane, @@ -2103,6 +1986,39 @@ skl_plane_disable_flip_done(struct intel_plane *plane) spin_unlock_irq(&i915->irq_lock); } +static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915, + enum pipe pipe, enum plane_id plane_id) +{ + /* Wa_22011186057 */ + if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) + return false; + + if (DISPLAY_VER(i915) >= 11) + return true; + + if (IS_GEMINILAKE(i915)) + return pipe != PIPE_C; + + return pipe != PIPE_C && + (plane_id == PLANE_PRIMARY || + plane_id == PLANE_SPRITE0); +} + +static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915, + enum plane_id plane_id) +{ + /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */ + if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || + IS_TGL_DISPLAY_STEP(i915, STEP_A0, STEP_D0)) + return false; + + /* Wa_22011186057 */ + if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) + return false; + + return plane_id < PLANE_SPRITE4; +} + struct intel_plane * skl_universal_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe, enum plane_id plane_id) @@ -2110,6 +2026,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, const struct drm_plane_funcs *plane_funcs; struct intel_plane *plane; enum drm_plane_type plane_type; + enum intel_plane_caps plane_caps; unsigned int supported_rotations; unsigned int supported_csc; const u64 *modifiers; @@ -2171,29 +2088,34 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, formats = skl_get_plane_formats(dev_priv, pipe, plane_id, &num_formats); - plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id); - if (DISPLAY_VER(dev_priv) >= 12) { - modifiers = gen12_get_plane_modifiers(dev_priv, plane_id); + if (DISPLAY_VER(dev_priv) >= 12) plane_funcs = &gen12_plane_funcs; - } else { - if (plane->has_ccs) - modifiers = skl_plane_format_modifiers_ccs; - else - modifiers = skl_plane_format_modifiers_noccs; + else plane_funcs = &skl_plane_funcs; - } if (plane_id == PLANE_PRIMARY) plane_type = DRM_PLANE_TYPE_PRIMARY; else plane_type = DRM_PLANE_TYPE_OVERLAY; + plane_caps = PLANE_HAS_TILING; + if (skl_plane_has_rc_ccs(dev_priv, pipe, plane_id)) + plane_caps |= PLANE_HAS_CCS_RC; + + if (gen12_plane_has_mc_ccs(dev_priv, plane_id)) + plane_caps |= PLANE_HAS_CCS_MC; + + modifiers = intel_fb_plane_get_modifiers(dev_priv, plane_caps); + ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, 0, plane_funcs, formats, num_formats, modifiers, plane_type, "plane %d%c", plane_id + 1, pipe_name(pipe)); + + kfree(modifiers); + if (ret) goto fail; -- 2.27.0 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH v4 01/11] drm/i915: Add a table with a descriptor for all i915 modifiers 2021-10-20 19:51 ` [Intel-gfx] [PATCH v4 01/11] drm/i915: Add a table with a descriptor for all i915 modifiers Imre Deak @ 2021-10-21 10:14 ` Jani Nikula 2021-10-21 10:49 ` Imre Deak 0 siblings, 1 reply; 19+ messages in thread From: Jani Nikula @ 2021-10-21 10:14 UTC (permalink / raw) To: Imre Deak, intel-gfx; +Cc: Ville Syrjälä, Juha-Pekka Heikkila On Wed, 20 Oct 2021, Imre Deak <imre.deak@intel.com> wrote: > Add a table describing all the framebuffer modifiers used by i915 at one > place. This has the benefit of deduplicating the listing of supported > modifiers for each platform and checking the support of these modifiers > on a given plane. This also simplifies in a similar way getting some > attribute for a modifier, for instance checking if the modifier is a > CCS modifier type. > > While at it drop the cursor plane filtering from skl_plane_has_rc_ccs(), > as the cursor plane is registered with DRM core elsewhere. > > v1: Unchanged. > v2: > - Keep the plane caps calculation in the plane code and pass an enum > with these caps to intel_fb_get_modifiers(). (Ville) > - Get the modifiers calling intel_fb_get_modifiers() in i9xx_plane.c as > well. > v3: > - s/.id/.modifier/ (Ville) > - Keep modifier_desc vs. plane_cap filter conditions consistent. (Ville) > - Drop redundant cursor plane check from skl_plane_has_rc_ccs(). (Ville) > - Use from, until display version fields in modifier_desc instead of a mask. (Jani) > - Unexport struct intel_modifier_desc, separate its decl and init. (Jani) > - Remove enum pipe, plane_id forward decls from intel_fb.h, which are > not needed after v2. > v4: > - Reuse IS_DISPLAY_VER() instead of open-coding it. (Jani) > - Preserve the current modifier order exposed to user space. (Ville) > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> > Cc: Jani Nikula <jani.nikula@intel.com> > Signed-off-by: Imre Deak <imre.deak@intel.com> > Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> (v3) > --- > drivers/gpu/drm/i915/display/i9xx_plane.c | 30 +-- > drivers/gpu/drm/i915/display/intel_cursor.c | 19 +- > .../drm/i915/display/intel_display_types.h | 1 - > drivers/gpu/drm/i915/display/intel_fb.c | 152 +++++++++++++++ > drivers/gpu/drm/i915/display/intel_fb.h | 13 ++ > drivers/gpu/drm/i915/display/intel_sprite.c | 35 +--- > drivers/gpu/drm/i915/display/skl_scaler.c | 1 + > .../drm/i915/display/skl_universal_plane.c | 178 +++++------------- > 8 files changed, 245 insertions(+), 184 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c > index b1439ba78f67b..a939accff7ee2 100644 > --- a/drivers/gpu/drm/i915/display/i9xx_plane.c > +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c > @@ -60,22 +60,11 @@ static const u32 vlv_primary_formats[] = { > DRM_FORMAT_XBGR16161616F, > }; > > -static const u64 i9xx_format_modifiers[] = { > - I915_FORMAT_MOD_X_TILED, > - DRM_FORMAT_MOD_LINEAR, > - DRM_FORMAT_MOD_INVALID > -}; > - > static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane, > u32 format, u64 modifier) > { > - switch (modifier) { > - case DRM_FORMAT_MOD_LINEAR: > - case I915_FORMAT_MOD_X_TILED: > - break; > - default: > + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier)) > return false; > - } > > switch (format) { > case DRM_FORMAT_C8: > @@ -92,13 +81,8 @@ static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane, > static bool i965_plane_format_mod_supported(struct drm_plane *_plane, > u32 format, u64 modifier) > { > - switch (modifier) { > - case DRM_FORMAT_MOD_LINEAR: > - case I915_FORMAT_MOD_X_TILED: > - break; > - default: > + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier)) > return false; > - } > > switch (format) { > case DRM_FORMAT_C8: > @@ -768,6 +752,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) > struct intel_plane *plane; > const struct drm_plane_funcs *plane_funcs; > unsigned int supported_rotations; > + const u64 *modifiers; > const u32 *formats; > int num_formats; > int ret, zpos; > @@ -875,21 +860,26 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) > plane->disable_flip_done = ilk_primary_disable_flip_done; > } > > + modifiers = intel_fb_plane_get_modifiers(dev_priv, PLANE_HAS_TILING); > + > if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) > ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, > 0, plane_funcs, > formats, num_formats, > - i9xx_format_modifiers, > + modifiers, > DRM_PLANE_TYPE_PRIMARY, > "primary %c", pipe_name(pipe)); > else > ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, > 0, plane_funcs, > formats, num_formats, > - i9xx_format_modifiers, > + modifiers, > DRM_PLANE_TYPE_PRIMARY, > "plane %c", > plane_name(plane->i9xx_plane)); > + > + kfree(modifiers); > + > if (ret) > goto fail; > > diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c > index 11842f2126130..6b08d8bca5cd4 100644 > --- a/drivers/gpu/drm/i915/display/intel_cursor.c > +++ b/drivers/gpu/drm/i915/display/intel_cursor.c > @@ -28,11 +28,6 @@ static const u32 intel_cursor_formats[] = { > DRM_FORMAT_ARGB8888, > }; > > -static const u64 cursor_format_modifiers[] = { > - DRM_FORMAT_MOD_LINEAR, > - DRM_FORMAT_MOD_INVALID > -}; > - > static u32 intel_cursor_base(const struct intel_plane_state *plane_state) > { > struct drm_i915_private *dev_priv = > @@ -605,8 +600,10 @@ static bool i9xx_cursor_get_hw_state(struct intel_plane *plane, > static bool intel_cursor_format_mod_supported(struct drm_plane *_plane, > u32 format, u64 modifier) > { > - return modifier == DRM_FORMAT_MOD_LINEAR && > - format == DRM_FORMAT_ARGB8888; > + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier)) > + return false; > + > + return format == DRM_FORMAT_ARGB8888; > } > > static int > @@ -754,6 +751,7 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, > { > struct intel_plane *cursor; > int ret, zpos; > + u64 *modifiers; > > cursor = intel_plane_alloc(); > if (IS_ERR(cursor)) > @@ -784,13 +782,18 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, > if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv)) > cursor->cursor.size = ~0; > > + modifiers = intel_fb_plane_get_modifiers(dev_priv, PLANE_HAS_NO_CAPS); > + > ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base, > 0, &intel_cursor_plane_funcs, > intel_cursor_formats, > ARRAY_SIZE(intel_cursor_formats), > - cursor_format_modifiers, > + modifiers, > DRM_PLANE_TYPE_CURSOR, > "cursor %c", pipe_name(pipe)); > + > + kfree(modifiers); > + > if (ret) > goto fail; > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h > index 1e42bf901263c..a4930a56bfa82 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -1336,7 +1336,6 @@ struct intel_plane { > enum plane_id id; > enum pipe pipe; > bool has_fbc; > - bool has_ccs; > bool need_async_flip_disable_wa; > u32 frontbuffer_bit; > > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c > index fa1f375e696bf..cf4748daf2acf 100644 > --- a/drivers/gpu/drm/i915/display/intel_fb.c > +++ b/drivers/gpu/drm/i915/display/intel_fb.c > @@ -13,6 +13,158 @@ > > #define check_array_bounds(i915, a, i) drm_WARN_ON(&(i915)->drm, (i) >= ARRAY_SIZE(a)) > > +struct intel_modifier_desc { > + u64 modifier; > + struct { > + u8 from; > + u8 until; > + } display_ver; > +#define DISPLAY_VER_ALL { 0, -1 } > + > + u8 is_linear:1; > + > + struct { > +#define INTEL_CCS_RC BIT(0) > +#define INTEL_CCS_RC_CC BIT(1) > +#define INTEL_CCS_MC BIT(2) > + > +#define INTEL_CCS_ANY (INTEL_CCS_RC | INTEL_CCS_RC_CC | INTEL_CCS_MC) > + u8 type:3; > + } ccs; > +}; > + > +static const struct intel_modifier_desc intel_modifiers[] = { > + { > + .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, > + .display_ver = { 12, 13 }, > + > + .ccs.type = INTEL_CCS_MC, > + }, > + { Argh, I meant to comment that "}, {" on one line is customary for stuff like this to reduce the vertical space. If you need to do another spin for other reasons, please include this change, otherwise it can be a follow-up. BR, Jani. > + .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, > + .display_ver = { 12, 13 }, > + > + .ccs.type = INTEL_CCS_RC, > + }, > + { > + .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC, > + .display_ver = { 12, 13 }, > + > + .ccs.type = INTEL_CCS_RC_CC, > + }, > + { > + .modifier = I915_FORMAT_MOD_Yf_TILED_CCS, > + .display_ver = { 9, 11 }, > + > + .ccs.type = INTEL_CCS_RC, > + }, > + { > + .modifier = I915_FORMAT_MOD_Y_TILED_CCS, > + .display_ver = { 9, 11 }, > + > + .ccs.type = INTEL_CCS_RC, > + }, > + { > + .modifier = I915_FORMAT_MOD_Yf_TILED, > + .display_ver = { 9, 11 }, > + }, > + { > + .modifier = I915_FORMAT_MOD_Y_TILED, > + .display_ver = { 9, 13 }, > + }, > + { > + .modifier = I915_FORMAT_MOD_X_TILED, > + .display_ver = DISPLAY_VER_ALL, > + }, > + { > + .modifier = DRM_FORMAT_MOD_LINEAR, > + .display_ver = DISPLAY_VER_ALL, > + > + .is_linear = true, > + }, > +}; > + > +static bool is_ccs_type_modifier(const struct intel_modifier_desc *md, u8 ccs_type) > +{ > + return md->ccs.type & ccs_type; > +} > + > +static bool plane_has_modifier(struct drm_i915_private *i915, > + enum intel_plane_caps plane_caps, > + const struct intel_modifier_desc *md) > +{ > + if (!IS_DISPLAY_VER(i915, md->display_ver.from, md->display_ver.until)) > + return false; > + > + if (!md->is_linear && > + !(plane_caps & PLANE_HAS_TILING)) > + return false; > + > + if (is_ccs_type_modifier(md, INTEL_CCS_RC | INTEL_CCS_RC_CC) && > + !(plane_caps & PLANE_HAS_CCS_RC)) > + return false; > + > + if (is_ccs_type_modifier(md, INTEL_CCS_MC) && > + !(plane_caps & PLANE_HAS_CCS_MC)) > + return false; > + > + return true; > +} > + > +/** > + * intel_fb_plane_get_modifiers: Get the modifiers for the given platform and plane capabilities > + * @i915: i915 device instance > + * @plane_caps: capabilities for the plane the modifiers are queried for > + * > + * Returns: > + * Returns the list of modifiers allowed by the @i915 platform and @plane_caps. > + * The caller must free the returned buffer. > + */ > +u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915, > + enum intel_plane_caps plane_caps) > +{ > + u64 *list, *p; > + int count = 1; /* +1 for invalid modifier terminator */ > + int i; > + > + for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) { > + if (plane_has_modifier(i915, plane_caps, &intel_modifiers[i])) > + count++; > + } > + > + list = kmalloc_array(count, sizeof(*list), GFP_KERNEL); > + if (drm_WARN_ON(&i915->drm, !list)) > + return NULL; > + > + p = list; > + for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) { > + if (plane_has_modifier(i915, plane_caps, &intel_modifiers[i])) > + *p++ = intel_modifiers[i].modifier; > + } > + *p++ = DRM_FORMAT_MOD_INVALID; > + > + return list; > +} > + > +/** > + * intel_fb_plane_supports_modifier: Determine if a modifier is supported by the given plane > + * @plane: Plane to check the modifier support for > + * @modifier: The modifier to check the support for > + * > + * Returns: > + * %true if the @modifier is supported on @plane. > + */ > +bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier) > +{ > + int i; > + > + for (i = 0; i < plane->base.modifier_count; i++) > + if (plane->base.modifiers[i] == modifier) > + return true; > + > + return false; > +} > + > bool is_ccs_plane(const struct drm_framebuffer *fb, int plane) > { > if (!is_ccs_modifier(fb->modifier)) > diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h > index 1cbdd84502bdd..0f77e81e69d29 100644 > --- a/drivers/gpu/drm/i915/display/intel_fb.h > +++ b/drivers/gpu/drm/i915/display/intel_fb.h > @@ -6,6 +6,7 @@ > #ifndef __INTEL_FB_H__ > #define __INTEL_FB_H__ > > +#include <linux/bits.h> > #include <linux/types.h> > > struct drm_device; > @@ -16,13 +17,25 @@ struct drm_i915_private; > struct drm_mode_fb_cmd2; > struct intel_fb_view; > struct intel_framebuffer; > +struct intel_plane; > struct intel_plane_state; > > +enum intel_plane_caps { > + PLANE_HAS_NO_CAPS = 0, > + PLANE_HAS_TILING = BIT(0), > + PLANE_HAS_CCS_RC = BIT(1), > + PLANE_HAS_CCS_MC = BIT(2), > +}; > + > bool is_ccs_plane(const struct drm_framebuffer *fb, int plane); > bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane); > bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane); > bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane); > > +u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915, > + enum intel_plane_caps plane_caps); > +bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier); > + > bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane); > > int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane); > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c > index 08116f41da26a..2f4f47ab9da03 100644 > --- a/drivers/gpu/drm/i915/display/intel_sprite.c > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c > @@ -45,6 +45,7 @@ > #include "intel_atomic_plane.h" > #include "intel_de.h" > #include "intel_display_types.h" > +#include "intel_fb.h" > #include "intel_frontbuffer.h" > #include "intel_sprite.h" > #include "i9xx_plane.h" > @@ -1575,12 +1576,6 @@ static const u32 g4x_plane_formats[] = { > DRM_FORMAT_VYUY, > }; > > -static const u64 i9xx_plane_format_modifiers[] = { > - I915_FORMAT_MOD_X_TILED, > - DRM_FORMAT_MOD_LINEAR, > - DRM_FORMAT_MOD_INVALID > -}; > - > static const u32 snb_plane_formats[] = { > DRM_FORMAT_XRGB8888, > DRM_FORMAT_XBGR8888, > @@ -1629,13 +1624,8 @@ static const u32 chv_pipe_b_sprite_formats[] = { > static bool g4x_sprite_format_mod_supported(struct drm_plane *_plane, > u32 format, u64 modifier) > { > - switch (modifier) { > - case DRM_FORMAT_MOD_LINEAR: > - case I915_FORMAT_MOD_X_TILED: > - break; > - default: > + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier)) > return false; > - } > > switch (format) { > case DRM_FORMAT_XRGB8888: > @@ -1655,13 +1645,8 @@ static bool g4x_sprite_format_mod_supported(struct drm_plane *_plane, > static bool snb_sprite_format_mod_supported(struct drm_plane *_plane, > u32 format, u64 modifier) > { > - switch (modifier) { > - case DRM_FORMAT_MOD_LINEAR: > - case I915_FORMAT_MOD_X_TILED: > - break; > - default: > + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier)) > return false; > - } > > switch (format) { > case DRM_FORMAT_XRGB8888: > @@ -1686,13 +1671,8 @@ static bool snb_sprite_format_mod_supported(struct drm_plane *_plane, > static bool vlv_sprite_format_mod_supported(struct drm_plane *_plane, > u32 format, u64 modifier) > { > - switch (modifier) { > - case DRM_FORMAT_MOD_LINEAR: > - case I915_FORMAT_MOD_X_TILED: > - break; > - default: > + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier)) > return false; > - } > > switch (format) { > case DRM_FORMAT_C8: > @@ -1776,7 +1756,6 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, > formats = vlv_plane_formats; > num_formats = ARRAY_SIZE(vlv_plane_formats); > } > - modifiers = i9xx_plane_format_modifiers; > > plane_funcs = &vlv_sprite_funcs; > } else if (DISPLAY_VER(dev_priv) >= 7) { > @@ -1795,7 +1774,6 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, > > formats = snb_plane_formats; > num_formats = ARRAY_SIZE(snb_plane_formats); > - modifiers = i9xx_plane_format_modifiers; > > plane_funcs = &snb_sprite_funcs; > } else { > @@ -1806,7 +1784,6 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, > plane->max_stride = g4x_sprite_max_stride; > plane->min_cdclk = g4x_sprite_min_cdclk; > > - modifiers = i9xx_plane_format_modifiers; > if (IS_SANDYBRIDGE(dev_priv)) { > formats = snb_plane_formats; > num_formats = ARRAY_SIZE(snb_plane_formats); > @@ -1833,11 +1810,15 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, > plane->id = PLANE_SPRITE0 + sprite; > plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id); > > + modifiers = intel_fb_plane_get_modifiers(dev_priv, PLANE_HAS_TILING); > + > ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, > 0, plane_funcs, > formats, num_formats, modifiers, > DRM_PLANE_TYPE_OVERLAY, > "sprite %c", sprite_name(pipe, sprite)); > + kfree(modifiers); > + > if (ret) > goto fail; > > diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c > index 37eabeff8197f..c2e94118566b6 100644 > --- a/drivers/gpu/drm/i915/display/skl_scaler.c > +++ b/drivers/gpu/drm/i915/display/skl_scaler.c > @@ -4,6 +4,7 @@ > */ > #include "intel_de.h" > #include "intel_display_types.h" > +#include "intel_fb.h" > #include "skl_scaler.h" > #include "skl_universal_plane.h" > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c > index 7444b88829ea7..7ee2114e420b7 100644 > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c > @@ -163,50 +163,6 @@ static const u32 icl_hdr_plane_formats[] = { > DRM_FORMAT_XVYU16161616, > }; > > -static const u64 skl_plane_format_modifiers_noccs[] = { > - I915_FORMAT_MOD_Yf_TILED, > - I915_FORMAT_MOD_Y_TILED, > - I915_FORMAT_MOD_X_TILED, > - DRM_FORMAT_MOD_LINEAR, > - DRM_FORMAT_MOD_INVALID > -}; > - > -static const u64 skl_plane_format_modifiers_ccs[] = { > - I915_FORMAT_MOD_Yf_TILED_CCS, > - I915_FORMAT_MOD_Y_TILED_CCS, > - I915_FORMAT_MOD_Yf_TILED, > - I915_FORMAT_MOD_Y_TILED, > - I915_FORMAT_MOD_X_TILED, > - DRM_FORMAT_MOD_LINEAR, > - DRM_FORMAT_MOD_INVALID > -}; > - > -static const u64 gen12_plane_format_modifiers_mc_ccs[] = { > - I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, > - I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, > - I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC, > - I915_FORMAT_MOD_Y_TILED, > - I915_FORMAT_MOD_X_TILED, > - DRM_FORMAT_MOD_LINEAR, > - DRM_FORMAT_MOD_INVALID > -}; > - > -static const u64 gen12_plane_format_modifiers_rc_ccs[] = { > - I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, > - I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC, > - I915_FORMAT_MOD_Y_TILED, > - I915_FORMAT_MOD_X_TILED, > - DRM_FORMAT_MOD_LINEAR, > - DRM_FORMAT_MOD_INVALID > -}; > - > -static const u64 adlp_step_a_plane_format_modifiers[] = { > - I915_FORMAT_MOD_Y_TILED, > - I915_FORMAT_MOD_X_TILED, > - DRM_FORMAT_MOD_LINEAR, > - DRM_FORMAT_MOD_INVALID > -}; > - > int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) > { > switch (format) { > @@ -1882,42 +1838,13 @@ static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv, > } > } > > -static bool skl_plane_has_ccs(struct drm_i915_private *dev_priv, > - enum pipe pipe, enum plane_id plane_id) > -{ > - if (plane_id == PLANE_CURSOR) > - return false; > - > - if (DISPLAY_VER(dev_priv) >= 11) > - return true; > - > - if (IS_GEMINILAKE(dev_priv)) > - return pipe != PIPE_C; > - > - return pipe != PIPE_C && > - (plane_id == PLANE_PRIMARY || > - plane_id == PLANE_SPRITE0); > -} > - > static bool skl_plane_format_mod_supported(struct drm_plane *_plane, > u32 format, u64 modifier) > { > struct intel_plane *plane = to_intel_plane(_plane); > > - switch (modifier) { > - case DRM_FORMAT_MOD_LINEAR: > - case I915_FORMAT_MOD_X_TILED: > - case I915_FORMAT_MOD_Y_TILED: > - case I915_FORMAT_MOD_Yf_TILED: > - break; > - case I915_FORMAT_MOD_Y_TILED_CCS: > - case I915_FORMAT_MOD_Yf_TILED_CCS: > - if (!plane->has_ccs) > - return false; > - break; > - default: > + if (!intel_fb_plane_supports_modifier(plane, modifier)) > return false; > - } > > switch (format) { > case DRM_FORMAT_XRGB8888: > @@ -1965,45 +1892,13 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane, > } > } > > -static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv, > - enum plane_id plane_id) > -{ > - /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */ > - if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) || > - IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_D0)) > - return false; > - > - /* Wa_22011186057 */ > - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) > - return false; > - > - return plane_id < PLANE_SPRITE4; > -} > - > static bool gen12_plane_format_mod_supported(struct drm_plane *_plane, > u32 format, u64 modifier) > { > - struct drm_i915_private *dev_priv = to_i915(_plane->dev); > struct intel_plane *plane = to_intel_plane(_plane); > > - switch (modifier) { > - case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: > - if (!gen12_plane_supports_mc_ccs(dev_priv, plane->id)) > - return false; > - fallthrough; > - case DRM_FORMAT_MOD_LINEAR: > - case I915_FORMAT_MOD_X_TILED: > - case I915_FORMAT_MOD_Y_TILED: > - break; > - case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: > - case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: > - /* Wa_22011186057 */ > - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) > - return false; > - break; > - default: > + if (!intel_fb_plane_supports_modifier(plane, modifier)) > return false; > - } > > switch (format) { > case DRM_FORMAT_XRGB8888: > @@ -2051,18 +1946,6 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane, > } > } > > -static const u64 *gen12_get_plane_modifiers(struct drm_i915_private *dev_priv, > - enum plane_id plane_id) > -{ > - /* Wa_22011186057 */ > - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) > - return adlp_step_a_plane_format_modifiers; > - else if (gen12_plane_supports_mc_ccs(dev_priv, plane_id)) > - return gen12_plane_format_modifiers_mc_ccs; > - else > - return gen12_plane_format_modifiers_rc_ccs; > -} > - > static const struct drm_plane_funcs skl_plane_funcs = { > .update_plane = drm_atomic_helper_update_plane, > .disable_plane = drm_atomic_helper_disable_plane, > @@ -2103,6 +1986,39 @@ skl_plane_disable_flip_done(struct intel_plane *plane) > spin_unlock_irq(&i915->irq_lock); > } > > +static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915, > + enum pipe pipe, enum plane_id plane_id) > +{ > + /* Wa_22011186057 */ > + if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) > + return false; > + > + if (DISPLAY_VER(i915) >= 11) > + return true; > + > + if (IS_GEMINILAKE(i915)) > + return pipe != PIPE_C; > + > + return pipe != PIPE_C && > + (plane_id == PLANE_PRIMARY || > + plane_id == PLANE_SPRITE0); > +} > + > +static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915, > + enum plane_id plane_id) > +{ > + /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */ > + if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || > + IS_TGL_DISPLAY_STEP(i915, STEP_A0, STEP_D0)) > + return false; > + > + /* Wa_22011186057 */ > + if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) > + return false; > + > + return plane_id < PLANE_SPRITE4; > +} > + > struct intel_plane * > skl_universal_plane_create(struct drm_i915_private *dev_priv, > enum pipe pipe, enum plane_id plane_id) > @@ -2110,6 +2026,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, > const struct drm_plane_funcs *plane_funcs; > struct intel_plane *plane; > enum drm_plane_type plane_type; > + enum intel_plane_caps plane_caps; > unsigned int supported_rotations; > unsigned int supported_csc; > const u64 *modifiers; > @@ -2171,29 +2088,34 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, > formats = skl_get_plane_formats(dev_priv, pipe, > plane_id, &num_formats); > > - plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id); > - if (DISPLAY_VER(dev_priv) >= 12) { > - modifiers = gen12_get_plane_modifiers(dev_priv, plane_id); > + if (DISPLAY_VER(dev_priv) >= 12) > plane_funcs = &gen12_plane_funcs; > - } else { > - if (plane->has_ccs) > - modifiers = skl_plane_format_modifiers_ccs; > - else > - modifiers = skl_plane_format_modifiers_noccs; > + else > plane_funcs = &skl_plane_funcs; > - } > > if (plane_id == PLANE_PRIMARY) > plane_type = DRM_PLANE_TYPE_PRIMARY; > else > plane_type = DRM_PLANE_TYPE_OVERLAY; > > + plane_caps = PLANE_HAS_TILING; > + if (skl_plane_has_rc_ccs(dev_priv, pipe, plane_id)) > + plane_caps |= PLANE_HAS_CCS_RC; > + > + if (gen12_plane_has_mc_ccs(dev_priv, plane_id)) > + plane_caps |= PLANE_HAS_CCS_MC; > + > + modifiers = intel_fb_plane_get_modifiers(dev_priv, plane_caps); > + > ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, > 0, plane_funcs, > formats, num_formats, modifiers, > plane_type, > "plane %d%c", plane_id + 1, > pipe_name(pipe)); > + > + kfree(modifiers); > + > if (ret) > goto fail; -- Jani Nikula, Intel Open Source Graphics Center ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [PATCH v4 01/11] drm/i915: Add a table with a descriptor for all i915 modifiers 2021-10-21 10:14 ` Jani Nikula @ 2021-10-21 10:49 ` Imre Deak 0 siblings, 0 replies; 19+ messages in thread From: Imre Deak @ 2021-10-21 10:49 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx, Ville Syrjälä, Juha-Pekka Heikkila On Thu, Oct 21, 2021 at 01:14:59PM +0300, Jani Nikula wrote: > On Wed, 20 Oct 2021, Imre Deak <imre.deak@intel.com> wrote: > > Add a table describing all the framebuffer modifiers used by i915 at one > > place. This has the benefit of deduplicating the listing of supported > > modifiers for each platform and checking the support of these modifiers > > on a given plane. This also simplifies in a similar way getting some > > attribute for a modifier, for instance checking if the modifier is a > > CCS modifier type. > > > > While at it drop the cursor plane filtering from skl_plane_has_rc_ccs(), > > as the cursor plane is registered with DRM core elsewhere. > > > > v1: Unchanged. > > v2: > > - Keep the plane caps calculation in the plane code and pass an enum > > with these caps to intel_fb_get_modifiers(). (Ville) > > - Get the modifiers calling intel_fb_get_modifiers() in i9xx_plane.c as > > well. > > v3: > > - s/.id/.modifier/ (Ville) > > - Keep modifier_desc vs. plane_cap filter conditions consistent. (Ville) > > - Drop redundant cursor plane check from skl_plane_has_rc_ccs(). (Ville) > > - Use from, until display version fields in modifier_desc instead of a mask. (Jani) > > - Unexport struct intel_modifier_desc, separate its decl and init. (Jani) > > - Remove enum pipe, plane_id forward decls from intel_fb.h, which are > > not needed after v2. > > v4: > > - Reuse IS_DISPLAY_VER() instead of open-coding it. (Jani) > > - Preserve the current modifier order exposed to user space. (Ville) > > > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> > > Cc: Jani Nikula <jani.nikula@intel.com> > > Signed-off-by: Imre Deak <imre.deak@intel.com> > > Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> (v3) > > --- > > drivers/gpu/drm/i915/display/i9xx_plane.c | 30 +-- > > drivers/gpu/drm/i915/display/intel_cursor.c | 19 +- > > .../drm/i915/display/intel_display_types.h | 1 - > > drivers/gpu/drm/i915/display/intel_fb.c | 152 +++++++++++++++ > > drivers/gpu/drm/i915/display/intel_fb.h | 13 ++ > > drivers/gpu/drm/i915/display/intel_sprite.c | 35 +--- > > drivers/gpu/drm/i915/display/skl_scaler.c | 1 + > > .../drm/i915/display/skl_universal_plane.c | 178 +++++------------- > > 8 files changed, 245 insertions(+), 184 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c > > index b1439ba78f67b..a939accff7ee2 100644 > > --- a/drivers/gpu/drm/i915/display/i9xx_plane.c > > +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c > > @@ -60,22 +60,11 @@ static const u32 vlv_primary_formats[] = { > > DRM_FORMAT_XBGR16161616F, > > }; > > > > -static const u64 i9xx_format_modifiers[] = { > > - I915_FORMAT_MOD_X_TILED, > > - DRM_FORMAT_MOD_LINEAR, > > - DRM_FORMAT_MOD_INVALID > > -}; > > - > > static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane, > > u32 format, u64 modifier) > > { > > - switch (modifier) { > > - case DRM_FORMAT_MOD_LINEAR: > > - case I915_FORMAT_MOD_X_TILED: > > - break; > > - default: > > + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier)) > > return false; > > - } > > > > switch (format) { > > case DRM_FORMAT_C8: > > @@ -92,13 +81,8 @@ static bool i8xx_plane_format_mod_supported(struct drm_plane *_plane, > > static bool i965_plane_format_mod_supported(struct drm_plane *_plane, > > u32 format, u64 modifier) > > { > > - switch (modifier) { > > - case DRM_FORMAT_MOD_LINEAR: > > - case I915_FORMAT_MOD_X_TILED: > > - break; > > - default: > > + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier)) > > return false; > > - } > > > > switch (format) { > > case DRM_FORMAT_C8: > > @@ -768,6 +752,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) > > struct intel_plane *plane; > > const struct drm_plane_funcs *plane_funcs; > > unsigned int supported_rotations; > > + const u64 *modifiers; > > const u32 *formats; > > int num_formats; > > int ret, zpos; > > @@ -875,21 +860,26 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) > > plane->disable_flip_done = ilk_primary_disable_flip_done; > > } > > > > + modifiers = intel_fb_plane_get_modifiers(dev_priv, PLANE_HAS_TILING); > > + > > if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) > > ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, > > 0, plane_funcs, > > formats, num_formats, > > - i9xx_format_modifiers, > > + modifiers, > > DRM_PLANE_TYPE_PRIMARY, > > "primary %c", pipe_name(pipe)); > > else > > ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, > > 0, plane_funcs, > > formats, num_formats, > > - i9xx_format_modifiers, > > + modifiers, > > DRM_PLANE_TYPE_PRIMARY, > > "plane %c", > > plane_name(plane->i9xx_plane)); > > + > > + kfree(modifiers); > > + > > if (ret) > > goto fail; > > > > diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c > > index 11842f2126130..6b08d8bca5cd4 100644 > > --- a/drivers/gpu/drm/i915/display/intel_cursor.c > > +++ b/drivers/gpu/drm/i915/display/intel_cursor.c > > @@ -28,11 +28,6 @@ static const u32 intel_cursor_formats[] = { > > DRM_FORMAT_ARGB8888, > > }; > > > > -static const u64 cursor_format_modifiers[] = { > > - DRM_FORMAT_MOD_LINEAR, > > - DRM_FORMAT_MOD_INVALID > > -}; > > - > > static u32 intel_cursor_base(const struct intel_plane_state *plane_state) > > { > > struct drm_i915_private *dev_priv = > > @@ -605,8 +600,10 @@ static bool i9xx_cursor_get_hw_state(struct intel_plane *plane, > > static bool intel_cursor_format_mod_supported(struct drm_plane *_plane, > > u32 format, u64 modifier) > > { > > - return modifier == DRM_FORMAT_MOD_LINEAR && > > - format == DRM_FORMAT_ARGB8888; > > + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier)) > > + return false; > > + > > + return format == DRM_FORMAT_ARGB8888; > > } > > > > static int > > @@ -754,6 +751,7 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, > > { > > struct intel_plane *cursor; > > int ret, zpos; > > + u64 *modifiers; > > > > cursor = intel_plane_alloc(); > > if (IS_ERR(cursor)) > > @@ -784,13 +782,18 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, > > if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv)) > > cursor->cursor.size = ~0; > > > > + modifiers = intel_fb_plane_get_modifiers(dev_priv, PLANE_HAS_NO_CAPS); > > + > > ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base, > > 0, &intel_cursor_plane_funcs, > > intel_cursor_formats, > > ARRAY_SIZE(intel_cursor_formats), > > - cursor_format_modifiers, > > + modifiers, > > DRM_PLANE_TYPE_CURSOR, > > "cursor %c", pipe_name(pipe)); > > + > > + kfree(modifiers); > > + > > if (ret) > > goto fail; > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h > > index 1e42bf901263c..a4930a56bfa82 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > > @@ -1336,7 +1336,6 @@ struct intel_plane { > > enum plane_id id; > > enum pipe pipe; > > bool has_fbc; > > - bool has_ccs; > > bool need_async_flip_disable_wa; > > u32 frontbuffer_bit; > > > > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c > > index fa1f375e696bf..cf4748daf2acf 100644 > > --- a/drivers/gpu/drm/i915/display/intel_fb.c > > +++ b/drivers/gpu/drm/i915/display/intel_fb.c > > @@ -13,6 +13,158 @@ > > > > #define check_array_bounds(i915, a, i) drm_WARN_ON(&(i915)->drm, (i) >= ARRAY_SIZE(a)) > > > > +struct intel_modifier_desc { > > + u64 modifier; > > + struct { > > + u8 from; > > + u8 until; > > + } display_ver; > > +#define DISPLAY_VER_ALL { 0, -1 } > > + > > + u8 is_linear:1; > > + > > + struct { > > +#define INTEL_CCS_RC BIT(0) > > +#define INTEL_CCS_RC_CC BIT(1) > > +#define INTEL_CCS_MC BIT(2) > > + > > +#define INTEL_CCS_ANY (INTEL_CCS_RC | INTEL_CCS_RC_CC | INTEL_CCS_MC) > > + u8 type:3; > > + } ccs; > > +}; > > + > > +static const struct intel_modifier_desc intel_modifiers[] = { > > + { > > + .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, > > + .display_ver = { 12, 13 }, > > + > > + .ccs.type = INTEL_CCS_MC, > > + }, > > + { > > Argh, I meant to comment that "}, {" on one line is customary for stuff > like this to reduce the vertical space. > > If you need to do another spin for other reasons, please include this > change, otherwise it can be a follow-up. Ok, let's see if there are more comments. If not I can also change this while pushing the patches. > > BR, > Jani. > > > + .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, > > + .display_ver = { 12, 13 }, > > + > > + .ccs.type = INTEL_CCS_RC, > > + }, > > + { > > + .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC, > > + .display_ver = { 12, 13 }, > > + > > + .ccs.type = INTEL_CCS_RC_CC, > > + }, > > + { > > + .modifier = I915_FORMAT_MOD_Yf_TILED_CCS, > > + .display_ver = { 9, 11 }, > > + > > + .ccs.type = INTEL_CCS_RC, > > + }, > > + { > > + .modifier = I915_FORMAT_MOD_Y_TILED_CCS, > > + .display_ver = { 9, 11 }, > > + > > + .ccs.type = INTEL_CCS_RC, > > + }, > > + { > > + .modifier = I915_FORMAT_MOD_Yf_TILED, > > + .display_ver = { 9, 11 }, > > + }, > > + { > > + .modifier = I915_FORMAT_MOD_Y_TILED, > > + .display_ver = { 9, 13 }, > > + }, > > + { > > + .modifier = I915_FORMAT_MOD_X_TILED, > > + .display_ver = DISPLAY_VER_ALL, > > + }, > > + { > > + .modifier = DRM_FORMAT_MOD_LINEAR, > > + .display_ver = DISPLAY_VER_ALL, > > + > > + .is_linear = true, > > + }, > > +}; > > + > > +static bool is_ccs_type_modifier(const struct intel_modifier_desc *md, u8 ccs_type) > > +{ > > + return md->ccs.type & ccs_type; > > +} > > + > > +static bool plane_has_modifier(struct drm_i915_private *i915, > > + enum intel_plane_caps plane_caps, > > + const struct intel_modifier_desc *md) > > +{ > > + if (!IS_DISPLAY_VER(i915, md->display_ver.from, md->display_ver.until)) > > + return false; > > + > > + if (!md->is_linear && > > + !(plane_caps & PLANE_HAS_TILING)) > > + return false; > > + > > + if (is_ccs_type_modifier(md, INTEL_CCS_RC | INTEL_CCS_RC_CC) && > > + !(plane_caps & PLANE_HAS_CCS_RC)) > > + return false; > > + > > + if (is_ccs_type_modifier(md, INTEL_CCS_MC) && > > + !(plane_caps & PLANE_HAS_CCS_MC)) > > + return false; > > + > > + return true; > > +} > > + > > +/** > > + * intel_fb_plane_get_modifiers: Get the modifiers for the given platform and plane capabilities > > + * @i915: i915 device instance > > + * @plane_caps: capabilities for the plane the modifiers are queried for > > + * > > + * Returns: > > + * Returns the list of modifiers allowed by the @i915 platform and @plane_caps. > > + * The caller must free the returned buffer. > > + */ > > +u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915, > > + enum intel_plane_caps plane_caps) > > +{ > > + u64 *list, *p; > > + int count = 1; /* +1 for invalid modifier terminator */ > > + int i; > > + > > + for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) { > > + if (plane_has_modifier(i915, plane_caps, &intel_modifiers[i])) > > + count++; > > + } > > + > > + list = kmalloc_array(count, sizeof(*list), GFP_KERNEL); > > + if (drm_WARN_ON(&i915->drm, !list)) > > + return NULL; > > + > > + p = list; > > + for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) { > > + if (plane_has_modifier(i915, plane_caps, &intel_modifiers[i])) > > + *p++ = intel_modifiers[i].modifier; > > + } > > + *p++ = DRM_FORMAT_MOD_INVALID; > > + > > + return list; > > +} > > + > > +/** > > + * intel_fb_plane_supports_modifier: Determine if a modifier is supported by the given plane > > + * @plane: Plane to check the modifier support for > > + * @modifier: The modifier to check the support for > > + * > > + * Returns: > > + * %true if the @modifier is supported on @plane. > > + */ > > +bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier) > > +{ > > + int i; > > + > > + for (i = 0; i < plane->base.modifier_count; i++) > > + if (plane->base.modifiers[i] == modifier) > > + return true; > > + > > + return false; > > +} > > + > > bool is_ccs_plane(const struct drm_framebuffer *fb, int plane) > > { > > if (!is_ccs_modifier(fb->modifier)) > > diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h > > index 1cbdd84502bdd..0f77e81e69d29 100644 > > --- a/drivers/gpu/drm/i915/display/intel_fb.h > > +++ b/drivers/gpu/drm/i915/display/intel_fb.h > > @@ -6,6 +6,7 @@ > > #ifndef __INTEL_FB_H__ > > #define __INTEL_FB_H__ > > > > +#include <linux/bits.h> > > #include <linux/types.h> > > > > struct drm_device; > > @@ -16,13 +17,25 @@ struct drm_i915_private; > > struct drm_mode_fb_cmd2; > > struct intel_fb_view; > > struct intel_framebuffer; > > +struct intel_plane; > > struct intel_plane_state; > > > > +enum intel_plane_caps { > > + PLANE_HAS_NO_CAPS = 0, > > + PLANE_HAS_TILING = BIT(0), > > + PLANE_HAS_CCS_RC = BIT(1), > > + PLANE_HAS_CCS_MC = BIT(2), > > +}; > > + > > bool is_ccs_plane(const struct drm_framebuffer *fb, int plane); > > bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane); > > bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane); > > bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane); > > > > +u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915, > > + enum intel_plane_caps plane_caps); > > +bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier); > > + > > bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane); > > > > int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane); > > diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c > > index 08116f41da26a..2f4f47ab9da03 100644 > > --- a/drivers/gpu/drm/i915/display/intel_sprite.c > > +++ b/drivers/gpu/drm/i915/display/intel_sprite.c > > @@ -45,6 +45,7 @@ > > #include "intel_atomic_plane.h" > > #include "intel_de.h" > > #include "intel_display_types.h" > > +#include "intel_fb.h" > > #include "intel_frontbuffer.h" > > #include "intel_sprite.h" > > #include "i9xx_plane.h" > > @@ -1575,12 +1576,6 @@ static const u32 g4x_plane_formats[] = { > > DRM_FORMAT_VYUY, > > }; > > > > -static const u64 i9xx_plane_format_modifiers[] = { > > - I915_FORMAT_MOD_X_TILED, > > - DRM_FORMAT_MOD_LINEAR, > > - DRM_FORMAT_MOD_INVALID > > -}; > > - > > static const u32 snb_plane_formats[] = { > > DRM_FORMAT_XRGB8888, > > DRM_FORMAT_XBGR8888, > > @@ -1629,13 +1624,8 @@ static const u32 chv_pipe_b_sprite_formats[] = { > > static bool g4x_sprite_format_mod_supported(struct drm_plane *_plane, > > u32 format, u64 modifier) > > { > > - switch (modifier) { > > - case DRM_FORMAT_MOD_LINEAR: > > - case I915_FORMAT_MOD_X_TILED: > > - break; > > - default: > > + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier)) > > return false; > > - } > > > > switch (format) { > > case DRM_FORMAT_XRGB8888: > > @@ -1655,13 +1645,8 @@ static bool g4x_sprite_format_mod_supported(struct drm_plane *_plane, > > static bool snb_sprite_format_mod_supported(struct drm_plane *_plane, > > u32 format, u64 modifier) > > { > > - switch (modifier) { > > - case DRM_FORMAT_MOD_LINEAR: > > - case I915_FORMAT_MOD_X_TILED: > > - break; > > - default: > > + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier)) > > return false; > > - } > > > > switch (format) { > > case DRM_FORMAT_XRGB8888: > > @@ -1686,13 +1671,8 @@ static bool snb_sprite_format_mod_supported(struct drm_plane *_plane, > > static bool vlv_sprite_format_mod_supported(struct drm_plane *_plane, > > u32 format, u64 modifier) > > { > > - switch (modifier) { > > - case DRM_FORMAT_MOD_LINEAR: > > - case I915_FORMAT_MOD_X_TILED: > > - break; > > - default: > > + if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier)) > > return false; > > - } > > > > switch (format) { > > case DRM_FORMAT_C8: > > @@ -1776,7 +1756,6 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, > > formats = vlv_plane_formats; > > num_formats = ARRAY_SIZE(vlv_plane_formats); > > } > > - modifiers = i9xx_plane_format_modifiers; > > > > plane_funcs = &vlv_sprite_funcs; > > } else if (DISPLAY_VER(dev_priv) >= 7) { > > @@ -1795,7 +1774,6 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, > > > > formats = snb_plane_formats; > > num_formats = ARRAY_SIZE(snb_plane_formats); > > - modifiers = i9xx_plane_format_modifiers; > > > > plane_funcs = &snb_sprite_funcs; > > } else { > > @@ -1806,7 +1784,6 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, > > plane->max_stride = g4x_sprite_max_stride; > > plane->min_cdclk = g4x_sprite_min_cdclk; > > > > - modifiers = i9xx_plane_format_modifiers; > > if (IS_SANDYBRIDGE(dev_priv)) { > > formats = snb_plane_formats; > > num_formats = ARRAY_SIZE(snb_plane_formats); > > @@ -1833,11 +1810,15 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, > > plane->id = PLANE_SPRITE0 + sprite; > > plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id); > > > > + modifiers = intel_fb_plane_get_modifiers(dev_priv, PLANE_HAS_TILING); > > + > > ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, > > 0, plane_funcs, > > formats, num_formats, modifiers, > > DRM_PLANE_TYPE_OVERLAY, > > "sprite %c", sprite_name(pipe, sprite)); > > + kfree(modifiers); > > + > > if (ret) > > goto fail; > > > > diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c > > index 37eabeff8197f..c2e94118566b6 100644 > > --- a/drivers/gpu/drm/i915/display/skl_scaler.c > > +++ b/drivers/gpu/drm/i915/display/skl_scaler.c > > @@ -4,6 +4,7 @@ > > */ > > #include "intel_de.h" > > #include "intel_display_types.h" > > +#include "intel_fb.h" > > #include "skl_scaler.h" > > #include "skl_universal_plane.h" > > > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c > > index 7444b88829ea7..7ee2114e420b7 100644 > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c > > @@ -163,50 +163,6 @@ static const u32 icl_hdr_plane_formats[] = { > > DRM_FORMAT_XVYU16161616, > > }; > > > > -static const u64 skl_plane_format_modifiers_noccs[] = { > > - I915_FORMAT_MOD_Yf_TILED, > > - I915_FORMAT_MOD_Y_TILED, > > - I915_FORMAT_MOD_X_TILED, > > - DRM_FORMAT_MOD_LINEAR, > > - DRM_FORMAT_MOD_INVALID > > -}; > > - > > -static const u64 skl_plane_format_modifiers_ccs[] = { > > - I915_FORMAT_MOD_Yf_TILED_CCS, > > - I915_FORMAT_MOD_Y_TILED_CCS, > > - I915_FORMAT_MOD_Yf_TILED, > > - I915_FORMAT_MOD_Y_TILED, > > - I915_FORMAT_MOD_X_TILED, > > - DRM_FORMAT_MOD_LINEAR, > > - DRM_FORMAT_MOD_INVALID > > -}; > > - > > -static const u64 gen12_plane_format_modifiers_mc_ccs[] = { > > - I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, > > - I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, > > - I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC, > > - I915_FORMAT_MOD_Y_TILED, > > - I915_FORMAT_MOD_X_TILED, > > - DRM_FORMAT_MOD_LINEAR, > > - DRM_FORMAT_MOD_INVALID > > -}; > > - > > -static const u64 gen12_plane_format_modifiers_rc_ccs[] = { > > - I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, > > - I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC, > > - I915_FORMAT_MOD_Y_TILED, > > - I915_FORMAT_MOD_X_TILED, > > - DRM_FORMAT_MOD_LINEAR, > > - DRM_FORMAT_MOD_INVALID > > -}; > > - > > -static const u64 adlp_step_a_plane_format_modifiers[] = { > > - I915_FORMAT_MOD_Y_TILED, > > - I915_FORMAT_MOD_X_TILED, > > - DRM_FORMAT_MOD_LINEAR, > > - DRM_FORMAT_MOD_INVALID > > -}; > > - > > int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) > > { > > switch (format) { > > @@ -1882,42 +1838,13 @@ static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv, > > } > > } > > > > -static bool skl_plane_has_ccs(struct drm_i915_private *dev_priv, > > - enum pipe pipe, enum plane_id plane_id) > > -{ > > - if (plane_id == PLANE_CURSOR) > > - return false; > > - > > - if (DISPLAY_VER(dev_priv) >= 11) > > - return true; > > - > > - if (IS_GEMINILAKE(dev_priv)) > > - return pipe != PIPE_C; > > - > > - return pipe != PIPE_C && > > - (plane_id == PLANE_PRIMARY || > > - plane_id == PLANE_SPRITE0); > > -} > > - > > static bool skl_plane_format_mod_supported(struct drm_plane *_plane, > > u32 format, u64 modifier) > > { > > struct intel_plane *plane = to_intel_plane(_plane); > > > > - switch (modifier) { > > - case DRM_FORMAT_MOD_LINEAR: > > - case I915_FORMAT_MOD_X_TILED: > > - case I915_FORMAT_MOD_Y_TILED: > > - case I915_FORMAT_MOD_Yf_TILED: > > - break; > > - case I915_FORMAT_MOD_Y_TILED_CCS: > > - case I915_FORMAT_MOD_Yf_TILED_CCS: > > - if (!plane->has_ccs) > > - return false; > > - break; > > - default: > > + if (!intel_fb_plane_supports_modifier(plane, modifier)) > > return false; > > - } > > > > switch (format) { > > case DRM_FORMAT_XRGB8888: > > @@ -1965,45 +1892,13 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane, > > } > > } > > > > -static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv, > > - enum plane_id plane_id) > > -{ > > - /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */ > > - if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv) || > > - IS_TGL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_D0)) > > - return false; > > - > > - /* Wa_22011186057 */ > > - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) > > - return false; > > - > > - return plane_id < PLANE_SPRITE4; > > -} > > - > > static bool gen12_plane_format_mod_supported(struct drm_plane *_plane, > > u32 format, u64 modifier) > > { > > - struct drm_i915_private *dev_priv = to_i915(_plane->dev); > > struct intel_plane *plane = to_intel_plane(_plane); > > > > - switch (modifier) { > > - case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: > > - if (!gen12_plane_supports_mc_ccs(dev_priv, plane->id)) > > - return false; > > - fallthrough; > > - case DRM_FORMAT_MOD_LINEAR: > > - case I915_FORMAT_MOD_X_TILED: > > - case I915_FORMAT_MOD_Y_TILED: > > - break; > > - case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: > > - case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: > > - /* Wa_22011186057 */ > > - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) > > - return false; > > - break; > > - default: > > + if (!intel_fb_plane_supports_modifier(plane, modifier)) > > return false; > > - } > > > > switch (format) { > > case DRM_FORMAT_XRGB8888: > > @@ -2051,18 +1946,6 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane, > > } > > } > > > > -static const u64 *gen12_get_plane_modifiers(struct drm_i915_private *dev_priv, > > - enum plane_id plane_id) > > -{ > > - /* Wa_22011186057 */ > > - if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) > > - return adlp_step_a_plane_format_modifiers; > > - else if (gen12_plane_supports_mc_ccs(dev_priv, plane_id)) > > - return gen12_plane_format_modifiers_mc_ccs; > > - else > > - return gen12_plane_format_modifiers_rc_ccs; > > -} > > - > > static const struct drm_plane_funcs skl_plane_funcs = { > > .update_plane = drm_atomic_helper_update_plane, > > .disable_plane = drm_atomic_helper_disable_plane, > > @@ -2103,6 +1986,39 @@ skl_plane_disable_flip_done(struct intel_plane *plane) > > spin_unlock_irq(&i915->irq_lock); > > } > > > > +static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915, > > + enum pipe pipe, enum plane_id plane_id) > > +{ > > + /* Wa_22011186057 */ > > + if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) > > + return false; > > + > > + if (DISPLAY_VER(i915) >= 11) > > + return true; > > + > > + if (IS_GEMINILAKE(i915)) > > + return pipe != PIPE_C; > > + > > + return pipe != PIPE_C && > > + (plane_id == PLANE_PRIMARY || > > + plane_id == PLANE_SPRITE0); > > +} > > + > > +static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915, > > + enum plane_id plane_id) > > +{ > > + /* Wa_14010477008:tgl[a0..c0],rkl[all],dg1[all] */ > > + if (IS_DG1(i915) || IS_ROCKETLAKE(i915) || > > + IS_TGL_DISPLAY_STEP(i915, STEP_A0, STEP_D0)) > > + return false; > > + > > + /* Wa_22011186057 */ > > + if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) > > + return false; > > + > > + return plane_id < PLANE_SPRITE4; > > +} > > + > > struct intel_plane * > > skl_universal_plane_create(struct drm_i915_private *dev_priv, > > enum pipe pipe, enum plane_id plane_id) > > @@ -2110,6 +2026,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, > > const struct drm_plane_funcs *plane_funcs; > > struct intel_plane *plane; > > enum drm_plane_type plane_type; > > + enum intel_plane_caps plane_caps; > > unsigned int supported_rotations; > > unsigned int supported_csc; > > const u64 *modifiers; > > @@ -2171,29 +2088,34 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, > > formats = skl_get_plane_formats(dev_priv, pipe, > > plane_id, &num_formats); > > > > - plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id); > > - if (DISPLAY_VER(dev_priv) >= 12) { > > - modifiers = gen12_get_plane_modifiers(dev_priv, plane_id); > > + if (DISPLAY_VER(dev_priv) >= 12) > > plane_funcs = &gen12_plane_funcs; > > - } else { > > - if (plane->has_ccs) > > - modifiers = skl_plane_format_modifiers_ccs; > > - else > > - modifiers = skl_plane_format_modifiers_noccs; > > + else > > plane_funcs = &skl_plane_funcs; > > - } > > > > if (plane_id == PLANE_PRIMARY) > > plane_type = DRM_PLANE_TYPE_PRIMARY; > > else > > plane_type = DRM_PLANE_TYPE_OVERLAY; > > > > + plane_caps = PLANE_HAS_TILING; > > + if (skl_plane_has_rc_ccs(dev_priv, pipe, plane_id)) > > + plane_caps |= PLANE_HAS_CCS_RC; > > + > > + if (gen12_plane_has_mc_ccs(dev_priv, plane_id)) > > + plane_caps |= PLANE_HAS_CCS_MC; > > + > > + modifiers = intel_fb_plane_get_modifiers(dev_priv, plane_caps); > > + > > ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, > > 0, plane_funcs, > > formats, num_formats, modifiers, > > plane_type, > > "plane %d%c", plane_id + 1, > > pipe_name(pipe)); > > + > > + kfree(modifiers); > > + > > if (ret) > > goto fail; > > -- > Jani Nikula, Intel Open Source Graphics Center ^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH v4 02/11] drm/i915: Move intel_get_format_info() to intel_fb.c 2021-10-20 19:51 [Intel-gfx] [PATCH v4 00/11] drm/i915: Simplify handling of modifiers Imre Deak 2021-10-20 19:51 ` [Intel-gfx] [PATCH v4 01/11] drm/i915: Add a table with a descriptor for all i915 modifiers Imre Deak @ 2021-10-20 19:51 ` Imre Deak 2021-10-20 19:51 ` [Intel-gfx] [PATCH v4 03/11] drm/i915: Add tiling attribute to the modifier descriptor Imre Deak ` (12 subsequent siblings) 14 siblings, 0 replies; 19+ messages in thread From: Imre Deak @ 2021-10-20 19:51 UTC (permalink / raw) To: intel-gfx; +Cc: Juha-Pekka Heikkila, Ville Syrjälä Move the function retrieving the format override information for a given format/modifier to intel_fb.c. We can store a pointer to the format list in each modifier's descriptor instead of the corresponding switch/case logic, avoiding the listing of the modifiers twice. v1: Unchanged. v2: Handle invalid modifiers in intel_fb_get_format_info() passed from userspace. (CI/igt_kms_addfb_basic/addfb25-bad-modifier) v3: Move lookup_modifier() to the next patch, where it's first used. Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> --- drivers/gpu/drm/i915/display/intel_display.c | 132 +--------------- drivers/gpu/drm/i915/display/intel_fb.c | 153 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_fb.h | 3 + 3 files changed, 157 insertions(+), 131 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 79a7552af7b5e..86333c0cd7937 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -669,136 +669,6 @@ void intel_add_fb_offsets(int *x, int *y, *y += state->view.color_plane[color_plane].y; } -/* - * From the Sky Lake PRM: - * "The Color Control Surface (CCS) contains the compression status of - * the cache-line pairs. The compression state of the cache-line pair - * is specified by 2 bits in the CCS. Each CCS cache-line represents - * an area on the main surface of 16 x16 sets of 128 byte Y-tiled - * cache-line-pairs. CCS is always Y tiled." - * - * Since cache line pairs refers to horizontally adjacent cache lines, - * each cache line in the CCS corresponds to an area of 32x16 cache - * lines on the main surface. Since each pixel is 4 bytes, this gives - * us a ratio of one byte in the CCS for each 8x16 pixels in the - * main surface. - */ -static const struct drm_format_info skl_ccs_formats[] = { - { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, - .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, - { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, - .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, - { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, - .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, }, - { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, - .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, }, -}; - -/* - * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the - * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles - * in the main surface. With 4 byte pixels and each Y-tile having dimensions of - * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in - * the main surface. - */ -static const struct drm_format_info gen12_ccs_formats[] = { - { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, - .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, - .hsub = 1, .vsub = 1, }, - { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, - .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, - .hsub = 1, .vsub = 1, }, - { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, - .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, - .hsub = 1, .vsub = 1, .has_alpha = true }, - { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, - .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, - .hsub = 1, .vsub = 1, .has_alpha = true }, - { .format = DRM_FORMAT_YUYV, .num_planes = 2, - .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, - .hsub = 2, .vsub = 1, .is_yuv = true }, - { .format = DRM_FORMAT_YVYU, .num_planes = 2, - .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, - .hsub = 2, .vsub = 1, .is_yuv = true }, - { .format = DRM_FORMAT_UYVY, .num_planes = 2, - .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, - .hsub = 2, .vsub = 1, .is_yuv = true }, - { .format = DRM_FORMAT_VYUY, .num_planes = 2, - .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, - .hsub = 2, .vsub = 1, .is_yuv = true }, - { .format = DRM_FORMAT_XYUV8888, .num_planes = 2, - .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, - .hsub = 1, .vsub = 1, .is_yuv = true }, - { .format = DRM_FORMAT_NV12, .num_planes = 4, - .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 }, - .hsub = 2, .vsub = 2, .is_yuv = true }, - { .format = DRM_FORMAT_P010, .num_planes = 4, - .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 }, - .hsub = 2, .vsub = 2, .is_yuv = true }, - { .format = DRM_FORMAT_P012, .num_planes = 4, - .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 }, - .hsub = 2, .vsub = 2, .is_yuv = true }, - { .format = DRM_FORMAT_P016, .num_planes = 4, - .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 }, - .hsub = 2, .vsub = 2, .is_yuv = true }, -}; - -/* - * Same as gen12_ccs_formats[] above, but with additional surface used - * to pass Clear Color information in plane 2 with 64 bits of data. - */ -static const struct drm_format_info gen12_ccs_cc_formats[] = { - { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3, - .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 }, - .hsub = 1, .vsub = 1, }, - { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3, - .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 }, - .hsub = 1, .vsub = 1, }, - { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3, - .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 }, - .hsub = 1, .vsub = 1, .has_alpha = true }, - { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3, - .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 }, - .hsub = 1, .vsub = 1, .has_alpha = true }, -}; - -static const struct drm_format_info * -lookup_format_info(const struct drm_format_info formats[], - int num_formats, u32 format) -{ - int i; - - for (i = 0; i < num_formats; i++) { - if (formats[i].format == format) - return &formats[i]; - } - - return NULL; -} - -static const struct drm_format_info * -intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd) -{ - switch (cmd->modifier[0]) { - case I915_FORMAT_MOD_Y_TILED_CCS: - case I915_FORMAT_MOD_Yf_TILED_CCS: - return lookup_format_info(skl_ccs_formats, - ARRAY_SIZE(skl_ccs_formats), - cmd->pixel_format); - case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: - case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: - return lookup_format_info(gen12_ccs_formats, - ARRAY_SIZE(gen12_ccs_formats), - cmd->pixel_format); - case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: - return lookup_format_info(gen12_ccs_cc_formats, - ARRAY_SIZE(gen12_ccs_cc_formats), - cmd->pixel_format); - default: - return NULL; - } -} - u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, u32 pixel_format, u64 modifier) { @@ -9538,7 +9408,7 @@ intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, static const struct drm_mode_config_funcs intel_mode_funcs = { .fb_create = intel_user_framebuffer_create, - .get_format_info = intel_get_format_info, + .get_format_info = intel_fb_get_format_info, .output_poll_changed = intel_fbdev_output_poll_changed, .mode_valid = intel_mode_valid, .atomic_check = intel_atomic_check, diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index cf4748daf2acf..539c23c1c9990 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -13,6 +13,99 @@ #define check_array_bounds(i915, a, i) drm_WARN_ON(&(i915)->drm, (i) >= ARRAY_SIZE(a)) +/* + * From the Sky Lake PRM: + * "The Color Control Surface (CCS) contains the compression status of + * the cache-line pairs. The compression state of the cache-line pair + * is specified by 2 bits in the CCS. Each CCS cache-line represents + * an area on the main surface of 16 x16 sets of 128 byte Y-tiled + * cache-line-pairs. CCS is always Y tiled." + * + * Since cache line pairs refers to horizontally adjacent cache lines, + * each cache line in the CCS corresponds to an area of 32x16 cache + * lines on the main surface. Since each pixel is 4 bytes, this gives + * us a ratio of one byte in the CCS for each 8x16 pixels in the + * main surface. + */ +static const struct drm_format_info skl_ccs_formats[] = { + { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, + .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, + { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, + .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, + { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, + .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, }, + { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, + .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, .has_alpha = true, }, +}; + +/* + * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the + * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles + * in the main surface. With 4 byte pixels and each Y-tile having dimensions of + * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in + * the main surface. + */ +static const struct drm_format_info gen12_ccs_formats[] = { + { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, + .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, + .hsub = 1, .vsub = 1, }, + { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, + .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, + .hsub = 1, .vsub = 1, }, + { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, + .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, + .hsub = 1, .vsub = 1, .has_alpha = true }, + { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, + .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, + .hsub = 1, .vsub = 1, .has_alpha = true }, + { .format = DRM_FORMAT_YUYV, .num_planes = 2, + .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, + .hsub = 2, .vsub = 1, .is_yuv = true }, + { .format = DRM_FORMAT_YVYU, .num_planes = 2, + .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, + .hsub = 2, .vsub = 1, .is_yuv = true }, + { .format = DRM_FORMAT_UYVY, .num_planes = 2, + .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, + .hsub = 2, .vsub = 1, .is_yuv = true }, + { .format = DRM_FORMAT_VYUY, .num_planes = 2, + .char_per_block = { 2, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, + .hsub = 2, .vsub = 1, .is_yuv = true }, + { .format = DRM_FORMAT_XYUV8888, .num_planes = 2, + .char_per_block = { 4, 1 }, .block_w = { 1, 2 }, .block_h = { 1, 1 }, + .hsub = 1, .vsub = 1, .is_yuv = true }, + { .format = DRM_FORMAT_NV12, .num_planes = 4, + .char_per_block = { 1, 2, 1, 1 }, .block_w = { 1, 1, 4, 4 }, .block_h = { 1, 1, 1, 1 }, + .hsub = 2, .vsub = 2, .is_yuv = true }, + { .format = DRM_FORMAT_P010, .num_planes = 4, + .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 }, + .hsub = 2, .vsub = 2, .is_yuv = true }, + { .format = DRM_FORMAT_P012, .num_planes = 4, + .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 }, + .hsub = 2, .vsub = 2, .is_yuv = true }, + { .format = DRM_FORMAT_P016, .num_planes = 4, + .char_per_block = { 2, 4, 1, 1 }, .block_w = { 1, 1, 2, 2 }, .block_h = { 1, 1, 1, 1 }, + .hsub = 2, .vsub = 2, .is_yuv = true }, +}; + +/* + * Same as gen12_ccs_formats[] above, but with additional surface used + * to pass Clear Color information in plane 2 with 64 bits of data. + */ +static const struct drm_format_info gen12_ccs_cc_formats[] = { + { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 3, + .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 }, + .hsub = 1, .vsub = 1, }, + { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 3, + .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 }, + .hsub = 1, .vsub = 1, }, + { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 3, + .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 }, + .hsub = 1, .vsub = 1, .has_alpha = true }, + { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 3, + .char_per_block = { 4, 1, 0 }, .block_w = { 1, 2, 2 }, .block_h = { 1, 1, 1 }, + .hsub = 1, .vsub = 1, .has_alpha = true }, +}; + struct intel_modifier_desc { u64 modifier; struct { @@ -21,6 +114,12 @@ struct intel_modifier_desc { } display_ver; #define DISPLAY_VER_ALL { 0, -1 } + const struct drm_format_info *formats; + int format_count; +#define FORMAT_OVERRIDE(format_list) \ + .formats = format_list, \ + .format_count = ARRAY_SIZE(format_list) + u8 is_linear:1; struct { @@ -39,30 +138,40 @@ static const struct intel_modifier_desc intel_modifiers[] = { .display_ver = { 12, 13 }, .ccs.type = INTEL_CCS_MC, + + FORMAT_OVERRIDE(gen12_ccs_formats), }, { .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, .display_ver = { 12, 13 }, .ccs.type = INTEL_CCS_RC, + + FORMAT_OVERRIDE(gen12_ccs_formats), }, { .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC, .display_ver = { 12, 13 }, .ccs.type = INTEL_CCS_RC_CC, + + FORMAT_OVERRIDE(gen12_ccs_cc_formats), }, { .modifier = I915_FORMAT_MOD_Yf_TILED_CCS, .display_ver = { 9, 11 }, .ccs.type = INTEL_CCS_RC, + + FORMAT_OVERRIDE(skl_ccs_formats), }, { .modifier = I915_FORMAT_MOD_Y_TILED_CCS, .display_ver = { 9, 11 }, .ccs.type = INTEL_CCS_RC, + + FORMAT_OVERRIDE(skl_ccs_formats), }, { .modifier = I915_FORMAT_MOD_Yf_TILED, @@ -84,6 +193,50 @@ static const struct intel_modifier_desc intel_modifiers[] = { }, }; +static const struct intel_modifier_desc *lookup_modifier_or_null(u64 modifier) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(intel_modifiers); i++) + if (intel_modifiers[i].modifier == modifier) + return &intel_modifiers[i]; + + return NULL; +} + +static const struct drm_format_info * +lookup_format_info(const struct drm_format_info formats[], + int num_formats, u32 format) +{ + int i; + + for (i = 0; i < num_formats; i++) { + if (formats[i].format == format) + return &formats[i]; + } + + return NULL; +} + +/** + * intel_fb_get_format_info: Get a modifier specific format information + * @cmd: FB add command structure + * + * Returns: + * Returns the format information for @cmd->pixel_format specific to @cmd->modifier[0], + * or %NULL if the modifier doesn't override the format. + */ +const struct drm_format_info * +intel_fb_get_format_info(const struct drm_mode_fb_cmd2 *cmd) +{ + const struct intel_modifier_desc *md = lookup_modifier_or_null(cmd->modifier[0]); + + if (!md || !md->formats) + return NULL; + + return lookup_format_info(md->formats, md->format_count, cmd->pixel_format); +} + static bool is_ccs_type_modifier(const struct intel_modifier_desc *md, u8 ccs_type) { return md->ccs.type & ccs_type; diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h index 0f77e81e69d29..97b31c3a29825 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.h +++ b/drivers/gpu/drm/i915/display/intel_fb.h @@ -36,6 +36,9 @@ u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915, enum intel_plane_caps plane_caps); bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier); +const struct drm_format_info * +intel_fb_get_format_info(const struct drm_mode_fb_cmd2 *cmd); + bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane); int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane); -- 2.27.0 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH v4 03/11] drm/i915: Add tiling attribute to the modifier descriptor 2021-10-20 19:51 [Intel-gfx] [PATCH v4 00/11] drm/i915: Simplify handling of modifiers Imre Deak 2021-10-20 19:51 ` [Intel-gfx] [PATCH v4 01/11] drm/i915: Add a table with a descriptor for all i915 modifiers Imre Deak 2021-10-20 19:51 ` [Intel-gfx] [PATCH v4 02/11] drm/i915: Move intel_get_format_info() to intel_fb.c Imre Deak @ 2021-10-20 19:51 ` Imre Deak 2021-10-20 19:51 ` [Intel-gfx] [PATCH v4 04/11] drm/i915: Simplify the modifier check for interlaced scanout support Imre Deak ` (11 subsequent siblings) 14 siblings, 0 replies; 19+ messages in thread From: Imre Deak @ 2021-10-20 19:51 UTC (permalink / raw) To: intel-gfx; +Cc: Juha-Pekka Heikkila, Ville Syrjälä Add a tiling atttribute to the modifier descriptor, which let's us get the tiling without listing the modifiers twice. v1-v2: Unchanged. v3: - Initialize .tiling to I915_TILING_NONE explicitly (Ville) - Move from previous patch lookup_modifier() to here, where it's first used. Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> --- drivers/gpu/drm/i915/display/intel_fb.c | 31 +++++++++++++++---------- 1 file changed, 19 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index 539c23c1c9990..8982cfa7205fe 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -120,6 +120,7 @@ struct intel_modifier_desc { .formats = format_list, \ .format_count = ARRAY_SIZE(format_list) + u8 tiling; u8 is_linear:1; struct { @@ -136,6 +137,7 @@ static const struct intel_modifier_desc intel_modifiers[] = { { .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, .display_ver = { 12, 13 }, + .tiling = I915_TILING_Y, .ccs.type = INTEL_CCS_MC, @@ -144,6 +146,7 @@ static const struct intel_modifier_desc intel_modifiers[] = { { .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, .display_ver = { 12, 13 }, + .tiling = I915_TILING_Y, .ccs.type = INTEL_CCS_RC, @@ -152,6 +155,7 @@ static const struct intel_modifier_desc intel_modifiers[] = { { .modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC, .display_ver = { 12, 13 }, + .tiling = I915_TILING_Y, .ccs.type = INTEL_CCS_RC_CC, @@ -168,6 +172,7 @@ static const struct intel_modifier_desc intel_modifiers[] = { { .modifier = I915_FORMAT_MOD_Y_TILED_CCS, .display_ver = { 9, 11 }, + .tiling = I915_TILING_Y, .ccs.type = INTEL_CCS_RC, @@ -180,14 +185,17 @@ static const struct intel_modifier_desc intel_modifiers[] = { { .modifier = I915_FORMAT_MOD_Y_TILED, .display_ver = { 9, 13 }, + .tiling = I915_TILING_Y, }, { .modifier = I915_FORMAT_MOD_X_TILED, .display_ver = DISPLAY_VER_ALL, + .tiling = I915_TILING_X, }, { .modifier = DRM_FORMAT_MOD_LINEAR, .display_ver = DISPLAY_VER_ALL, + .tiling = I915_TILING_NONE, .is_linear = true, }, @@ -204,6 +212,16 @@ static const struct intel_modifier_desc *lookup_modifier_or_null(u64 modifier) return NULL; } +static const struct intel_modifier_desc *lookup_modifier(u64 modifier) +{ + const struct intel_modifier_desc *md = lookup_modifier_or_null(modifier); + + if (WARN_ON(!md)) + return &intel_modifiers[0]; + + return md; +} + static const struct drm_format_info * lookup_format_info(const struct drm_format_info formats[], int num_formats, u32 format) @@ -528,18 +546,7 @@ intel_fb_align_height(const struct drm_framebuffer *fb, static unsigned int intel_fb_modifier_to_tiling(u64 fb_modifier) { - switch (fb_modifier) { - case I915_FORMAT_MOD_X_TILED: - return I915_TILING_X; - case I915_FORMAT_MOD_Y_TILED: - case I915_FORMAT_MOD_Y_TILED_CCS: - case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: - case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: - case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: - return I915_TILING_Y; - default: - return I915_TILING_NONE; - } + return lookup_modifier(fb_modifier)->tiling; } unsigned int intel_cursor_alignment(const struct drm_i915_private *i915) -- 2.27.0 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH v4 04/11] drm/i915: Simplify the modifier check for interlaced scanout support 2021-10-20 19:51 [Intel-gfx] [PATCH v4 00/11] drm/i915: Simplify handling of modifiers Imre Deak ` (2 preceding siblings ...) 2021-10-20 19:51 ` [Intel-gfx] [PATCH v4 03/11] drm/i915: Add tiling attribute to the modifier descriptor Imre Deak @ 2021-10-20 19:51 ` Imre Deak 2021-10-20 19:51 ` [Intel-gfx] [PATCH v4 05/11] drm/i915: Unexport is_semiplanar_uv_plane() Imre Deak ` (10 subsequent siblings) 14 siblings, 0 replies; 19+ messages in thread From: Imre Deak @ 2021-10-20 19:51 UTC (permalink / raw) To: intel-gfx; +Cc: Juha-Pekka Heikkila Checking the modifiers that support interlacing makes the condition simpler and avoids us having to add new modifiers to the list (presuming all/most of the new modifiers won't support interlacing). Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> --- drivers/gpu/drm/i915/display/skl_universal_plane.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 7ee2114e420b7..2c3d11193caa7 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -1235,13 +1235,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, /* Y-tiling is not supported in IF-ID Interlace mode */ if (crtc_state->hw.enable && crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE && - (fb->modifier == I915_FORMAT_MOD_Y_TILED || - fb->modifier == I915_FORMAT_MOD_Yf_TILED || - fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || - fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS || - fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || - fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS || - fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC)) { + fb->modifier != DRM_FORMAT_MOD_LINEAR && + fb->modifier != I915_FORMAT_MOD_X_TILED) { drm_dbg_kms(&dev_priv->drm, "Y/Yf tiling not supported in IF-ID mode\n"); return -EINVAL; -- 2.27.0 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH v4 05/11] drm/i915: Unexport is_semiplanar_uv_plane() 2021-10-20 19:51 [Intel-gfx] [PATCH v4 00/11] drm/i915: Simplify handling of modifiers Imre Deak ` (3 preceding siblings ...) 2021-10-20 19:51 ` [Intel-gfx] [PATCH v4 04/11] drm/i915: Simplify the modifier check for interlaced scanout support Imre Deak @ 2021-10-20 19:51 ` Imre Deak 2021-10-20 19:51 ` [Intel-gfx] [PATCH v4 06/11] drm/i915: Move intel_format_info_is_yuv_semiplanar() to intel_fb.c Imre Deak ` (9 subsequent siblings) 14 siblings, 0 replies; 19+ messages in thread From: Imre Deak @ 2021-10-20 19:51 UTC (permalink / raw) To: intel-gfx; +Cc: Juha-Pekka Heikkila This function is only used by intel_fb.c, so unexport it. Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> --- drivers/gpu/drm/i915/display/intel_fb.c | 2 +- drivers/gpu/drm/i915/display/intel_fb.h | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index 8982cfa7205fe..1da55c0f7b21e 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -355,7 +355,7 @@ bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane) plane == 2; } -bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane) +static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane) { return intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && color_plane == 1; diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h index 97b31c3a29825..c331df575490d 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.h +++ b/drivers/gpu/drm/i915/display/intel_fb.h @@ -30,7 +30,6 @@ enum intel_plane_caps { bool is_ccs_plane(const struct drm_framebuffer *fb, int plane); bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane); bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane); -bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane); u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915, enum intel_plane_caps plane_caps); -- 2.27.0 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH v4 06/11] drm/i915: Move intel_format_info_is_yuv_semiplanar() to intel_fb.c 2021-10-20 19:51 [Intel-gfx] [PATCH v4 00/11] drm/i915: Simplify handling of modifiers Imre Deak ` (4 preceding siblings ...) 2021-10-20 19:51 ` [Intel-gfx] [PATCH v4 05/11] drm/i915: Unexport is_semiplanar_uv_plane() Imre Deak @ 2021-10-20 19:51 ` Imre Deak 2021-10-20 19:51 ` [Intel-gfx] [PATCH v4 07/11] drm/i915: Add a platform independent way to get the RC CCS CC plane Imre Deak ` (8 subsequent siblings) 14 siblings, 0 replies; 19+ messages in thread From: Imre Deak @ 2021-10-20 19:51 UTC (permalink / raw) To: intel-gfx; +Cc: Juha-Pekka Heikkila Move intel_format_info_is_yuv_semiplanar() to intel_fb.c . The number of planes for YUV semiplanar formats using CCS modifiers will change on future platforms. We can use the modifier descriptors to simplify getting the plane numbers for all modifiers, prepare for that here. Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> --- .../gpu/drm/i915/display/intel_atomic_plane.c | 1 + drivers/gpu/drm/i915/display/intel_display.c | 8 ----- drivers/gpu/drm/i915/display/intel_display.h | 3 -- drivers/gpu/drm/i915/display/intel_fb.c | 30 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_fb.h | 4 +++ drivers/gpu/drm/i915/intel_pm.c | 1 + 6 files changed, 36 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c index 0be8c00e3db9a..f61a48e1a562b 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -39,6 +39,7 @@ #include "intel_atomic_plane.h" #include "intel_cdclk.h" #include "intel_display_types.h" +#include "intel_fb.h" #include "intel_fb_pin.h" #include "intel_pm.h" #include "intel_sprite.h" diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 86333c0cd7937..c66d525612ad1 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -595,14 +595,6 @@ void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state) intel_wait_for_pipe_off(old_crtc_state); } -bool -intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info, - u64 modifier) -{ - return info->is_yuv && - info->num_planes == (is_ccs_modifier(modifier) ? 4 : 2); -} - unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) { unsigned int size = 0; diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index c2efba7c6c172..38c15ec30ee7c 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -605,9 +605,6 @@ int bdw_get_pipemisc_bpp(struct intel_crtc *crtc); unsigned int intel_plane_fence_y_offset(const struct intel_plane_state *plane_state); bool intel_plane_uses_fence(const struct intel_plane_state *plane_state); -bool -intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info, - u64 modifier); struct intel_encoder * intel_get_crtc_new_encoder(const struct intel_atomic_state *state, diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index 1da55c0f7b21e..73634966a04cd 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -336,6 +336,36 @@ bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier) return false; } +static bool format_is_yuv_semiplanar(const struct intel_modifier_desc *md, + const struct drm_format_info *info) +{ + int yuv_planes; + + if (!info->is_yuv) + return false; + + if (is_ccs_type_modifier(md, INTEL_CCS_ANY)) + yuv_planes = 4; + else + yuv_planes = 2; + + return info->num_planes == yuv_planes; +} + +/** + * intel_format_info_is_yuv_semiplanar: Check if the given format is YUV semiplanar + * @info: format to check + * @modifier: modifier used with the format + * + * Returns: + * %true if @info / @modifier is YUV semiplanar. + */ +bool intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info, + u64 modifier) +{ + return format_is_yuv_semiplanar(lookup_modifier(modifier), info); +} + bool is_ccs_plane(const struct drm_framebuffer *fb, int plane) { if (!is_ccs_modifier(fb->modifier)) diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h index c331df575490d..a2cdf48f13395 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.h +++ b/drivers/gpu/drm/i915/display/intel_fb.h @@ -38,6 +38,10 @@ bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier); const struct drm_format_info * intel_fb_get_format_info(const struct drm_mode_fb_cmd2 *cmd); +bool +intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info, + u64 modifier); + bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane); int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane); diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 201477ca408a5..cffb3df35a636 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -37,6 +37,7 @@ #include "display/intel_bw.h" #include "display/intel_de.h" #include "display/intel_display_types.h" +#include "display/intel_fb.h" #include "display/intel_fbc.h" #include "display/intel_sprite.h" #include "display/skl_universal_plane.h" -- 2.27.0 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH v4 07/11] drm/i915: Add a platform independent way to get the RC CCS CC plane 2021-10-20 19:51 [Intel-gfx] [PATCH v4 00/11] drm/i915: Simplify handling of modifiers Imre Deak ` (5 preceding siblings ...) 2021-10-20 19:51 ` [Intel-gfx] [PATCH v4 06/11] drm/i915: Move intel_format_info_is_yuv_semiplanar() to intel_fb.c Imre Deak @ 2021-10-20 19:51 ` Imre Deak 2021-10-20 19:51 ` [Intel-gfx] [PATCH v4 08/11] drm/i915: Handle CCS CC planes separately from CCS AUX planes Imre Deak ` (7 subsequent siblings) 14 siblings, 0 replies; 19+ messages in thread From: Imre Deak @ 2021-10-20 19:51 UTC (permalink / raw) To: intel-gfx; +Cc: Juha-Pekka Heikkila On future platforms the index of the color-clear plane will change from the one used by the GEN12 RC CCS CC modifier, so add a way to retrieve the index independently of the platform/modifier. Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> --- drivers/gpu/drm/i915/display/intel_display.c | 10 +++++--- drivers/gpu/drm/i915/display/intel_fb.c | 25 ++++++++++++++++++-- drivers/gpu/drm/i915/display/intel_fb.h | 2 ++ 3 files changed, 32 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index c66d525612ad1..2b97c87971773 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -8572,10 +8572,14 @@ static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *s for_each_new_intel_plane_in_state(state, plane, plane_state, i) { struct drm_framebuffer *fb = plane_state->hw.fb; + int cc_plane; int ret; - if (!fb || - fb->modifier != I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) + if (!fb) + continue; + + cc_plane = intel_fb_rc_ccs_cc_plane(fb); + if (cc_plane < 0) continue; /* @@ -8592,7 +8596,7 @@ static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *s * GPU write on it. */ ret = i915_gem_object_read_from_page(intel_fb_obj(fb), - fb->offsets[2] + 16, + fb->offsets[cc_plane] + 16, &plane_state->ccval, sizeof(plane_state->ccval)); /* The above could only fail if the FB obj has an unexpected backing store type. */ diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index 73634966a04cd..a575d8dce3b11 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -130,6 +130,7 @@ struct intel_modifier_desc { #define INTEL_CCS_ANY (INTEL_CCS_RC | INTEL_CCS_RC_CC | INTEL_CCS_MC) u8 type:3; + u8 cc_planes:3; } ccs; }; @@ -158,6 +159,7 @@ static const struct intel_modifier_desc intel_modifiers[] = { .tiling = I915_TILING_Y, .ccs.type = INTEL_CCS_RC_CC, + .ccs.cc_planes = BIT(2), FORMAT_OVERRIDE(gen12_ccs_cc_formats), }, @@ -379,10 +381,29 @@ bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane) return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane); } +/** + * intel_fb_rc_ccs_cc_plane: Get the CCS CC color plane index for a framebuffer + * @fb: Framebuffer + * + * Returns: + * Returns the index of the color clear plane for @fb, or -1 if @fb is not a + * framebuffer using a render compression/color clear modifier. + */ +int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb) +{ + const struct intel_modifier_desc *md = lookup_modifier(fb->modifier); + + if (!md->ccs.cc_planes) + return -1; + + drm_WARN_ON_ONCE(fb->dev, hweight8(md->ccs.cc_planes) > 1); + + return ilog2((int)md->ccs.cc_planes); +} + bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane) { - return fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC && - plane == 2; + return intel_fb_rc_ccs_cc_plane(fb) == plane; } static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane) diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h index a2cdf48f13395..74e0fc03319b9 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.h +++ b/drivers/gpu/drm/i915/display/intel_fb.h @@ -31,6 +31,8 @@ bool is_ccs_plane(const struct drm_framebuffer *fb, int plane); bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane); bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane); +int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb); + u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915, enum intel_plane_caps plane_caps); bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier); -- 2.27.0 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH v4 08/11] drm/i915: Handle CCS CC planes separately from CCS AUX planes 2021-10-20 19:51 [Intel-gfx] [PATCH v4 00/11] drm/i915: Simplify handling of modifiers Imre Deak ` (6 preceding siblings ...) 2021-10-20 19:51 ` [Intel-gfx] [PATCH v4 07/11] drm/i915: Add a platform independent way to get the RC CCS CC plane Imre Deak @ 2021-10-20 19:51 ` Imre Deak 2021-10-20 19:51 ` [Intel-gfx] [PATCH v4 09/11] drm/i915: Add a platform independent way to check for " Imre Deak ` (6 subsequent siblings) 14 siblings, 0 replies; 19+ messages in thread From: Imre Deak @ 2021-10-20 19:51 UTC (permalink / raw) To: intel-gfx; +Cc: Juha-Pekka Heikkila CCS CC planes are quite different from CCS AUX planes, even though we regard the CC planes as a linear buffer having a 64 byte stride. Thus it's clearer to check for either CCS plane types explicitly when we need to handle them; add the required CCS CC planes check here, while the next patch will change all is_ccs_plane()/is_gen12_ccs_plane() checks to consider only the CCS AUX planes. Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> --- drivers/gpu/drm/i915/display/intel_fb.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index a575d8dce3b11..0aa521f923611 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -415,7 +415,8 @@ static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_p bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane) { return fb->modifier == DRM_FORMAT_MOD_LINEAR || - is_gen12_ccs_plane(fb, color_plane); + is_gen12_ccs_plane(fb, color_plane) || + is_gen12_ccs_cc_plane(fb, color_plane); } int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane) @@ -508,7 +509,8 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane) case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: - if (is_ccs_plane(fb, color_plane)) + if (is_ccs_plane(fb, color_plane) || + is_gen12_ccs_cc_plane(fb, color_plane)) return 64; fallthrough; case I915_FORMAT_MOD_Y_TILED: -- 2.27.0 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH v4 09/11] drm/i915: Add a platform independent way to check for CCS AUX planes 2021-10-20 19:51 [Intel-gfx] [PATCH v4 00/11] drm/i915: Simplify handling of modifiers Imre Deak ` (7 preceding siblings ...) 2021-10-20 19:51 ` [Intel-gfx] [PATCH v4 08/11] drm/i915: Handle CCS CC planes separately from CCS AUX planes Imre Deak @ 2021-10-20 19:51 ` Imre Deak 2021-10-20 19:51 ` [Intel-gfx] [PATCH v4 10/11] drm/i915: Move is_ccs_modifier() to intel_fb.c Imre Deak ` (5 subsequent siblings) 14 siblings, 0 replies; 19+ messages in thread From: Imre Deak @ 2021-10-20 19:51 UTC (permalink / raw) To: intel-gfx; +Cc: Juha-Pekka Heikkila, Ville Syrjälä, Jani Nikula Future platforms change the location of CCS AUX planes in CCS framebuffers, so add intel_fb_is_ccs_aux_plane() to query for these planes independently of the platform. This function can be used everywhere instead of is_ccs_plane() (or is_ccs_plane() && !cc_plane()), since all the callers are only interested in CCS AUX planes (and not CCS color-clear planes). Add the corresponding intel_fb_is_gen12_ccs_aux_plane(), which can be used everywhere instead of is_gen12_ccs_plane(), based on the above explanation. This change also unexports the is_gen12_ccs_modifier(), is_gen12_ccs_plane(), is_gen12_ccs_cc_plane() functions as they are only used in intel_fb.c v1-v2: Unchanged v3: (Ville) - Use ccs_aux instead of the ccs_ctrl term everywhere. - Use color_plane instead of plane term for FB plane indicies. v4: Fix version range check. (Jani) Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> --- .../drm/i915/display/intel_display_types.h | 7 -- drivers/gpu/drm/i915/display/intel_fb.c | 82 ++++++++++++++----- drivers/gpu/drm/i915/display/intel_fb.h | 5 +- .../drm/i915/display/skl_universal_plane.c | 3 +- 4 files changed, 64 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index a4930a56bfa82..bf97a56bdbc37 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -2051,11 +2051,4 @@ static inline bool is_ccs_modifier(u64 modifier) modifier == I915_FORMAT_MOD_Yf_TILED_CCS; } -static inline bool is_gen12_ccs_modifier(u64 modifier) -{ - return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || - modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC || - modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS; -} - #endif /* __INTEL_DISPLAY_TYPES_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index 0aa521f923611..58d9928194024 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -131,6 +131,8 @@ struct intel_modifier_desc { #define INTEL_CCS_ANY (INTEL_CCS_RC | INTEL_CCS_RC_CC | INTEL_CCS_MC) u8 type:3; u8 cc_planes:3; + u8 packed_aux_planes:4; + u8 planar_aux_planes:4; } ccs; }; @@ -141,6 +143,8 @@ static const struct intel_modifier_desc intel_modifiers[] = { .tiling = I915_TILING_Y, .ccs.type = INTEL_CCS_MC, + .ccs.packed_aux_planes = BIT(1), + .ccs.planar_aux_planes = BIT(2) | BIT(3), FORMAT_OVERRIDE(gen12_ccs_formats), }, @@ -150,6 +154,7 @@ static const struct intel_modifier_desc intel_modifiers[] = { .tiling = I915_TILING_Y, .ccs.type = INTEL_CCS_RC, + .ccs.packed_aux_planes = BIT(1), FORMAT_OVERRIDE(gen12_ccs_formats), }, @@ -160,6 +165,7 @@ static const struct intel_modifier_desc intel_modifiers[] = { .ccs.type = INTEL_CCS_RC_CC, .ccs.cc_planes = BIT(2), + .ccs.packed_aux_planes = BIT(1), FORMAT_OVERRIDE(gen12_ccs_cc_formats), }, @@ -168,6 +174,7 @@ static const struct intel_modifier_desc intel_modifiers[] = { .display_ver = { 9, 11 }, .ccs.type = INTEL_CCS_RC, + .ccs.packed_aux_planes = BIT(1), FORMAT_OVERRIDE(skl_ccs_formats), }, @@ -177,6 +184,7 @@ static const struct intel_modifier_desc intel_modifiers[] = { .tiling = I915_TILING_Y, .ccs.type = INTEL_CCS_RC, + .ccs.packed_aux_planes = BIT(1), FORMAT_OVERRIDE(skl_ccs_formats), }, @@ -262,6 +270,13 @@ static bool is_ccs_type_modifier(const struct intel_modifier_desc *md, u8 ccs_ty return md->ccs.type & ccs_type; } +static bool check_modifier_display_ver_range(const struct intel_modifier_desc *md, + u8 display_ver_from, u8 display_ver_until) +{ + return md->display_ver.from <= display_ver_until && + display_ver_from <= md->display_ver.until; +} + static bool plane_has_modifier(struct drm_i915_private *i915, enum intel_plane_caps plane_caps, const struct intel_modifier_desc *md) @@ -368,17 +383,44 @@ bool intel_format_info_is_yuv_semiplanar(const struct drm_format_info *info, return format_is_yuv_semiplanar(lookup_modifier(modifier), info); } -bool is_ccs_plane(const struct drm_framebuffer *fb, int plane) +static u8 ccs_aux_plane_mask(const struct intel_modifier_desc *md, + const struct drm_format_info *format) { - if (!is_ccs_modifier(fb->modifier)) - return false; + if (format_is_yuv_semiplanar(md, format)) + return md->ccs.planar_aux_planes; + else + return md->ccs.packed_aux_planes; +} + +/** + * intel_fb_is_ccs_aux_plane: Check if a framebuffer color plane is a CCS AUX plane + * @fb: Framebuffer + * @color_plane: color plane index to check + * + * Returns: + * Returns %true if @fb's color plane at index @color_plane is a CCS AUX plane. + */ +bool intel_fb_is_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane) +{ + const struct intel_modifier_desc *md = lookup_modifier(fb->modifier); - return plane >= fb->format->num_planes / 2; + return ccs_aux_plane_mask(md, fb->format) & BIT(color_plane); } -bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane) +/** + * intel_fb_is_gen12_ccs_aux_plane: Check if a framebuffer color plane is a GEN12 CCS AUX plane + * @fb: Framebuffer + * @color_plane: color plane index to check + * + * Returns: + * Returns %true if @fb's color plane at index @color_plane is a GEN12 CCS AUX plane. + */ +static bool intel_fb_is_gen12_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane) { - return is_gen12_ccs_modifier(fb->modifier) && is_ccs_plane(fb, plane); + const struct intel_modifier_desc *md = lookup_modifier(fb->modifier); + + return check_modifier_display_ver_range(md, 12, 13) && + ccs_aux_plane_mask(md, fb->format) & BIT(color_plane); } /** @@ -401,9 +443,9 @@ int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb) return ilog2((int)md->ccs.cc_planes); } -bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane) +static bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int color_plane) { - return intel_fb_rc_ccs_cc_plane(fb) == plane; + return intel_fb_rc_ccs_cc_plane(fb) == color_plane; } static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_plane) @@ -415,7 +457,7 @@ static bool is_semiplanar_uv_plane(const struct drm_framebuffer *fb, int color_p bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane) { return fb->modifier == DRM_FORMAT_MOD_LINEAR || - is_gen12_ccs_plane(fb, color_plane) || + intel_fb_is_gen12_ccs_aux_plane(fb, color_plane) || is_gen12_ccs_cc_plane(fb, color_plane); } @@ -503,13 +545,13 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane) else return 512; case I915_FORMAT_MOD_Y_TILED_CCS: - if (is_ccs_plane(fb, color_plane)) + if (intel_fb_is_ccs_aux_plane(fb, color_plane)) return 128; fallthrough; case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: - if (is_ccs_plane(fb, color_plane) || + if (intel_fb_is_ccs_aux_plane(fb, color_plane) || is_gen12_ccs_cc_plane(fb, color_plane)) return 64; fallthrough; @@ -519,7 +561,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane) else return 512; case I915_FORMAT_MOD_Yf_TILED_CCS: - if (is_ccs_plane(fb, color_plane)) + if (intel_fb_is_ccs_aux_plane(fb, color_plane)) return 128; fallthrough; case I915_FORMAT_MOD_Yf_TILED: @@ -575,7 +617,7 @@ static void intel_tile_block_dims(const struct drm_framebuffer *fb, int color_pl { intel_tile_dims(fb, color_plane, tile_width, tile_height); - if (is_gen12_ccs_plane(fb, color_plane)) + if (intel_fb_is_gen12_ccs_aux_plane(fb, color_plane)) *tile_height = 1; } @@ -636,7 +678,7 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, return 512 * 4096; /* AUX_DIST needs only 4K alignment */ - if (is_ccs_plane(fb, color_plane)) + if (intel_fb_is_ccs_aux_plane(fb, color_plane)) return 4096; if (is_semiplanar_uv_plane(fb, color_plane)) { @@ -695,7 +737,7 @@ void intel_fb_plane_get_subsampling(int *hsub, int *vsub, * TODO: Deduct the subsampling from the char block for all CCS * formats and planes. */ - if (!is_gen12_ccs_plane(fb, color_plane)) { + if (!intel_fb_is_gen12_ccs_aux_plane(fb, color_plane)) { *hsub = fb->format->hsub; *vsub = fb->format->vsub; @@ -723,7 +765,7 @@ void intel_fb_plane_get_subsampling(int *hsub, int *vsub, static void intel_fb_plane_dims(const struct intel_framebuffer *fb, int color_plane, int *w, int *h) { struct drm_i915_private *i915 = to_i915(fb->base.dev); - int main_plane = is_ccs_plane(&fb->base, color_plane) ? + int main_plane = intel_fb_is_ccs_aux_plane(&fb->base, color_plane) ? skl_ccs_to_main_plane(&fb->base, color_plane) : 0; unsigned int main_width = fb->base.width; unsigned int main_height = fb->base.height; @@ -736,7 +778,7 @@ static void intel_fb_plane_dims(const struct intel_framebuffer *fb, int color_pl * stride in the allocated FB object may not be power-of-two * sized, in which case it is auto-padded to the POT size. */ - if (IS_ALDERLAKE_P(i915) && is_ccs_plane(&fb->base, color_plane)) + if (IS_ALDERLAKE_P(i915) && intel_fb_is_ccs_aux_plane(&fb->base, color_plane)) main_width = gen12_aligned_scanout_stride(fb, 0) / fb->base.format->cpp[0]; @@ -975,7 +1017,7 @@ static int intel_fb_check_ccs_xy(const struct drm_framebuffer *fb, int ccs_plane int ccs_x, ccs_y; int main_x, main_y; - if (!is_ccs_plane(fb, ccs_plane) || is_gen12_ccs_cc_plane(fb, ccs_plane)) + if (!intel_fb_is_ccs_aux_plane(fb, ccs_plane)) return 0; /* @@ -1179,7 +1221,7 @@ plane_view_dst_stride_tiles(const struct intel_framebuffer *fb, int color_plane, unsigned int pitch_tiles) { if (intel_fb_needs_pot_stride_remap(fb)) { - unsigned int min_stride = is_ccs_plane(&fb->base, color_plane) ? 2 : 8; + unsigned int min_stride = intel_fb_is_ccs_aux_plane(&fb->base, color_plane) ? 2 : 8; /* * ADL_P, the only platform needing a POT stride has a minimum * of 8 main surface and 2 CCS AUX stride tiles. @@ -1795,7 +1837,7 @@ int intel_framebuffer_init(struct intel_framebuffer *intel_fb, goto err; } - if (is_gen12_ccs_plane(fb, i) && !is_gen12_ccs_cc_plane(fb, i)) { + if (intel_fb_is_gen12_ccs_aux_plane(fb, i)) { int ccs_aux_stride = gen12_ccs_aux_stride(intel_fb, i); if (fb->pitches[i] != ccs_aux_stride) { diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h index 74e0fc03319b9..c80822b3cb827 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.h +++ b/drivers/gpu/drm/i915/display/intel_fb.h @@ -27,10 +27,7 @@ enum intel_plane_caps { PLANE_HAS_CCS_MC = BIT(2), }; -bool is_ccs_plane(const struct drm_framebuffer *fb, int plane); -bool is_gen12_ccs_plane(const struct drm_framebuffer *fb, int plane); -bool is_gen12_ccs_cc_plane(const struct drm_framebuffer *fb, int plane); - +bool intel_fb_is_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane); int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb); u64 *intel_fb_plane_get_modifiers(struct drm_i915_private *i915, diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 2c3d11193caa7..cd17f03db57ae 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -1602,8 +1602,7 @@ static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state) int hsub, vsub; int x, y; - if (!is_ccs_plane(fb, ccs_plane) || - is_gen12_ccs_cc_plane(fb, ccs_plane)) + if (!intel_fb_is_ccs_aux_plane(fb, ccs_plane)) continue; intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb, -- 2.27.0 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH v4 10/11] drm/i915: Move is_ccs_modifier() to intel_fb.c 2021-10-20 19:51 [Intel-gfx] [PATCH v4 00/11] drm/i915: Simplify handling of modifiers Imre Deak ` (8 preceding siblings ...) 2021-10-20 19:51 ` [Intel-gfx] [PATCH v4 09/11] drm/i915: Add a platform independent way to check for " Imre Deak @ 2021-10-20 19:51 ` Imre Deak 2021-10-20 19:51 ` [Intel-gfx] [PATCH v4 11/11] drm/i915: Add functions to check for RC CCS CC and MC CCS modifiers Imre Deak ` (4 subsequent siblings) 14 siblings, 0 replies; 19+ messages in thread From: Imre Deak @ 2021-10-20 19:51 UTC (permalink / raw) To: intel-gfx; +Cc: Juha-Pekka Heikkila Move the function to intel_fb.c and rename it adding the intel_fb_ prefix following the naming of exported functions. Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> --- .../drm/i915/display/intel_display_types.h | 9 ------ drivers/gpu/drm/i915/display/intel_fb.c | 29 ++++++++++++++----- drivers/gpu/drm/i915/display/intel_fb.h | 2 ++ .../drm/i915/display/skl_universal_plane.c | 12 ++++---- 4 files changed, 29 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index bf97a56bdbc37..85cb55034bb02 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -2042,13 +2042,4 @@ to_intel_frontbuffer(struct drm_framebuffer *fb) return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL; } -static inline bool is_ccs_modifier(u64 modifier) -{ - return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || - modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC || - modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS || - modifier == I915_FORMAT_MOD_Y_TILED_CCS || - modifier == I915_FORMAT_MOD_Yf_TILED_CCS; -} - #endif /* __INTEL_DISPLAY_TYPES_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index 58d9928194024..a0baa5d2e3a19 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -270,6 +270,19 @@ static bool is_ccs_type_modifier(const struct intel_modifier_desc *md, u8 ccs_ty return md->ccs.type & ccs_type; } +/** + * intel_fb_is_ccs_modifier: Check if a modifier is a CCS modifier type + * @modifier: Modifier to check + * + * Returns: + * Returns %true if @modifier is a render, render with color clear or + * media compression modifier. + */ +bool intel_fb_is_ccs_modifier(u64 modifier) +{ + return is_ccs_type_modifier(lookup_modifier(modifier), INTEL_CCS_ANY); +} + static bool check_modifier_display_ver_range(const struct intel_modifier_desc *md, u8 display_ver_from, u8 display_ver_until) { @@ -463,7 +476,7 @@ bool is_surface_linear(const struct drm_framebuffer *fb, int color_plane) int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane) { - drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) || + drm_WARN_ON(fb->dev, !intel_fb_is_ccs_modifier(fb->modifier) || (main_plane && main_plane >= fb->format->num_planes / 2)); return fb->format->num_planes / 2 + main_plane; @@ -471,7 +484,7 @@ int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane) int skl_ccs_to_main_plane(const struct drm_framebuffer *fb, int ccs_plane) { - drm_WARN_ON(fb->dev, !is_ccs_modifier(fb->modifier) || + drm_WARN_ON(fb->dev, !intel_fb_is_ccs_modifier(fb->modifier) || ccs_plane < fb->format->num_planes / 2); if (is_gen12_ccs_cc_plane(fb, ccs_plane)) @@ -516,7 +529,7 @@ int skl_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane) { struct drm_i915_private *i915 = to_i915(fb->dev); - if (is_ccs_modifier(fb->modifier)) + if (intel_fb_is_ccs_modifier(fb->modifier)) return main_to_ccs_plane(fb, main_plane); else if (DISPLAY_VER(i915) < 11 && intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) @@ -1080,7 +1093,7 @@ static bool intel_plane_can_remap(const struct intel_plane_state *plane_state) * The new CCS hash mode isn't compatible with remapping as * the virtual address of the pages affects the compressed data. */ - if (is_ccs_modifier(fb->modifier)) + if (intel_fb_is_ccs_modifier(fb->modifier)) return false; /* Linear needs a page aligned stride for remapping */ @@ -1487,7 +1500,7 @@ static void intel_plane_remap_gtt(struct intel_plane_state *plane_state) src_w = drm_rect_width(&plane_state->uapi.src) >> 16; src_h = drm_rect_height(&plane_state->uapi.src) >> 16; - drm_WARN_ON(&i915->drm, is_ccs_modifier(fb->modifier)); + drm_WARN_ON(&i915->drm, intel_fb_is_ccs_modifier(fb->modifier)); /* Make src coordinates relative to the viewport */ drm_rect_translate(&plane_state->uapi.src, @@ -1550,7 +1563,7 @@ u32 intel_fb_max_stride(struct drm_i915_private *dev_priv, * * The new CCS hash mode makes remapping impossible */ - if (DISPLAY_VER(dev_priv) < 4 || is_ccs_modifier(modifier) || + if (DISPLAY_VER(dev_priv) < 4 || intel_fb_is_ccs_modifier(modifier) || intel_modifier_uses_dpt(dev_priv, modifier)) return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier); else if (DISPLAY_VER(dev_priv) >= 7) @@ -1575,14 +1588,14 @@ intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane) * we need the stride to be page aligned. */ if (fb->pitches[color_plane] > max_stride && - !is_ccs_modifier(fb->modifier)) + !intel_fb_is_ccs_modifier(fb->modifier)) return intel_tile_size(dev_priv); else return 64; } tile_width = intel_tile_width_bytes(fb, color_plane); - if (is_ccs_modifier(fb->modifier)) { + if (intel_fb_is_ccs_modifier(fb->modifier)) { /* * On ADL-P the stride must be either 8 tiles or a stride * that is aligned to 16 tiles, required by the 16 tiles = diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h index c80822b3cb827..f32306fbd3dee 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.h +++ b/drivers/gpu/drm/i915/display/intel_fb.h @@ -27,6 +27,8 @@ enum intel_plane_caps { PLANE_HAS_CCS_MC = BIT(2), }; +bool intel_fb_is_ccs_modifier(u64 modifier); + bool intel_fb_is_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane); int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb); diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index cd17f03db57ae..e2d1c05d4270c 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -1183,7 +1183,7 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, return 0; if (rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180) && - is_ccs_modifier(fb->modifier)) { + intel_fb_is_ccs_modifier(fb->modifier)) { drm_dbg_kms(&dev_priv->drm, "RC support only with 0/180 degree rotation (%x)\n", rotation); @@ -1482,7 +1482,7 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) * CCS AUX surface doesn't have its own x/y offsets, we must make sure * they match with the main surface x/y offsets. */ - if (is_ccs_modifier(fb->modifier)) { + if (intel_fb_is_ccs_modifier(fb->modifier)) { while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset, aux_plane)) { if (offset == 0) @@ -1546,7 +1546,7 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, uv_plane); - if (is_ccs_modifier(fb->modifier)) { + if (intel_fb_is_ccs_modifier(fb->modifier)) { int ccs_plane = main_to_ccs_plane(fb, uv_plane); u32 aux_offset = plane_state->view.color_plane[ccs_plane].offset; u32 alignment = intel_surf_alignment(fb, uv_plane); @@ -1644,7 +1644,7 @@ static int skl_check_plane_surface(struct intel_plane_state *plane_state) * Handle the AUX surface first since the main surface setup depends on * it. */ - if (is_ccs_modifier(fb->modifier)) { + if (intel_fb_is_ccs_modifier(fb->modifier)) { ret = skl_check_ccs_aux_surface(plane_state); if (ret) return ret; @@ -1845,7 +1845,7 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane, case DRM_FORMAT_XBGR8888: case DRM_FORMAT_ARGB8888: case DRM_FORMAT_ABGR8888: - if (is_ccs_modifier(modifier)) + if (intel_fb_is_ccs_modifier(modifier)) return true; fallthrough; case DRM_FORMAT_RGB565: @@ -1899,7 +1899,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane, case DRM_FORMAT_XBGR8888: case DRM_FORMAT_ARGB8888: case DRM_FORMAT_ABGR8888: - if (is_ccs_modifier(modifier)) + if (intel_fb_is_ccs_modifier(modifier)) return true; fallthrough; case DRM_FORMAT_YUYV: -- 2.27.0 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [PATCH v4 11/11] drm/i915: Add functions to check for RC CCS CC and MC CCS modifiers 2021-10-20 19:51 [Intel-gfx] [PATCH v4 00/11] drm/i915: Simplify handling of modifiers Imre Deak ` (9 preceding siblings ...) 2021-10-20 19:51 ` [Intel-gfx] [PATCH v4 10/11] drm/i915: Move is_ccs_modifier() to intel_fb.c Imre Deak @ 2021-10-20 19:51 ` Imre Deak 2021-10-20 20:22 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Simplify handling of modifiers (rev12) Patchwork ` (3 subsequent siblings) 14 siblings, 0 replies; 19+ messages in thread From: Imre Deak @ 2021-10-20 19:51 UTC (permalink / raw) To: intel-gfx; +Cc: Juha-Pekka Heikkila Instead of open-coding the checks add functions for this, simplifying the handling of CCS modifiers on future platforms. Cc: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com> --- drivers/gpu/drm/i915/display/intel_fb.c | 24 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_fb.h | 2 ++ .../drm/i915/display/skl_universal_plane.c | 4 ++-- 3 files changed, 28 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index a0baa5d2e3a19..8a49bf6744ed2 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -283,6 +283,30 @@ bool intel_fb_is_ccs_modifier(u64 modifier) return is_ccs_type_modifier(lookup_modifier(modifier), INTEL_CCS_ANY); } +/** + * intel_fb_is_rc_ccs_cc_modifier: Check if a modifier is an RC CCS CC modifier type + * @modifier: Modifier to check + * + * Returns: + * Returns %true if @modifier is a render with color clear modifier. + */ +bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier) +{ + return is_ccs_type_modifier(lookup_modifier(modifier), INTEL_CCS_RC_CC); +} + +/** + * intel_fb_is_mc_ccs_modifier: Check if a modifier is an MC CCS modifier type + * @modifier: Modifier to check + * + * Returns: + * Returns %true if @modifier is a media compression modifier. + */ +bool intel_fb_is_mc_ccs_modifier(u64 modifier) +{ + return is_ccs_type_modifier(lookup_modifier(modifier), INTEL_CCS_MC); +} + static bool check_modifier_display_ver_range(const struct intel_modifier_desc *md, u8 display_ver_from, u8 display_ver_until) { diff --git a/drivers/gpu/drm/i915/display/intel_fb.h b/drivers/gpu/drm/i915/display/intel_fb.h index f32306fbd3dee..042ad81f86082 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.h +++ b/drivers/gpu/drm/i915/display/intel_fb.h @@ -28,6 +28,8 @@ enum intel_plane_caps { }; bool intel_fb_is_ccs_modifier(u64 modifier); +bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier); +bool intel_fb_is_mc_ccs_modifier(u64 modifier); bool intel_fb_is_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane); int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb); diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index e2d1c05d4270c..69fd56de83a7a 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -1078,7 +1078,7 @@ skl_program_plane(struct intel_plane *plane, if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id)) icl_program_input_csc(plane, crtc_state, plane_state); - if (fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC) + if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier)) intel_uncore_write64_fw(&dev_priv->uncore, PLANE_CC_VAL(pipe, plane_id), plane_state->ccval); @@ -1911,7 +1911,7 @@ static bool gen12_plane_format_mod_supported(struct drm_plane *_plane, case DRM_FORMAT_P010: case DRM_FORMAT_P012: case DRM_FORMAT_P016: - if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS) + if (intel_fb_is_mc_ccs_modifier(modifier)) return true; fallthrough; case DRM_FORMAT_RGB565: -- 2.27.0 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Simplify handling of modifiers (rev12) 2021-10-20 19:51 [Intel-gfx] [PATCH v4 00/11] drm/i915: Simplify handling of modifiers Imre Deak ` (10 preceding siblings ...) 2021-10-20 19:51 ` [Intel-gfx] [PATCH v4 11/11] drm/i915: Add functions to check for RC CCS CC and MC CCS modifiers Imre Deak @ 2021-10-20 20:22 ` Patchwork 2021-10-20 20:24 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork ` (2 subsequent siblings) 14 siblings, 0 replies; 19+ messages in thread From: Patchwork @ 2021-10-20 20:22 UTC (permalink / raw) To: Imre Deak; +Cc: intel-gfx == Series Details == Series: drm/i915: Simplify handling of modifiers (rev12) URL : https://patchwork.freedesktop.org/series/95579/ State : warning == Summary == $ dim checkpatch origin/drm-tip 78f3fdfcbe6d drm/i915: Add a table with a descriptor for all i915 modifiers -:30: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #30: - Use from, until display version fields in modifier_desc instead of a mask. (Jani) total: 0 errors, 1 warnings, 0 checks, 668 lines checked 31cf2c8a39f2 drm/i915: Move intel_get_format_info() to intel_fb.c -:284: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'format_list' - possible side-effects? #284: FILE: drivers/gpu/drm/i915/display/intel_fb.c:119: +#define FORMAT_OVERRIDE(format_list) \ + .formats = format_list, \ + .format_count = ARRAY_SIZE(format_list) total: 0 errors, 0 warnings, 1 checks, 354 lines checked bc09112178a4 drm/i915: Add tiling attribute to the modifier descriptor c62bf50af74c drm/i915: Simplify the modifier check for interlaced scanout support d9e1b092e0b4 drm/i915: Unexport is_semiplanar_uv_plane() a57a4c9e3ddc drm/i915: Move intel_format_info_is_yuv_semiplanar() to intel_fb.c 3b5a352ccae1 drm/i915: Add a platform independent way to get the RC CCS CC plane 066204606ff2 drm/i915: Handle CCS CC planes separately from CCS AUX planes 48b044ca6958 drm/i915: Add a platform independent way to check for CCS AUX planes 605d4c7e75b3 drm/i915: Move is_ccs_modifier() to intel_fb.c a510cc2c3093 drm/i915: Add functions to check for RC CCS CC and MC CCS modifiers ^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Simplify handling of modifiers (rev12) 2021-10-20 19:51 [Intel-gfx] [PATCH v4 00/11] drm/i915: Simplify handling of modifiers Imre Deak ` (11 preceding siblings ...) 2021-10-20 20:22 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Simplify handling of modifiers (rev12) Patchwork @ 2021-10-20 20:24 ` Patchwork 2021-10-20 20:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-10-21 0:34 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 14 siblings, 0 replies; 19+ messages in thread From: Patchwork @ 2021-10-20 20:24 UTC (permalink / raw) To: Imre Deak; +Cc: intel-gfx == Series Details == Series: drm/i915: Simplify handling of modifiers (rev12) URL : https://patchwork.freedesktop.org/series/95579/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31 +drivers/gpu/drm/i915/gt/intel_reset.c:1392:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block +drivers/gpu/drm/i915/i915_perf.c:1442:15: warning: memset with byte count of 16777216 +drivers/gpu/drm/i915/i915_perf.c:1496:15: warning: memset with byte count of 16777216 +./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080) +./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080) +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block +./include/linux/spinlock.h:418:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block ^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Simplify handling of modifiers (rev12) 2021-10-20 19:51 [Intel-gfx] [PATCH v4 00/11] drm/i915: Simplify handling of modifiers Imre Deak ` (12 preceding siblings ...) 2021-10-20 20:24 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork @ 2021-10-20 20:51 ` Patchwork 2021-10-21 0:34 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 14 siblings, 0 replies; 19+ messages in thread From: Patchwork @ 2021-10-20 20:51 UTC (permalink / raw) To: Imre Deak; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 4838 bytes --] == Series Details == Series: drm/i915: Simplify handling of modifiers (rev12) URL : https://patchwork.freedesktop.org/series/95579/ State : success == Summary == CI Bug Log - changes from CI_DRM_10765 -> Patchwork_21393 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/index.html Known issues ------------ Here are the changes found in Patchwork_21393 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@i915_selftest@live@hangcheck: - fi-snb-2600: [PASS][1] -> [INCOMPLETE][2] ([i915#3921]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/fi-snb-2600/igt@i915_selftest@live@hangcheck.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/fi-snb-2600/igt@i915_selftest@live@hangcheck.html #### Possible fixes #### * igt@i915_selftest@live@perf: - {fi-tgl-dsi}: [DMESG-WARN][3] ([i915#2867]) -> [PASS][4] +11 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/fi-tgl-dsi/igt@i915_selftest@live@perf.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/fi-tgl-dsi/igt@i915_selftest@live@perf.html * igt@kms_flip@basic-flip-vs-wf_vblank@c-dp1: - fi-cfl-8109u: [FAIL][5] ([i915#4165]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/fi-cfl-8109u/igt@kms_flip@basic-flip-vs-wf_vblank@c-dp1.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/fi-cfl-8109u/igt@kms_flip@basic-flip-vs-wf_vblank@c-dp1.html * igt@kms_frontbuffer_tracking@basic: - fi-cml-u2: [DMESG-WARN][7] ([i915#4269]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b: - fi-cfl-8109u: [DMESG-WARN][9] ([i915#295]) -> [PASS][10] +17 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html #### Warnings #### * igt@kms_frontbuffer_tracking@basic: - fi-cfl-8109u: [DMESG-WARN][11] ([i915#295]) -> [FAIL][12] ([i915#2546]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/fi-cfl-8109u/igt@kms_frontbuffer_tracking@basic.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [i915#2546]: https://gitlab.freedesktop.org/drm/intel/issues/2546 [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867 [i915#295]: https://gitlab.freedesktop.org/drm/intel/issues/295 [i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921 [i915#4165]: https://gitlab.freedesktop.org/drm/intel/issues/4165 [i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269 Participating hosts (44 -> 38) ------------------------------ Missing (6): fi-ilk-m540 bat-dg1-6 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-kbl-x1275 Build changes ------------- * Linux: CI_DRM_10765 -> Patchwork_21393 CI-20190529: 20190529 CI_DRM_10765: 19edb8bd013aa8cfd4345a405b07a0c1ef424b74 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6258: 4c80c71d7dec29b6376846ae96bd04dc0b6e34d9 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_21393: a510cc2c3093e14534e5641be105d6445613e42d @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == a510cc2c3093 drm/i915: Add functions to check for RC CCS CC and MC CCS modifiers 605d4c7e75b3 drm/i915: Move is_ccs_modifier() to intel_fb.c 48b044ca6958 drm/i915: Add a platform independent way to check for CCS AUX planes 066204606ff2 drm/i915: Handle CCS CC planes separately from CCS AUX planes 3b5a352ccae1 drm/i915: Add a platform independent way to get the RC CCS CC plane a57a4c9e3ddc drm/i915: Move intel_format_info_is_yuv_semiplanar() to intel_fb.c d9e1b092e0b4 drm/i915: Unexport is_semiplanar_uv_plane() c62bf50af74c drm/i915: Simplify the modifier check for interlaced scanout support bc09112178a4 drm/i915: Add tiling attribute to the modifier descriptor 31cf2c8a39f2 drm/i915: Move intel_get_format_info() to intel_fb.c 78f3fdfcbe6d drm/i915: Add a table with a descriptor for all i915 modifiers == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/index.html [-- Attachment #2: Type: text/html, Size: 5707 bytes --] ^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Simplify handling of modifiers (rev12) 2021-10-20 19:51 [Intel-gfx] [PATCH v4 00/11] drm/i915: Simplify handling of modifiers Imre Deak ` (13 preceding siblings ...) 2021-10-20 20:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork @ 2021-10-21 0:34 ` Patchwork 2021-10-21 19:00 ` Imre Deak 14 siblings, 1 reply; 19+ messages in thread From: Patchwork @ 2021-10-21 0:34 UTC (permalink / raw) To: Imre Deak; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 30271 bytes --] == Series Details == Series: drm/i915: Simplify handling of modifiers (rev12) URL : https://patchwork.freedesktop.org/series/95579/ State : success == Summary == CI Bug Log - changes from CI_DRM_10765_full -> Patchwork_21393_full ==================================================== Summary ------- **SUCCESS** No regressions found. Known issues ------------ Here are the changes found in Patchwork_21393_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_create@create-massive: - shard-kbl: NOTRUN -> [DMESG-WARN][1] ([i915#3002]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl2/igt@gem_create@create-massive.html * igt@gem_ctx_persistence@legacy-engines-hostile-preempt: - shard-snb: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1099]) +2 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-snb5/igt@gem_ctx_persistence@legacy-engines-hostile-preempt.html * igt@gem_exec_fair@basic-flow@rcs0: - shard-skl: NOTRUN -> [SKIP][3] ([fdo#109271]) +155 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl8/igt@gem_exec_fair@basic-flow@rcs0.html * igt@gem_exec_fair@basic-pace@vecs0: - shard-kbl: [PASS][4] -> [FAIL][5] ([i915#2842]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-kbl2/igt@gem_exec_fair@basic-pace@vecs0.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl6/igt@gem_exec_fair@basic-pace@vecs0.html - shard-tglb: [PASS][6] -> [FAIL][7] ([i915#2842]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-tglb6/igt@gem_exec_fair@basic-pace@vecs0.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-tglb6/igt@gem_exec_fair@basic-pace@vecs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-glk: [PASS][8] -> [FAIL][9] ([i915#2842]) +2 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-glk5/igt@gem_exec_fair@basic-throttle@rcs0.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-glk1/igt@gem_exec_fair@basic-throttle@rcs0.html - shard-tglb: NOTRUN -> [FAIL][10] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-tglb2/igt@gem_exec_fair@basic-throttle@rcs0.html * igt@gem_huc_copy@huc-copy: - shard-skl: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#2190]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl7/igt@gem_huc_copy@huc-copy.html * igt@gem_mmap_offset@open-flood: - shard-skl: [PASS][12] -> [DMESG-WARN][13] ([i915#1982]) +1 similar issue [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-skl1/igt@gem_mmap_offset@open-flood.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl9/igt@gem_mmap_offset@open-flood.html * igt@gem_ppgtt@flink-and-close-vma-leak: - shard-glk: [PASS][14] -> [FAIL][15] ([i915#644]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-glk4/igt@gem_ppgtt@flink-and-close-vma-leak.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-glk2/igt@gem_ppgtt@flink-and-close-vma-leak.html * igt@gem_pread@exhaustion: - shard-apl: NOTRUN -> [WARN][16] ([i915#2658]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-apl3/igt@gem_pread@exhaustion.html * igt@gem_userptr_blits@dmabuf-sync: - shard-skl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#3323]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl9/igt@gem_userptr_blits@dmabuf-sync.html * igt@gem_userptr_blits@input-checking: - shard-apl: NOTRUN -> [DMESG-WARN][18] ([i915#3002]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-apl6/igt@gem_userptr_blits@input-checking.html * igt@gem_userptr_blits@readonly-unsync: - shard-tglb: NOTRUN -> [SKIP][19] ([i915#3297]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-tglb5/igt@gem_userptr_blits@readonly-unsync.html * igt@gem_userptr_blits@vma-merge: - shard-kbl: NOTRUN -> [FAIL][20] ([i915#3318]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl1/igt@gem_userptr_blits@vma-merge.html * igt@gen9_exec_parse@basic-rejected: - shard-tglb: NOTRUN -> [SKIP][21] ([i915#2856]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-tglb5/igt@gen9_exec_parse@basic-rejected.html * igt@i915_pm_dc@dc6-psr: - shard-iclb: [PASS][22] -> [FAIL][23] ([i915#454]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-iclb7/igt@i915_pm_dc@dc6-psr.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-iclb6/igt@i915_pm_dc@dc6-psr.html * igt@i915_pm_rpm@dpms-non-lpsp: - shard-tglb: NOTRUN -> [SKIP][24] ([fdo#111644] / [i915#1397] / [i915#2411]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-tglb5/igt@i915_pm_rpm@dpms-non-lpsp.html * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip: - shard-kbl: NOTRUN -> [SKIP][25] ([fdo#109271] / [i915#3777]) +1 similar issue [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl2/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip.html * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip: - shard-skl: NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#3777]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl7/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip.html * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0: - shard-apl: NOTRUN -> [SKIP][27] ([fdo#109271]) +91 similar issues [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-apl3/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip: - shard-tglb: NOTRUN -> [SKIP][28] ([fdo#111615]) [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-tglb5/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip.html * igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_mc_ccs: - shard-apl: NOTRUN -> [SKIP][29] ([fdo#109271] / [i915#3886]) +1 similar issue [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-apl6/igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc: - shard-kbl: NOTRUN -> [SKIP][30] ([fdo#109271] / [i915#3886]) +5 similar issues [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl2/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs: - shard-skl: NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#3886]) +7 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl8/igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-d-crc-primary-rotation-180-yf_tiled_ccs: - shard-tglb: NOTRUN -> [SKIP][32] ([i915#3689]) [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-tglb2/igt@kms_ccs@pipe-d-crc-primary-rotation-180-yf_tiled_ccs.html * igt@kms_chamelium@hdmi-mode-timings: - shard-kbl: NOTRUN -> [SKIP][33] ([fdo#109271] / [fdo#111827]) +12 similar issues [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl2/igt@kms_chamelium@hdmi-mode-timings.html * igt@kms_chamelium@vga-hpd-for-each-pipe: - shard-skl: NOTRUN -> [SKIP][34] ([fdo#109271] / [fdo#111827]) +12 similar issues [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl9/igt@kms_chamelium@vga-hpd-for-each-pipe.html * igt@kms_color@pipe-a-ctm-0-75: - shard-skl: NOTRUN -> [DMESG-WARN][35] ([i915#1982]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl8/igt@kms_color@pipe-a-ctm-0-75.html * igt@kms_color_chamelium@pipe-b-ctm-0-75: - shard-tglb: NOTRUN -> [SKIP][36] ([fdo#109284] / [fdo#111827]) [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-tglb2/igt@kms_color_chamelium@pipe-b-ctm-0-75.html * igt@kms_color_chamelium@pipe-b-ctm-max: - shard-snb: NOTRUN -> [SKIP][37] ([fdo#109271] / [fdo#111827]) +8 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-snb5/igt@kms_color_chamelium@pipe-b-ctm-max.html * igt@kms_color_chamelium@pipe-c-ctm-0-25: - shard-apl: NOTRUN -> [SKIP][38] ([fdo#109271] / [fdo#111827]) +6 similar issues [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-apl8/igt@kms_color_chamelium@pipe-c-ctm-0-25.html * igt@kms_content_protection@atomic: - shard-kbl: NOTRUN -> [TIMEOUT][39] ([i915#1319]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl7/igt@kms_content_protection@atomic.html * igt@kms_cursor_crc@pipe-b-cursor-512x170-random: - shard-tglb: NOTRUN -> [SKIP][40] ([fdo#109279] / [i915#3359]) [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-tglb5/igt@kms_cursor_crc@pipe-b-cursor-512x170-random.html * igt@kms_cursor_crc@pipe-c-cursor-max-size-random: - shard-tglb: NOTRUN -> [SKIP][41] ([i915#3359]) [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-tglb5/igt@kms_cursor_crc@pipe-c-cursor-max-size-random.html * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: - shard-tglb: NOTRUN -> [SKIP][42] ([fdo#111825]) +2 similar issues [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-tglb5/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html * igt@kms_cursor_legacy@pipe-d-torture-bo: - shard-kbl: NOTRUN -> [SKIP][43] ([fdo#109271] / [i915#533]) [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl7/igt@kms_cursor_legacy@pipe-d-torture-bo.html * igt@kms_fbcon_fbt@fbc-suspend: - shard-kbl: [PASS][44] -> [INCOMPLETE][45] ([i915#180] / [i915#636]) [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl4/igt@kms_fbcon_fbt@fbc-suspend.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1: - shard-skl: [PASS][46] -> [FAIL][47] ([i915#2122]) [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-skl10/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html * igt@kms_flip@flip-vs-expired-vblank@a-edp1: - shard-skl: [PASS][48] -> [FAIL][49] ([i915#79]) [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-skl1/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl9/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1: - shard-kbl: [PASS][50] -> [DMESG-WARN][51] ([i915#180]) +12 similar issues [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs: - shard-skl: NOTRUN -> [SKIP][52] ([fdo#109271] / [i915#2672]) [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl9/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt: - shard-snb: NOTRUN -> [SKIP][53] ([fdo#109271]) +147 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-snb5/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt.html * igt@kms_hdr@bpc-switch: - shard-skl: NOTRUN -> [FAIL][54] ([i915#1188]) [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl9/igt@kms_hdr@bpc-switch.html * igt@kms_pipe_crc_basic@hang-read-crc-pipe-d: - shard-skl: NOTRUN -> [SKIP][55] ([fdo#109271] / [i915#533]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl8/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence: - shard-apl: NOTRUN -> [SKIP][56] ([fdo#109271] / [i915#533]) [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-apl6/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes: - shard-apl: [PASS][57] -> [DMESG-WARN][58] ([i915#180]) [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-apl8/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html * igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb: - shard-kbl: NOTRUN -> [FAIL][59] ([i915#265]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl7/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: NOTRUN -> [FAIL][60] ([fdo#108145] / [i915#265]) +1 similar issue [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt@kms_plane_alpha_blend@pipe-b-alpha-basic: - shard-kbl: NOTRUN -> [FAIL][61] ([fdo#108145] / [i915#265]) +1 similar issue [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl2/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html * igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb: - shard-apl: NOTRUN -> [FAIL][62] ([fdo#108145] / [i915#265]) +1 similar issue [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-apl3/igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb.html * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1: - shard-skl: NOTRUN -> [SKIP][63] ([fdo#109271] / [i915#658]) +1 similar issue [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl8/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html * igt@kms_psr2_sf@plane-move-sf-dmg-area-2: - shard-apl: NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#658]) +1 similar issue [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-apl6/igt@kms_psr2_sf@plane-move-sf-dmg-area-2.html * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5: - shard-kbl: NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#658]) +3 similar issues [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html - shard-tglb: NOTRUN -> [SKIP][66] ([i915#2920]) [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-tglb5/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html * igt@kms_writeback@writeback-invalid-parameters: - shard-apl: NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#2437]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-apl3/igt@kms_writeback@writeback-invalid-parameters.html * igt@kms_writeback@writeback-pixel-formats: - shard-skl: NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#2437]) +1 similar issue [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl7/igt@kms_writeback@writeback-pixel-formats.html * igt@nouveau_crc@pipe-d-ctx-flip-skip-current-frame: - shard-tglb: NOTRUN -> [SKIP][69] ([i915#2530]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-tglb5/igt@nouveau_crc@pipe-d-ctx-flip-skip-current-frame.html * igt@perf_pmu@module-unload: - shard-skl: [PASS][70] -> [DMESG-WARN][71] ([i915#1982] / [i915#262]) [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-skl9/igt@perf_pmu@module-unload.html [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl10/igt@perf_pmu@module-unload.html * igt@prime_nv_pcopy@test2: - shard-kbl: NOTRUN -> [SKIP][72] ([fdo#109271]) +123 similar issues [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl7/igt@prime_nv_pcopy@test2.html * igt@prime_vgem@fence-write-hang: - shard-tglb: NOTRUN -> [SKIP][73] ([fdo#109295]) [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-tglb5/igt@prime_vgem@fence-write-hang.html * igt@sysfs_clients@create: - shard-kbl: NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#2994]) +1 similar issue [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl7/igt@sysfs_clients@create.html * igt@sysfs_clients@split-50: - shard-apl: NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#2994]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-apl6/igt@sysfs_clients@split-50.html #### Possible fixes #### * igt@drm_mm@all@bottomup: - shard-skl: [INCOMPLETE][76] -> [PASS][77] [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-skl10/igt@drm_mm@all@bottomup.html [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl3/igt@drm_mm@all@bottomup.html * igt@gem_exec_fair@basic-deadline: - shard-glk: [FAIL][78] ([i915#2846]) -> [PASS][79] [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-glk6/igt@gem_exec_fair@basic-deadline.html [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-glk9/igt@gem_exec_fair@basic-deadline.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-apl: [SKIP][80] ([fdo#109271]) -> [PASS][81] [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-apl2/igt@gem_exec_fair@basic-none-share@rcs0.html [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-apl6/igt@gem_exec_fair@basic-none-share@rcs0.html * igt@gem_exec_fair@basic-none@vcs0: - shard-kbl: [FAIL][82] ([i915#2842]) -> [PASS][83] +1 similar issue [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-kbl2/igt@gem_exec_fair@basic-none@vcs0.html [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl4/igt@gem_exec_fair@basic-none@vcs0.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-tglb: [FAIL][84] ([i915#2842]) -> [PASS][85] +2 similar issues [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-tglb8/igt@gem_exec_fair@basic-pace-share@rcs0.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size: - shard-skl: [FAIL][86] ([i915#2346] / [i915#533]) -> [PASS][87] [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html * igt@kms_fbcon_fbt@fbc-suspend: - shard-apl: [INCOMPLETE][88] ([i915#180] / [i915#1982]) -> [PASS][89] [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-apl1/igt@kms_fbcon_fbt@fbc-suspend.html [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-apl8/igt@kms_fbcon_fbt@fbc-suspend.html * igt@kms_frontbuffer_tracking@psr-suspend: - shard-skl: [INCOMPLETE][90] ([i915#123]) -> [PASS][91] [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-skl1/igt@kms_frontbuffer_tracking@psr-suspend.html [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl9/igt@kms_frontbuffer_tracking@psr-suspend.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - shard-skl: [INCOMPLETE][92] ([i915#198]) -> [PASS][93] [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-skl7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl8/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes: - shard-kbl: [DMESG-WARN][94] ([i915#180]) -> [PASS][95] +7 similar issues [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-kbl3/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl1/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: - shard-skl: [FAIL][96] ([fdo#108145] / [i915#265]) -> [PASS][97] +2 similar issues [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html * igt@perf@polling-parameterized: - shard-glk: [FAIL][98] ([i915#1542]) -> [PASS][99] [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-glk7/igt@perf@polling-parameterized.html [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-glk2/igt@perf@polling-parameterized.html - shard-skl: [FAIL][100] ([i915#1542]) -> [PASS][101] [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-skl8/igt@perf@polling-parameterized.html [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl2/igt@perf@polling-parameterized.html * igt@sysfs_preempt_timeout@timeout@vecs0: - shard-skl: [FAIL][102] -> [PASS][103] [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-skl10/igt@sysfs_preempt_timeout@timeout@vecs0.html [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl5/igt@sysfs_preempt_timeout@timeout@vecs0.html #### Warnings #### * igt@gem_exec_fair@basic-pace@rcs0: - shard-kbl: [FAIL][104] ([i915#2842]) -> [FAIL][105] ([i915#2851]) [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-kbl2/igt@gem_exec_fair@basic-pace@rcs0.html [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl6/igt@gem_exec_fair@basic-pace@rcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-iclb: [FAIL][106] ([i915#2842]) -> [FAIL][107] ([i915#2849]) [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html * igt@i915_pm_rc6_residency@rc6-fence: - shard-iclb: [WARN][108] ([i915#1804] / [i915#2684]) -> [WARN][109] ([i915#2684]) [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-iclb6/igt@i915_pm_rc6_residency@rc6-fence.html [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-iclb8/igt@i915_pm_rc6_residency@rc6-fence.html * igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary: - shard-skl: [INCOMPLETE][110] ([i915#123]) -> [SKIP][111] ([fdo#109271]) [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-skl8/igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary.html [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl2/igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary.html * igt@runner@aborted: - shard-kbl: ([FAIL][112], [FAIL][113], [FAIL][114], [FAIL][115], [FAIL][116], [FAIL][117], [FAIL][118], [FAIL][119]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363] / [i915#4312] / [i915#602]) -> ([FAIL][120], [FAIL][121], [FAIL][122], [FAIL][123], [FAIL][124], [FAIL][125], [FAIL][126], [FAIL][127], [FAIL][128], [FAIL][129], [FAIL][130], [FAIL][131]) ([i915#180] / [i915#1814] / [i915#3002] / [i915#3363] / [i915#4312] / [i915#602] / [i915#92]) [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-kbl6/igt@runner@aborted.html [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-kbl6/igt@runner@aborted.html [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-kbl4/igt@runner@aborted.html [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-kbl6/igt@runner@aborted.html [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-kbl1/igt@runner@aborted.html [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-kbl6/igt@runner@aborted.html [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-kbl6/igt@runner@aborted.html [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-kbl3/igt@runner@aborted.html [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl4/igt@runner@aborted.html [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl6/igt@runner@aborted.html [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl2/igt@runner@aborted.html [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl4/igt@runner@aborted.html [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl6/igt@runner@aborted.html [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl4/igt@runner@aborted.html [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl4/igt@runner@aborted.html [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl3/igt@runner@aborted.html [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl3/igt@runner@aborted.html [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl3/igt@runner@aborted.html [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl3/igt@runner@aborted.html [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl3/igt@runner@aborted.html - shard-apl: ([FAIL][132], [FAIL][133], [FAIL][134]) ([i915#180] / [i915#3002] / [i915#3363] / [i915#4312]) -> ([FAIL][135], [FAIL][136], [FAIL][137]) ([i915#3002] / [i915#3363] / [i915#4312]) [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-apl1/igt@runner@aborted.html [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-apl1/igt@runner@aborted.html [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-apl6/igt@runner@aborted.html [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-apl7/igt@runner@aborted.html [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-apl1/igt@runner@aborted.html [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-apl6/igt@runner@aborted.html [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279 [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284 [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295 [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615 [fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644 [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#123]: https://gitlab.freedesktop.org/drm/intel/issues/123 [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804 [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814 [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346 [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411 [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437 [i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530 [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658 [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672 [i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684 [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842 [i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846 [i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849 [i915#2851]: https://gitlab.freedesktop.org/drm/intel/issues/2851 [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856 [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920 [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994 [i915#3002] == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/index.html [-- Attachment #2: Type: text/html, Size: 37489 bytes --] ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Simplify handling of modifiers (rev12) 2021-10-21 0:34 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork @ 2021-10-21 19:00 ` Imre Deak 0 siblings, 0 replies; 19+ messages in thread From: Imre Deak @ 2021-10-21 19:00 UTC (permalink / raw) To: intel-gfx, Juha-Pekka Heikkilä, Ville Syrjälä, Jani Nikula On Thu, Oct 21, 2021 at 12:34:23AM +0000, Patchwork wrote: > == Series Details == > > Series: drm/i915: Simplify handling of modifiers (rev12) > URL : https://patchwork.freedesktop.org/series/95579/ > State : success Pushed with that the '}, {' formatting change applied, thanks for the reviews. > > == Summary == > > CI Bug Log - changes from CI_DRM_10765_full -> Patchwork_21393_full > ==================================================== > > Summary > ------- > > **SUCCESS** > > No regressions found. > > > > Known issues > ------------ > > Here are the changes found in Patchwork_21393_full that come from known issues: > > ### IGT changes ### > > #### Issues hit #### > > * igt@gem_create@create-massive: > - shard-kbl: NOTRUN -> [DMESG-WARN][1] ([i915#3002]) > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl2/igt@gem_create@create-massive.html > > * igt@gem_ctx_persistence@legacy-engines-hostile-preempt: > - shard-snb: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1099]) +2 similar issues > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-snb5/igt@gem_ctx_persistence@legacy-engines-hostile-preempt.html > > * igt@gem_exec_fair@basic-flow@rcs0: > - shard-skl: NOTRUN -> [SKIP][3] ([fdo#109271]) +155 similar issues > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl8/igt@gem_exec_fair@basic-flow@rcs0.html > > * igt@gem_exec_fair@basic-pace@vecs0: > - shard-kbl: [PASS][4] -> [FAIL][5] ([i915#2842]) > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-kbl2/igt@gem_exec_fair@basic-pace@vecs0.html > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl6/igt@gem_exec_fair@basic-pace@vecs0.html > - shard-tglb: [PASS][6] -> [FAIL][7] ([i915#2842]) > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-tglb6/igt@gem_exec_fair@basic-pace@vecs0.html > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-tglb6/igt@gem_exec_fair@basic-pace@vecs0.html > > * igt@gem_exec_fair@basic-throttle@rcs0: > - shard-glk: [PASS][8] -> [FAIL][9] ([i915#2842]) +2 similar issues > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-glk5/igt@gem_exec_fair@basic-throttle@rcs0.html > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-glk1/igt@gem_exec_fair@basic-throttle@rcs0.html > - shard-tglb: NOTRUN -> [FAIL][10] ([i915#2842]) > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-tglb2/igt@gem_exec_fair@basic-throttle@rcs0.html > > * igt@gem_huc_copy@huc-copy: > - shard-skl: NOTRUN -> [SKIP][11] ([fdo#109271] / [i915#2190]) > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl7/igt@gem_huc_copy@huc-copy.html > > * igt@gem_mmap_offset@open-flood: > - shard-skl: [PASS][12] -> [DMESG-WARN][13] ([i915#1982]) +1 similar issue > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-skl1/igt@gem_mmap_offset@open-flood.html > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl9/igt@gem_mmap_offset@open-flood.html > > * igt@gem_ppgtt@flink-and-close-vma-leak: > - shard-glk: [PASS][14] -> [FAIL][15] ([i915#644]) > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-glk4/igt@gem_ppgtt@flink-and-close-vma-leak.html > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-glk2/igt@gem_ppgtt@flink-and-close-vma-leak.html > > * igt@gem_pread@exhaustion: > - shard-apl: NOTRUN -> [WARN][16] ([i915#2658]) > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-apl3/igt@gem_pread@exhaustion.html > > * igt@gem_userptr_blits@dmabuf-sync: > - shard-skl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#3323]) > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl9/igt@gem_userptr_blits@dmabuf-sync.html > > * igt@gem_userptr_blits@input-checking: > - shard-apl: NOTRUN -> [DMESG-WARN][18] ([i915#3002]) > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-apl6/igt@gem_userptr_blits@input-checking.html > > * igt@gem_userptr_blits@readonly-unsync: > - shard-tglb: NOTRUN -> [SKIP][19] ([i915#3297]) > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-tglb5/igt@gem_userptr_blits@readonly-unsync.html > > * igt@gem_userptr_blits@vma-merge: > - shard-kbl: NOTRUN -> [FAIL][20] ([i915#3318]) > [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl1/igt@gem_userptr_blits@vma-merge.html > > * igt@gen9_exec_parse@basic-rejected: > - shard-tglb: NOTRUN -> [SKIP][21] ([i915#2856]) > [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-tglb5/igt@gen9_exec_parse@basic-rejected.html > > * igt@i915_pm_dc@dc6-psr: > - shard-iclb: [PASS][22] -> [FAIL][23] ([i915#454]) > [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-iclb7/igt@i915_pm_dc@dc6-psr.html > [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-iclb6/igt@i915_pm_dc@dc6-psr.html > > * igt@i915_pm_rpm@dpms-non-lpsp: > - shard-tglb: NOTRUN -> [SKIP][24] ([fdo#111644] / [i915#1397] / [i915#2411]) > [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-tglb5/igt@i915_pm_rpm@dpms-non-lpsp.html > > * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip: > - shard-kbl: NOTRUN -> [SKIP][25] ([fdo#109271] / [i915#3777]) +1 similar issue > [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl2/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip.html > > * igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip: > - shard-skl: NOTRUN -> [SKIP][26] ([fdo#109271] / [i915#3777]) > [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl7/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-hflip.html > > * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0: > - shard-apl: NOTRUN -> [SKIP][27] ([fdo#109271]) +91 similar issues > [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-apl3/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0.html > > * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip: > - shard-tglb: NOTRUN -> [SKIP][28] ([fdo#111615]) > [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-tglb5/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip.html > > * igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_mc_ccs: > - shard-apl: NOTRUN -> [SKIP][29] ([fdo#109271] / [i915#3886]) +1 similar issue > [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-apl6/igt@kms_ccs@pipe-a-crc-primary-basic-y_tiled_gen12_mc_ccs.html > > * igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc: > - shard-kbl: NOTRUN -> [SKIP][30] ([fdo#109271] / [i915#3886]) +5 similar issues > [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl2/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html > > * igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs: > - shard-skl: NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#3886]) +7 similar issues > [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl8/igt@kms_ccs@pipe-b-crc-primary-basic-y_tiled_gen12_mc_ccs.html > > * igt@kms_ccs@pipe-d-crc-primary-rotation-180-yf_tiled_ccs: > - shard-tglb: NOTRUN -> [SKIP][32] ([i915#3689]) > [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-tglb2/igt@kms_ccs@pipe-d-crc-primary-rotation-180-yf_tiled_ccs.html > > * igt@kms_chamelium@hdmi-mode-timings: > - shard-kbl: NOTRUN -> [SKIP][33] ([fdo#109271] / [fdo#111827]) +12 similar issues > [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl2/igt@kms_chamelium@hdmi-mode-timings.html > > * igt@kms_chamelium@vga-hpd-for-each-pipe: > - shard-skl: NOTRUN -> [SKIP][34] ([fdo#109271] / [fdo#111827]) +12 similar issues > [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl9/igt@kms_chamelium@vga-hpd-for-each-pipe.html > > * igt@kms_color@pipe-a-ctm-0-75: > - shard-skl: NOTRUN -> [DMESG-WARN][35] ([i915#1982]) > [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl8/igt@kms_color@pipe-a-ctm-0-75.html > > * igt@kms_color_chamelium@pipe-b-ctm-0-75: > - shard-tglb: NOTRUN -> [SKIP][36] ([fdo#109284] / [fdo#111827]) > [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-tglb2/igt@kms_color_chamelium@pipe-b-ctm-0-75.html > > * igt@kms_color_chamelium@pipe-b-ctm-max: > - shard-snb: NOTRUN -> [SKIP][37] ([fdo#109271] / [fdo#111827]) +8 similar issues > [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-snb5/igt@kms_color_chamelium@pipe-b-ctm-max.html > > * igt@kms_color_chamelium@pipe-c-ctm-0-25: > - shard-apl: NOTRUN -> [SKIP][38] ([fdo#109271] / [fdo#111827]) +6 similar issues > [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-apl8/igt@kms_color_chamelium@pipe-c-ctm-0-25.html > > * igt@kms_content_protection@atomic: > - shard-kbl: NOTRUN -> [TIMEOUT][39] ([i915#1319]) > [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl7/igt@kms_content_protection@atomic.html > > * igt@kms_cursor_crc@pipe-b-cursor-512x170-random: > - shard-tglb: NOTRUN -> [SKIP][40] ([fdo#109279] / [i915#3359]) > [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-tglb5/igt@kms_cursor_crc@pipe-b-cursor-512x170-random.html > > * igt@kms_cursor_crc@pipe-c-cursor-max-size-random: > - shard-tglb: NOTRUN -> [SKIP][41] ([i915#3359]) > [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-tglb5/igt@kms_cursor_crc@pipe-c-cursor-max-size-random.html > > * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: > - shard-tglb: NOTRUN -> [SKIP][42] ([fdo#111825]) +2 similar issues > [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-tglb5/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html > > * igt@kms_cursor_legacy@pipe-d-torture-bo: > - shard-kbl: NOTRUN -> [SKIP][43] ([fdo#109271] / [i915#533]) > [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl7/igt@kms_cursor_legacy@pipe-d-torture-bo.html > > * igt@kms_fbcon_fbt@fbc-suspend: > - shard-kbl: [PASS][44] -> [INCOMPLETE][45] ([i915#180] / [i915#636]) > [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html > [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl4/igt@kms_fbcon_fbt@fbc-suspend.html > > * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1: > - shard-skl: [PASS][46] -> [FAIL][47] ([i915#2122]) > [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-skl10/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html > [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html > > * igt@kms_flip@flip-vs-expired-vblank@a-edp1: > - shard-skl: [PASS][48] -> [FAIL][49] ([i915#79]) > [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-skl1/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html > [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl9/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html > > * igt@kms_flip@flip-vs-suspend-interruptible@a-dp1: > - shard-kbl: [PASS][50] -> [DMESG-WARN][51] ([i915#180]) +12 similar issues > [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html > [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible@a-dp1.html > > * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs: > - shard-skl: NOTRUN -> [SKIP][52] ([fdo#109271] / [i915#2672]) > [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl9/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs.html > > * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt: > - shard-snb: NOTRUN -> [SKIP][53] ([fdo#109271]) +147 similar issues > [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-snb5/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt.html > > * igt@kms_hdr@bpc-switch: > - shard-skl: NOTRUN -> [FAIL][54] ([i915#1188]) > [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl9/igt@kms_hdr@bpc-switch.html > > * igt@kms_pipe_crc_basic@hang-read-crc-pipe-d: > - shard-skl: NOTRUN -> [SKIP][55] ([fdo#109271] / [i915#533]) > [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl8/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html > > * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence: > - shard-apl: NOTRUN -> [SKIP][56] ([fdo#109271] / [i915#533]) > [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-apl6/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-d-frame-sequence.html > > * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes: > - shard-apl: [PASS][57] -> [DMESG-WARN][58] ([i915#180]) > [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-apl8/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html > [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html > > * igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb: > - shard-kbl: NOTRUN -> [FAIL][59] ([i915#265]) > [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl7/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html > > * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: > - shard-skl: NOTRUN -> [FAIL][60] ([fdo#108145] / [i915#265]) +1 similar issue > [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html > > * igt@kms_plane_alpha_blend@pipe-b-alpha-basic: > - shard-kbl: NOTRUN -> [FAIL][61] ([fdo#108145] / [i915#265]) +1 similar issue > [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl2/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html > > * igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb: > - shard-apl: NOTRUN -> [FAIL][62] ([fdo#108145] / [i915#265]) +1 similar issue > [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-apl3/igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb.html > > * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1: > - shard-skl: NOTRUN -> [SKIP][63] ([fdo#109271] / [i915#658]) +1 similar issue > [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl8/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area-1.html > > * igt@kms_psr2_sf@plane-move-sf-dmg-area-2: > - shard-apl: NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#658]) +1 similar issue > [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-apl6/igt@kms_psr2_sf@plane-move-sf-dmg-area-2.html > > * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5: > - shard-kbl: NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#658]) +3 similar issues > [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html > - shard-tglb: NOTRUN -> [SKIP][66] ([i915#2920]) > [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-tglb5/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-5.html > > * igt@kms_writeback@writeback-invalid-parameters: > - shard-apl: NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#2437]) > [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-apl3/igt@kms_writeback@writeback-invalid-parameters.html > > * igt@kms_writeback@writeback-pixel-formats: > - shard-skl: NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#2437]) +1 similar issue > [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl7/igt@kms_writeback@writeback-pixel-formats.html > > * igt@nouveau_crc@pipe-d-ctx-flip-skip-current-frame: > - shard-tglb: NOTRUN -> [SKIP][69] ([i915#2530]) > [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-tglb5/igt@nouveau_crc@pipe-d-ctx-flip-skip-current-frame.html > > * igt@perf_pmu@module-unload: > - shard-skl: [PASS][70] -> [DMESG-WARN][71] ([i915#1982] / [i915#262]) > [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-skl9/igt@perf_pmu@module-unload.html > [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl10/igt@perf_pmu@module-unload.html > > * igt@prime_nv_pcopy@test2: > - shard-kbl: NOTRUN -> [SKIP][72] ([fdo#109271]) +123 similar issues > [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl7/igt@prime_nv_pcopy@test2.html > > * igt@prime_vgem@fence-write-hang: > - shard-tglb: NOTRUN -> [SKIP][73] ([fdo#109295]) > [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-tglb5/igt@prime_vgem@fence-write-hang.html > > * igt@sysfs_clients@create: > - shard-kbl: NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#2994]) +1 similar issue > [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl7/igt@sysfs_clients@create.html > > * igt@sysfs_clients@split-50: > - shard-apl: NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#2994]) > [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-apl6/igt@sysfs_clients@split-50.html > > > #### Possible fixes #### > > * igt@drm_mm@all@bottomup: > - shard-skl: [INCOMPLETE][76] -> [PASS][77] > [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-skl10/igt@drm_mm@all@bottomup.html > [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl3/igt@drm_mm@all@bottomup.html > > * igt@gem_exec_fair@basic-deadline: > - shard-glk: [FAIL][78] ([i915#2846]) -> [PASS][79] > [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-glk6/igt@gem_exec_fair@basic-deadline.html > [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-glk9/igt@gem_exec_fair@basic-deadline.html > > * igt@gem_exec_fair@basic-none-share@rcs0: > - shard-apl: [SKIP][80] ([fdo#109271]) -> [PASS][81] > [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-apl2/igt@gem_exec_fair@basic-none-share@rcs0.html > [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-apl6/igt@gem_exec_fair@basic-none-share@rcs0.html > > * igt@gem_exec_fair@basic-none@vcs0: > - shard-kbl: [FAIL][82] ([i915#2842]) -> [PASS][83] +1 similar issue > [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-kbl2/igt@gem_exec_fair@basic-none@vcs0.html > [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl4/igt@gem_exec_fair@basic-none@vcs0.html > > * igt@gem_exec_fair@basic-pace-share@rcs0: > - shard-tglb: [FAIL][84] ([i915#2842]) -> [PASS][85] +2 similar issues > [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html > [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-tglb8/igt@gem_exec_fair@basic-pace-share@rcs0.html > > * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size: > - shard-skl: [FAIL][86] ([i915#2346] / [i915#533]) -> [PASS][87] > [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html > [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl10/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html > > * igt@kms_fbcon_fbt@fbc-suspend: > - shard-apl: [INCOMPLETE][88] ([i915#180] / [i915#1982]) -> [PASS][89] > [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-apl1/igt@kms_fbcon_fbt@fbc-suspend.html > [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-apl8/igt@kms_fbcon_fbt@fbc-suspend.html > > * igt@kms_frontbuffer_tracking@psr-suspend: > - shard-skl: [INCOMPLETE][90] ([i915#123]) -> [PASS][91] > [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-skl1/igt@kms_frontbuffer_tracking@psr-suspend.html > [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl9/igt@kms_frontbuffer_tracking@psr-suspend.html > > * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: > - shard-skl: [INCOMPLETE][92] ([i915#198]) -> [PASS][93] > [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-skl7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html > [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl8/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html > > * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes: > - shard-kbl: [DMESG-WARN][94] ([i915#180]) -> [PASS][95] +7 similar issues > [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-kbl3/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html > [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl1/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html > > * igt@kms_plane_alpha_blend@pipe-c-coverage-7efc: > - shard-skl: [FAIL][96] ([fdo#108145] / [i915#265]) -> [PASS][97] +2 similar issues > [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html > [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html > > * igt@perf@polling-parameterized: > - shard-glk: [FAIL][98] ([i915#1542]) -> [PASS][99] > [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-glk7/igt@perf@polling-parameterized.html > [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-glk2/igt@perf@polling-parameterized.html > - shard-skl: [FAIL][100] ([i915#1542]) -> [PASS][101] > [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-skl8/igt@perf@polling-parameterized.html > [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl2/igt@perf@polling-parameterized.html > > * igt@sysfs_preempt_timeout@timeout@vecs0: > - shard-skl: [FAIL][102] -> [PASS][103] > [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-skl10/igt@sysfs_preempt_timeout@timeout@vecs0.html > [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl5/igt@sysfs_preempt_timeout@timeout@vecs0.html > > > #### Warnings #### > > * igt@gem_exec_fair@basic-pace@rcs0: > - shard-kbl: [FAIL][104] ([i915#2842]) -> [FAIL][105] ([i915#2851]) > [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-kbl2/igt@gem_exec_fair@basic-pace@rcs0.html > [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl6/igt@gem_exec_fair@basic-pace@rcs0.html > > * igt@gem_exec_fair@basic-throttle@rcs0: > - shard-iclb: [FAIL][106] ([i915#2842]) -> [FAIL][107] ([i915#2849]) > [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html > [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html > > * igt@i915_pm_rc6_residency@rc6-fence: > - shard-iclb: [WARN][108] ([i915#1804] / [i915#2684]) -> [WARN][109] ([i915#2684]) > [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-iclb6/igt@i915_pm_rc6_residency@rc6-fence.html > [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-iclb8/igt@i915_pm_rc6_residency@rc6-fence.html > > * igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary: > - shard-skl: [INCOMPLETE][110] ([i915#123]) -> [SKIP][111] ([fdo#109271]) > [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-skl8/igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary.html > [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-skl2/igt@kms_frontbuffer_tracking@fbcpsr-indfb-scaledprimary.html > > * igt@runner@aborted: > - shard-kbl: ([FAIL][112], [FAIL][113], [FAIL][114], [FAIL][115], [FAIL][116], [FAIL][117], [FAIL][118], [FAIL][119]) ([i915#1436] / [i915#180] / [i915#1814] / [i915#3002] / [i915#3363] / [i915#4312] / [i915#602]) -> ([FAIL][120], [FAIL][121], [FAIL][122], [FAIL][123], [FAIL][124], [FAIL][125], [FAIL][126], [FAIL][127], [FAIL][128], [FAIL][129], [FAIL][130], [FAIL][131]) ([i915#180] / [i915#1814] / [i915#3002] / [i915#3363] / [i915#4312] / [i915#602] / [i915#92]) > [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-kbl6/igt@runner@aborted.html > [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-kbl6/igt@runner@aborted.html > [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-kbl4/igt@runner@aborted.html > [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-kbl6/igt@runner@aborted.html > [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-kbl1/igt@runner@aborted.html > [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-kbl6/igt@runner@aborted.html > [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-kbl6/igt@runner@aborted.html > [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-kbl3/igt@runner@aborted.html > [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl4/igt@runner@aborted.html > [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl6/igt@runner@aborted.html > [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl2/igt@runner@aborted.html > [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl4/igt@runner@aborted.html > [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl6/igt@runner@aborted.html > [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl4/igt@runner@aborted.html > [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl4/igt@runner@aborted.html > [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl3/igt@runner@aborted.html > [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl3/igt@runner@aborted.html > [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl3/igt@runner@aborted.html > [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl3/igt@runner@aborted.html > [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-kbl3/igt@runner@aborted.html > - shard-apl: ([FAIL][132], [FAIL][133], [FAIL][134]) ([i915#180] / [i915#3002] / [i915#3363] / [i915#4312]) -> ([FAIL][135], [FAIL][136], [FAIL][137]) ([i915#3002] / [i915#3363] / [i915#4312]) > [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-apl1/igt@runner@aborted.html > [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-apl1/igt@runner@aborted.html > [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10765/shard-apl6/igt@runner@aborted.html > [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-apl7/igt@runner@aborted.html > [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-apl1/igt@runner@aborted.html > [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/shard-apl6/igt@runner@aborted.html > > > [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 > [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 > [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279 > [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284 > [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295 > [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615 > [fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644 > [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 > [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 > [i915#1099]: https://gitlab.freedesktop.org/drm/intel/issues/1099 > [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 > [i915#123]: https://gitlab.freedesktop.org/drm/intel/issues/123 > [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319 > [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397 > [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 > [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542 > [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 > [i915#1804]: https://gitlab.freedesktop.org/drm/intel/issues/1804 > [i915#1814]: https://gitlab.freedesktop.org/drm/intel/issues/1814 > [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198 > [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 > [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122 > [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 > [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346 > [i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411 > [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437 > [i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530 > [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262 > [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 > [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658 > [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672 > [i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684 > [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842 > [i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846 > [i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849 > [i915#2851]: https://gitlab.freedesktop.org/drm/intel/issues/2851 > [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856 > [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920 > [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994 > [i915#3002] > > == Logs == > > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_21393/index.html ^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2021-10-21 19:00 UTC | newest] Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-10-20 19:51 [Intel-gfx] [PATCH v4 00/11] drm/i915: Simplify handling of modifiers Imre Deak 2021-10-20 19:51 ` [Intel-gfx] [PATCH v4 01/11] drm/i915: Add a table with a descriptor for all i915 modifiers Imre Deak 2021-10-21 10:14 ` Jani Nikula 2021-10-21 10:49 ` Imre Deak 2021-10-20 19:51 ` [Intel-gfx] [PATCH v4 02/11] drm/i915: Move intel_get_format_info() to intel_fb.c Imre Deak 2021-10-20 19:51 ` [Intel-gfx] [PATCH v4 03/11] drm/i915: Add tiling attribute to the modifier descriptor Imre Deak 2021-10-20 19:51 ` [Intel-gfx] [PATCH v4 04/11] drm/i915: Simplify the modifier check for interlaced scanout support Imre Deak 2021-10-20 19:51 ` [Intel-gfx] [PATCH v4 05/11] drm/i915: Unexport is_semiplanar_uv_plane() Imre Deak 2021-10-20 19:51 ` [Intel-gfx] [PATCH v4 06/11] drm/i915: Move intel_format_info_is_yuv_semiplanar() to intel_fb.c Imre Deak 2021-10-20 19:51 ` [Intel-gfx] [PATCH v4 07/11] drm/i915: Add a platform independent way to get the RC CCS CC plane Imre Deak 2021-10-20 19:51 ` [Intel-gfx] [PATCH v4 08/11] drm/i915: Handle CCS CC planes separately from CCS AUX planes Imre Deak 2021-10-20 19:51 ` [Intel-gfx] [PATCH v4 09/11] drm/i915: Add a platform independent way to check for " Imre Deak 2021-10-20 19:51 ` [Intel-gfx] [PATCH v4 10/11] drm/i915: Move is_ccs_modifier() to intel_fb.c Imre Deak 2021-10-20 19:51 ` [Intel-gfx] [PATCH v4 11/11] drm/i915: Add functions to check for RC CCS CC and MC CCS modifiers Imre Deak 2021-10-20 20:22 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Simplify handling of modifiers (rev12) Patchwork 2021-10-20 20:24 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2021-10-20 20:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-10-21 0:34 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork 2021-10-21 19:00 ` Imre Deak
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.